Merge branch 'pxa' into devel

[pandora-kernel.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 699b899..7868f4d 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -322,7 +322,7 @@ config CPU_SA1100
 # XScale
 config CPU_XSCALE
        bool
-       depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
+       depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
        default y
        select CPU_32v5
        select CPU_ABRT_EV5T
@@ -333,7 +333,7 @@ config CPU_XSCALE
 # XScale Core Version 3
 config CPU_XSC3
        bool
-       depends on ARCH_IXP23XX || ARCH_IOP13XX
+       depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
        default y
        select CPU_32v5
        select CPU_ABRT_EV5T
@@ -352,7 +352,7 @@ config CPU_V6
        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
-       select CPU_HAS_ASID
+       select CPU_HAS_ASID if MMU
        select CPU_COPY_V6 if MMU
        select CPU_TLB_V6 if MMU
 
@@ -378,7 +378,7 @@ config CPU_V7
        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
-       select CPU_HAS_ASID
+       select CPU_HAS_ASID if MMU
        select CPU_COPY_V6 if MMU
        select CPU_TLB_V7 if MMU
 
@@ -406,6 +406,7 @@ config CPU_32v5
 
 config CPU_32v6
        bool
+       select TLS_REG_EMUL if !CPU_32v6K && !MMU
 
 config CPU_32v7
        bool
@@ -599,7 +600,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -612,12 +613,6 @@ config CPU_CACHE_ROUND_ROBIN
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.
 
-config CPU_L2CACHE_DISABLE
-       bool "Disable level 2 cache"
-       depends on CPU_V7
-       help
-         Say Y here to disable the level 2 cache.  If unsure, say N.
-
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7