Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid

[pandora-kernel.git] / arch / arm / mach-orion5x / irq.c

diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b9..b1b45ff 100644 (file)
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -9,12 +9,11 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-
+#include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/gpio.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"
@@ -28,29 +27,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init orion5x_init_irq(void)
 {
-       int i;
-
        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
 
        /*
-        * Mask and clear GPIO IRQ interrupts
-        */
-       writel(0x0, GPIO_LEVEL_MASK(0));
-       writel(0x0, GPIO_EDGE_MASK(0));
-       writel(0x0, GPIO_EDGE_CAUSE(0));
-
-       /*
-        * Register chained level handlers for GPIO IRQs by default.
-        * User can use set_type() if he wants to use edge types handlers.
+        * Initialize gpiolib for GPIOs 0-31.
         */
-       for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
-               set_irq_chip(i, &orion_gpio_irq_chip);
-               set_irq_handler(i, handle_level_irq);
-               irq_desc[i].status |= IRQ_LEVEL;
-               set_irq_flags(i, IRQF_VALID);
-       }
-       set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
-       set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
-       set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
-       set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
+       orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
+       irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
+       irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
+       irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
+       irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
 }