#include "prm-regbits-44xx.h"
#include "prm44xx.h"
-/*
- * Channel configuration bits, common for OMAP3 & 4
+/**
+ * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
+ * @sa: bit for slave address
+ * @rav: bit for voltage configuration register
+ * @rac: bit for command configuration register
+ * @racen: enable bit for RAC
+ * @cmd: bit for command value set selection
+ *
+ * Channel configuration bits, common for OMAP3+
* OMAP3 register: PRM_VC_CH_CONF
* OMAP4 register: PRM_VC_CFG_CHANNEL
+ * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
+ */
+struct omap_vc_channel_cfg {
+ u8 sa;
+ u8 rav;
+ u8 rac;
+ u8 racen;
+ u8 cmd;
+};
+
+static struct omap_vc_channel_cfg vc_default_channel_cfg = {
+ .sa = BIT(0),
+ .rav = BIT(1),
+ .rac = BIT(2),
+ .racen = BIT(3),
+ .cmd = BIT(4),
+};
+
+/*
+ * On OMAP3+, all VC channels have the above default bitfield
+ * configuration, except the OMAP4 MPU channel. This appears
+ * to be a freak accident as every other VC channel has the
+ * default configuration, thus creating a mutant channel config.
*/
-#define CFG_CHANNEL_SA BIT(0)
-#define CFG_CHANNEL_RAV BIT(1)
-#define CFG_CHANNEL_RAC BIT(2)
-#define CFG_CHANNEL_RACEN BIT(3)
-#define CFG_CHANNEL_CMD BIT(4)
-#define CFG_CHANNEL_MASK 0x3f
+static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
+ .sa = BIT(0),
+ .rav = BIT(2),
+ .rac = BIT(3),
+ .racen = BIT(4),
+ .cmd = BIT(1),
+};
+
+static struct omap_vc_channel_cfg *vc_cfg_bits;
+#define CFG_CHANNEL_MASK 0x1f
/**
* omap_vc_config_channel - configure VC channel to PMIC mappings
* All others must stay at zero (see function comment above.)
*/
if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
- vc->cfg_channel &= CFG_CHANNEL_RACEN;
+ vc->cfg_channel &= vc_cfg_bits->racen;
voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
vc->cfg_channel << vc->cfg_channel_sa_shift,
- vc->common->cfg_channel_reg);
+ vc->cfg_channel_reg);
return 0;
}
u8 *target_vsel, u8 *current_vsel)
{
struct omap_vc_channel *vc = voltdm->vc;
- struct omap_vdd_info *vdd = voltdm->vdd;
- struct omap_volt_data *volt_data;
- const struct omap_vp_common_data *vp_common;
- u32 vc_cmdval, vp_errgain_val;
-
- vp_common = vdd->vp_data->vp_common;
+ u32 vc_cmdval;
/* Check if sufficient pmic info is available for this vdd */
if (!voltdm->pmic) {
return -EINVAL;
}
- /* Get volt_data corresponding to target_volt */
- volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
- if (IS_ERR(volt_data))
- volt_data = NULL;
-
*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
- *current_vsel = voltdm->read(vdd->vp_data->voltage);
+ *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
/* Setting the ON voltage to the new target voltage */
vc_cmdval = voltdm->read(vc->cmdval_reg);
vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
voltdm->write(vc_cmdval, vc->cmdval_reg);
- /* Setting vp errorgain based on the voltage */
- if (volt_data) {
- vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
- vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
- vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
- vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
- vp_common->vpconfig_errorgain_shift;
- voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
- }
+ omap_vp_update_errorgain(voltdm, target_volt);
return 0;
}
unsigned long target_volt,
u8 target_vsel, u8 current_vsel)
{
- struct omap_vdd_info *vdd = voltdm->vdd;
u32 smps_steps = 0, smps_delay = 0;
smps_steps = abs(target_vsel - current_vsel);
smps_delay = ((smps_steps * voltdm->pmic->step_size) /
voltdm->pmic->slew_rate) + 2;
udelay(smps_delay);
-
- vdd->curr_volt = target_volt;
}
/* vc_bypass_scale - VC bypass method of voltage scaling */
}
vc->cfg_channel = 0;
+ if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
+ vc_cfg_bits = &vc_mutant_channel_cfg;
+ else
+ vc_cfg_bits = &vc_default_channel_cfg;
/* get PMIC/board specific settings */
vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
/* Configure the i2c slave address for this VC */
voltdm->rmw(vc->smps_sa_mask,
vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
- vc->common->smps_sa_reg);
- vc->cfg_channel |= CFG_CHANNEL_SA;
+ vc->smps_sa_reg);
+ vc->cfg_channel |= vc_cfg_bits->sa;
/*
* Configure the PMIC register addresses.
*/
voltdm->rmw(vc->smps_volra_mask,
vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
- vc->common->smps_volra_reg);
- vc->cfg_channel |= CFG_CHANNEL_RAV;
+ vc->smps_volra_reg);
+ vc->cfg_channel |= vc_cfg_bits->rav;
if (vc->cmd_reg_addr) {
voltdm->rmw(vc->smps_cmdra_mask,
vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
- vc->common->smps_cmdra_reg);
- vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
+ vc->smps_cmdra_reg);
+ vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
}
/* Set up the on, inactive, retention and off voltage */
(ret_vsel << vc->common->cmd_ret_shift) |
(off_vsel << vc->common->cmd_off_shift));
voltdm->write(val, vc->cmdval_reg);
- vc->cfg_channel |= CFG_CHANNEL_CMD;
+ vc->cfg_channel |= vc_cfg_bits->cmd;
/* Channel configuration */
omap_vc_config_channel(voltdm);
git.openpandora.org / pandora-kernel.git / blobdiff