Merge branch 'packaging' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek...

[pandora-kernel.git] / arch / arm / mach-omap2 / prcm.c

diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 68c541f..679bcd2 100644 (file)
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,7 +17,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/module.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -30,10 +31,9 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm2xxx_3xxx.h"
-#include "cm44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
-#include "prcm44xx.h"
+#include "prminst44xx.h"
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-44xx.h"
 #include "control.h"
@@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void)
 {
        /* XXX This presumably needs modification for 34XX */
        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-               return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+               return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
        if (cpu_is_omap44xx())
-               return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+               return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 
        return 0;
 }
@@ -74,10 +74,38 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
                WARN_ON(1);
        }
 
+       /*
+        * As per Errata i520, in some cases, user will not be able to
+        * access DDR memory after warm-reset.
+        * This situation occurs while the warm-reset happens during a read
+        * access to DDR memory. In that particular condition, DDR memory
+        * does not respond to a corrupted read command due to the warm
+        * reset occurrence but SDRC is waiting for read completion.
+        * SDRC is not sensitive to the warm reset, but the interconnect is
+        * reset on the fly, thus causing a misalignment between SDRC logic,
+        * interconnect logic and DDR memory state.
+        * WORKAROUND:
+        * Steps to perform before a Warm reset is trigged:
+        * 1. enable self-refresh on idle request
+        * 2. put SDRC in idle
+        * 3. wait until SDRC goes to idle
+        * 4. generate SW reset (Global SW reset)
+        *
+        * Steps to be performed after warm reset occurs (in bootloader):
+        * if HW warm reset is the source, apply below steps before any
+        * accesses to SDRAM:
+        * 1. Reset SMS and SDRC and wait till reset is complete
+        * 2. Re-initialize SMS, SDRC and memory
+        *
+        * NOTE: Above work around is required only if arch reset is implemented
+        * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+        * the WA since it resets SDRC as well as part of cold reset.
+        */
+
        /* XXX should be moved to some OMAP2/3 specific code */
-       prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                            OMAP2_RM_RSTCTRL);
-       prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
+       omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+                                  OMAP2_RM_RSTCTRL);
+       omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 }
 
 /**