static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
-static struct powerdomain *cam_pwrdm;
static inline void omap3_per_save_context(void)
{
int core_prev_state, per_prev_state;
u32 sdrc_pwr = 0;
- pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
- pwrdm_clear_all_prev_pwrst(neon_pwrdm);
- pwrdm_clear_all_prev_pwrst(core_pwrdm);
- pwrdm_clear_all_prev_pwrst(per_pwrdm);
-
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
switch (mpu_next_state) {
case PWRDM_POWER_ON:
if (!console_trylock())
goto console_still_active;
- pwrdm_pre_transition();
+ if (mpu_next_state < PWRDM_POWER_ON)
+ pwrdm_pre_transition(mpu_pwrdm);
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
+ pwrdm_pre_transition(per_pwrdm);
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
omap_uart_prepare_idle(2);
omap_uart_prepare_idle(3);
if (core_next_state < PWRDM_POWER_ON) {
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
+ pwrdm_pre_transition(core_pwrdm);
if (core_next_state == PWRDM_POWER_OFF) {
omap3_core_save_context();
omap3_cm_save_context();
}
omap_uart_resume_idle(0);
omap_uart_resume_idle(1);
- if (core_next_state == PWRDM_POWER_OFF)
- omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTCTRL_OFFSET);
+ pwrdm_post_transition(core_pwrdm);
}
omap3_intc_resume_idle();
- pwrdm_post_transition();
-
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
omap3_per_restore_context();
omap_uart_resume_idle(2);
omap_uart_resume_idle(3);
+ pwrdm_post_transition(per_pwrdm);
}
if (!is_suspending())
omap3_disable_io_chain();
}
- clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
-}
-
-int omap3_can_sleep(void)
-{
- if (!omap_uart_can_sleep())
- return 0;
- return 1;
+ if (mpu_next_state < PWRDM_POWER_ON)
+ pwrdm_post_transition(mpu_pwrdm);
}
static void omap3_pm_idle(void)
{
local_irq_disable();
- local_fiq_disable();
-
- if (!omap3_can_sleep())
- goto out;
if (omap_irq_pending() || need_resched())
goto out;
trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
out:
- local_fiq_enable();
local_irq_enable();
}
omap3_iva_idle();
omap3_d2d_idle();
+
+ /* enable sys_clkreq signalling */
+ omap2_prm_rmw_mod_reg_bits((OMAP3430_AUTO_OFF_MASK | OMAP3430_AUTO_RET_MASK
+ | OMAP3430_AUTO_SLEEP_MASK), OMAP3430_AUTO_RET_MASK,
+ OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET);
}
void omap3_pm_off_mode_enable(int enable)
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
per_pwrdm = pwrdm_lookup("per_pwrdm");
core_pwrdm = pwrdm_lookup("core_pwrdm");
- cam_pwrdm = pwrdm_lookup("cam_pwrdm");
neon_clkdm = clkdm_lookup("neon_clkdm");
mpu_clkdm = clkdm_lookup("mpu_clkdm");
"allocating for secure sram context\n");
local_irq_disable();
- local_fiq_disable();
omap_dma_global_context_save();
omap3_save_secure_ram_context();
omap_dma_global_context_restore();
local_irq_enable();
- local_fiq_enable();
}
omap3_save_scratchpad_contents();