ARM: OMAP: TI814X: Add cpu type macros and detection support

[pandora-kernel.git] / arch / arm / mach-omap2 / clock3xxx_data.c

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index b9b8446..60424f4 100644 (file)
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3464,6 +3464,30 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
+       CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
+       CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
+       CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
 };
 
 
@@ -3472,7 +3496,16 @@ int __init omap3xxx_clk_init(void)
        struct omap_clk *c;
        u32 cpu_clkflg = 0;
 
-       if (cpu_is_omap3517()) {
+       /*
+        * 3505 must be tested before 3517, since 3517 returns true
+        * for both AM3517 chips and AM3517 family chips, which
+        * includes 3505.  Unfortunately there's no obvious family
+        * test for 3517/3505 :-(
+        */
+       if (cpu_is_omap3505()) {
+               cpu_mask = RATE_IN_34XX;
+               cpu_clkflg = CK_3505;
+       } else if (cpu_is_omap3517()) {
                cpu_mask = RATE_IN_34XX;
                cpu_clkflg = CK_3517;
        } else if (cpu_is_omap3505()) {
@@ -3484,6 +3517,10 @@ int __init omap3xxx_clk_init(void)
        } else if (cpu_is_ti816x()) {
                cpu_mask = RATE_IN_TI816X;
                cpu_clkflg = CK_TI816X;
+       } else if (cpu_is_am33xx()) {
+               cpu_mask = RATE_IN_AM33XX;
+       } else if (cpu_is_ti814x()) {
+               cpu_mask = RATE_IN_TI814X;
        } else if (cpu_is_omap34xx()) {
                if (omap_rev() == OMAP3430_REV_ES1_0) {
                        cpu_mask = RATE_IN_3430ES1;
@@ -3567,7 +3604,7 @@ int __init omap3xxx_clk_init(void)
         * Lock DPLL5 -- here only until other device init code can
         * handle this
         */
-       if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+       if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
                omap3_clk_lock_dpll5();
 
        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */