CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
- CLK("omap_timer.1", "fck", &gpt1_fck, CK_3XXX),
- CLK("omap_timer.2", "fck", &gpt2_fck, CK_3XXX),
- CLK("omap_timer.3", "fck", &gpt3_fck, CK_3XXX),
- CLK("omap_timer.4", "fck", &gpt4_fck, CK_3XXX),
- CLK("omap_timer.5", "fck", &gpt5_fck, CK_3XXX),
- CLK("omap_timer.6", "fck", &gpt6_fck, CK_3XXX),
- CLK("omap_timer.7", "fck", &gpt7_fck, CK_3XXX),
- CLK("omap_timer.8", "fck", &gpt8_fck, CK_3XXX),
- CLK("omap_timer.9", "fck", &gpt9_fck, CK_3XXX),
- CLK("omap_timer.10", "fck", &gpt10_fck, CK_3XXX),
- CLK("omap_timer.11", "fck", &gpt11_fck, CK_3XXX),
- CLK("omap_timer.12", "fck", &gpt12_fck, CK_3XXX),
CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
+ } else if (cpu_is_am33xx()) {
+ cpu_mask = RATE_IN_AM33XX;
+ } else if (cpu_is_ti814x()) {
+ cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
- if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */