git.openpandora.org / pandora-kernel.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[pandora-kernel.git] / arch / arm / mach-omap2 / clock24xx.h
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index b59bf90..33c3e5b 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,13 +24,13 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 
-static void omap2_table_mpu_recalc(struct clk *clk);
+static unsigned long omap2_table_mpu_recalc(struct clk *clk);
 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_osc_clk_recalc(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_dpllcore_recalc(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_osc_clk_recalc(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_dpllcore_recalc(struct clk *clk);
 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -621,18 +621,14 @@ static struct clk func_32k_ck = {
        .name           = "func_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32000,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_FIXED | RATE_PROPAGATES,
+       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
-       .recalc         = &propagate_rate,
 };
 
 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 static struct clk osc_ck = {           /* (*12, *13, 19.2, *26, 38.4)MHz */
        .name           = "osc_ck",
        .ops            = &clkops_oscck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_osc_clk_recalc,
 };
@@ -642,8 +638,6 @@ static struct clk sys_ck = {                /* (*12, *13, 19.2, 26, 38.4)MHz */
        .name           = "sys_ck",             /* ~ ref_clk also */
        .ops            = &clkops_null,
        .parent         = &osc_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_sys_clk_recalc,
 };
@@ -652,10 +646,8 @@ static struct clk alt_ck = {               /* Typical 54M or 48M, may not exist */
        .name           = "alt_ck",
        .ops            = &clkops_null,
        .rate           = 54000000,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_FIXED | RATE_PROPAGATES,
+       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
-       .recalc         = &propagate_rate,
 };
 
 /*
@@ -671,7 +663,12 @@ static struct dpll_data dpll_dd = {
        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+       .clk_bypass             = &sys_ck,
+       .clk_ref                = &sys_ck,
+       .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_mask            = OMAP24XX_EN_DPLL_MASK,
        .max_multiplier         = 1024,
+       .min_divider            = 1,
        .max_divider            = 16,
        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -685,8 +682,6 @@ static struct clk dpll_ck = {
        .ops            = &clkops_null,
        .parent         = &sys_ck,              /* Can be func_32k also */
        .dpll_data      = &dpll_dd,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_dpllcore_recalc,
        .set_rate       = &omap2_reprogram_dpllcore,
@@ -697,12 +692,10 @@ static struct clk apll96_ck = {
        .ops            = &clkops_fixed,
        .parent         = &sys_ck,
        .rate           = 96000000,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+       .flags          = RATE_FIXED | ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
-       .recalc         = &propagate_rate,
 };
 
 static struct clk apll54_ck = {
@@ -710,12 +703,10 @@ static struct clk apll54_ck = {
        .ops            = &clkops_fixed,
        .parent         = &sys_ck,
        .rate           = 54000000,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+       .flags          = RATE_FIXED | ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
-       .recalc         = &propagate_rate,
 };
 
 /*
@@ -744,8 +735,6 @@ static struct clk func_54m_ck = {
        .name           = "func_54m_ck",
        .ops            = &clkops_null,
        .parent         = &apll54_ck,   /* can also be alt_clk */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -758,8 +747,6 @@ static struct clk core_ck = {
        .name           = "core_ck",
        .ops            = &clkops_null,
        .parent         = &dpll_ck,             /* can also be 32k */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -786,8 +773,6 @@ static struct clk func_96m_ck = {
        .name           = "func_96m_ck",
        .ops            = &clkops_null,
        .parent         = &apll96_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -820,8 +805,6 @@ static struct clk func_48m_ck = {
        .name           = "func_48m_ck",
        .ops            = &clkops_null,
        .parent         = &apll96_ck,    /* 96M or Alt */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -837,8 +820,6 @@ static struct clk func_12m_ck = {
        .ops            = &clkops_null,
        .parent         = &func_48m_ck,
        .fixed_div      = 4,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -848,7 +829,6 @@ static struct clk wdt1_osc_ck = {
        .name           = "ck_wdt1_osc",
        .ops            = &clkops_null, /* RMK: missing? */
        .parent         = &osc_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .recalc         = &followparent_recalc,
 };
 
@@ -890,10 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = {
 
 static struct clk sys_clkout_src = {
        .name           = "sys_clkout_src",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &func_54m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -924,7 +902,6 @@ static struct clk sys_clkout = {
        .name           = "sys_clkout",
        .ops            = &clkops_null,
        .parent         = &sys_clkout_src,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "wkup_clkdm",
        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
@@ -937,9 +914,8 @@ static struct clk sys_clkout = {
 /* In 2430, new in 2420 ES2 */
 static struct clk sys_clkout2_src = {
        .name           = "sys_clkout2_src",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &func_54m_ck,
-       .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -962,7 +938,6 @@ static struct clk sys_clkout2 = {
        .name           = "sys_clkout2",
        .ops            = &clkops_null,
        .parent         = &sys_clkout2_src,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "wkup_clkdm",
        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
@@ -974,9 +949,8 @@ static struct clk sys_clkout2 = {
 
 static struct clk emul_ck = {
        .name           = "emul_ck",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &func_54m_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1012,9 +986,7 @@ static struct clk mpu_ck = {       /* Control cpu */
        .name           = "mpu_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP |
-                               CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "mpu_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1056,8 +1028,7 @@ static struct clk dsp_fck = {
        .name           = "dsp_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
-                               CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "dsp_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1087,8 +1058,7 @@ static struct clk dsp_irate_ick = {
        .name           = "dsp_irate_ick",
        .ops            = &clkops_null,
        .parent         = &dsp_fck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
-                               CONFIG_PARTICIPANT,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
        .clksel         = dsp_irate_ick_clksel,
@@ -1102,7 +1072,7 @@ static struct clk dsp_ick = {
        .name           = "dsp_ick",     /* apparently ipi and isp */
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dsp_irate_ick,
-       .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 };
@@ -1112,7 +1082,7 @@ static struct clk iva2_1_ick = {
        .name           = "iva2_1_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &dsp_irate_ick,
-       .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 };
@@ -1126,8 +1096,7 @@ static struct clk iva1_ifck = {
        .name           = "iva1_ifck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
-                               RATE_PROPAGATES | DELAYED_APP,
+       .flags          = CONFIG_PARTICIPANT | DELAYED_APP,
        .clkdm_name     = "iva1_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1144,7 +1113,6 @@ static struct clk iva1_mpu_int_ifck = {
        .name           = "iva1_mpu_int_ifck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &iva1_ifck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "iva1_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1191,9 +1159,7 @@ static struct clk core_l3_ck = {  /* Used for ick and fck, interconnect */
        .name           = "core_l3_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP |
-                               CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "core_l3_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
@@ -1221,8 +1187,7 @@ static struct clk usb_l4_ick = {  /* FS-USB interface clock */
        .name           = "usb_l4_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP | CONFIG_PARTICIPANT,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
@@ -1256,8 +1221,7 @@ static struct clk l4_ck = {               /* used both as an ick and fck */
        .name           = "l4_ck",
        .ops            = &clkops_null,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP | RATE_PROPAGATES,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "core_l4_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
@@ -1295,8 +1259,7 @@ static struct clk ssi_ssr_sst_fck = {
        .name           = "ssi_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
@@ -1308,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = {
        .set_rate       = &omap2_clksel_set_rate
 };
 
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+       .name           = "ssi_l4_ick",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &l4_ck,
+       .clkdm_name     = "core_l4_clkdm",
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+       .recalc         = &followparent_recalc,
+};
+
 
 /*
  * GFX clock domain
@@ -1332,7 +1309,6 @@ static struct clk gfx_3d_fck = {
        .name           = "gfx_3d_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "gfx_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
@@ -1348,7 +1324,6 @@ static struct clk gfx_2d_fck = {
        .name           = "gfx_2d_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "gfx_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
@@ -1364,7 +1339,6 @@ static struct clk gfx_ick = {
        .name           = "gfx_ick",            /* From l3 */
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "gfx_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
        .enable_bit     = OMAP_EN_GFX_SHIFT,
@@ -1395,7 +1369,7 @@ static struct clk mdm_ick = {             /* used both as a ick and fck */
        .name           = "mdm_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "mdm_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1411,7 +1385,6 @@ static struct clk mdm_osc_ck = {
        .name           = "mdm_osc_ck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &osc_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "mdm_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
@@ -1455,9 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {          /* Enables both L3,L4 ICLK's */
        .name           = "dss_ick",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &l4_ck,       /* really both l3 and l4 */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "dss_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
@@ -1466,10 +1438,9 @@ static struct clk dss_ick = {            /* Enables both L3,L4 ICLK's */
 
 static struct clk dss1_fck = {
        .name           = "dss1_fck",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &core_ck,             /* Core or sys */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "dss_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
@@ -1500,10 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = {
 
 static struct clk dss2_fck = {         /* Alt clk used in power management */
        .name           = "dss2_fck",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "dss_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
@@ -1518,7 +1488,6 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
        .name           = "dss_54m_fck",        /* 54m tv clk */
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_54m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "dss_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
@@ -1547,7 +1516,6 @@ static struct clk gpt1_ick = {
        .name           = "gpt1_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
@@ -1558,7 +1526,6 @@ static struct clk gpt1_fck = {
        .name           = "gpt1_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
@@ -1575,7 +1542,6 @@ static struct clk gpt2_ick = {
        .name           = "gpt2_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
@@ -1586,7 +1552,6 @@ static struct clk gpt2_fck = {
        .name           = "gpt2_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
@@ -1601,7 +1566,6 @@ static struct clk gpt3_ick = {
        .name           = "gpt3_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
@@ -1612,7 +1576,6 @@ static struct clk gpt3_fck = {
        .name           = "gpt3_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
@@ -1627,7 +1590,6 @@ static struct clk gpt4_ick = {
        .name           = "gpt4_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
@@ -1638,7 +1600,6 @@ static struct clk gpt4_fck = {
        .name           = "gpt4_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
@@ -1653,7 +1614,6 @@ static struct clk gpt5_ick = {
        .name           = "gpt5_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
@@ -1664,7 +1624,6 @@ static struct clk gpt5_fck = {
        .name           = "gpt5_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
@@ -1679,7 +1638,6 @@ static struct clk gpt6_ick = {
        .name           = "gpt6_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
@@ -1690,7 +1648,6 @@ static struct clk gpt6_fck = {
        .name           = "gpt6_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
@@ -1705,7 +1662,6 @@ static struct clk gpt7_ick = {
        .name           = "gpt7_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
        .recalc         = &followparent_recalc,
@@ -1715,7 +1671,6 @@ static struct clk gpt7_fck = {
        .name           = "gpt7_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
@@ -1730,7 +1685,6 @@ static struct clk gpt8_ick = {
        .name           = "gpt8_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
@@ -1741,7 +1695,6 @@ static struct clk gpt8_fck = {
        .name           = "gpt8_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
@@ -1756,7 +1709,6 @@ static struct clk gpt9_ick = {
        .name           = "gpt9_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
@@ -1767,7 +1719,6 @@ static struct clk gpt9_fck = {
        .name           = "gpt9_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
@@ -1782,7 +1733,6 @@ static struct clk gpt10_ick = {
        .name           = "gpt10_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
@@ -1793,7 +1743,6 @@ static struct clk gpt10_fck = {
        .name           = "gpt10_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
@@ -1808,7 +1757,6 @@ static struct clk gpt11_ick = {
        .name           = "gpt11_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
@@ -1819,7 +1767,6 @@ static struct clk gpt11_fck = {
        .name           = "gpt11_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
@@ -1834,7 +1781,6 @@ static struct clk gpt12_ick = {
        .name           = "gpt12_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
@@ -1845,7 +1791,6 @@ static struct clk gpt12_fck = {
        .name           = "gpt12_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
@@ -1861,7 +1806,6 @@ static struct clk mcbsp1_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1873,7 +1817,6 @@ static struct clk mcbsp1_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1885,7 +1828,6 @@ static struct clk mcbsp2_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1897,7 +1839,6 @@ static struct clk mcbsp2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1909,7 +1850,6 @@ static struct clk mcbsp3_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 3,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1921,7 +1861,6 @@ static struct clk mcbsp3_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 3,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1933,7 +1872,6 @@ static struct clk mcbsp4_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 4,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1945,7 +1883,6 @@ static struct clk mcbsp4_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 4,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1957,7 +1894,6 @@ static struct clk mcbsp5_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 5,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1969,7 +1905,6 @@ static struct clk mcbsp5_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 5,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1982,7 +1917,6 @@ static struct clk mcspi1_ick = {
        .id             = 1,
        .parent         = &l4_ck,
        .clkdm_name     = "core_l4_clkdm",
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
        .recalc         = &followparent_recalc,
@@ -1993,7 +1927,6 @@ static struct clk mcspi1_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -2005,7 +1938,6 @@ static struct clk mcspi2_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -2017,7 +1949,6 @@ static struct clk mcspi2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -2029,7 +1960,6 @@ static struct clk mcspi3_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 3,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
@@ -2041,7 +1971,6 @@ static struct clk mcspi3_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 3,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
@@ -2052,7 +1981,6 @@ static struct clk uart1_ick = {
        .name           = "uart1_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
@@ -2063,7 +1991,6 @@ static struct clk uart1_fck = {
        .name           = "uart1_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
@@ -2074,7 +2001,6 @@ static struct clk uart2_ick = {
        .name           = "uart2_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
@@ -2085,7 +2011,6 @@ static struct clk uart2_fck = {
        .name           = "uart2_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
@@ -2096,7 +2021,6 @@ static struct clk uart3_ick = {
        .name           = "uart3_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
@@ -2107,7 +2031,6 @@ static struct clk uart3_fck = {
        .name           = "uart3_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
@@ -2118,7 +2041,6 @@ static struct clk gpios_ick = {
        .name           = "gpios_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2129,7 +2051,6 @@ static struct clk gpios_fck = {
        .name           = "gpios_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2140,7 +2061,6 @@ static struct clk mpu_wdt_ick = {
        .name           = "mpu_wdt_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2151,7 +2071,6 @@ static struct clk mpu_wdt_fck = {
        .name           = "mpu_wdt_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2162,8 +2081,7 @@ static struct clk sync_32k_ick = {
        .name           = "sync_32k_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2174,7 +2092,6 @@ static struct clk wdt1_ick = {
        .name           = "wdt1_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
@@ -2185,8 +2102,7 @@ static struct clk omapctrl_ick = {
        .name           = "omapctrl_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2197,7 +2113,6 @@ static struct clk icr_ick = {
        .name           = "icr_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
@@ -2206,9 +2121,8 @@ static struct clk icr_ick = {
 
 static struct clk cam_ick = {
        .name           = "cam_ick",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
@@ -2222,9 +2136,8 @@ static struct clk cam_ick = {
  */
 static struct clk cam_fck = {
        .name           = "cam_fck",
-       .ops            = &clkops_omap2_dflt_wait,
+       .ops            = &clkops_omap2_dflt,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
@@ -2235,7 +2148,6 @@ static struct clk mailboxes_ick = {
        .name           = "mailboxes_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2246,7 +2158,6 @@ static struct clk wdt4_ick = {
        .name           = "wdt4_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
@@ -2257,7 +2168,6 @@ static struct clk wdt4_fck = {
        .name           = "wdt4_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
@@ -2268,7 +2178,6 @@ static struct clk wdt3_ick = {
        .name           = "wdt3_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
@@ -2279,7 +2188,6 @@ static struct clk wdt3_fck = {
        .name           = "wdt3_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
@@ -2290,7 +2198,6 @@ static struct clk mspro_ick = {
        .name           = "mspro_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2301,7 +2208,6 @@ static struct clk mspro_fck = {
        .name           = "mspro_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2312,7 +2218,6 @@ static struct clk mmc_ick = {
        .name           = "mmc_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
@@ -2323,7 +2228,6 @@ static struct clk mmc_fck = {
        .name           = "mmc_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
@@ -2334,7 +2238,6 @@ static struct clk fac_ick = {
        .name           = "fac_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
@@ -2345,7 +2248,6 @@ static struct clk fac_fck = {
        .name           = "fac_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_12m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
@@ -2356,7 +2258,6 @@ static struct clk eac_ick = {
        .name           = "eac_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
@@ -2367,7 +2268,6 @@ static struct clk eac_fck = {
        .name           = "eac_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
@@ -2378,7 +2278,6 @@ static struct clk hdq_ick = {
        .name           = "hdq_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
@@ -2389,7 +2288,6 @@ static struct clk hdq_fck = {
        .name           = "hdq_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_12m_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
@@ -2401,7 +2299,6 @@ static struct clk i2c2_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
@@ -2413,7 +2310,6 @@ static struct clk i2c2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &func_12m_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
@@ -2425,7 +2321,6 @@ static struct clk i2chs2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 2,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2437,7 +2332,6 @@ static struct clk i2c1_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
@@ -2449,7 +2343,6 @@ static struct clk i2c1_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_12m_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
@@ -2461,7 +2354,6 @@ static struct clk i2chs1_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2472,8 +2364,7 @@ static struct clk gpmc_fck = {
        .name           = "gpmc_fck",
        .ops            = &clkops_null, /* RMK: missing? */
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "core_l3_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -2482,7 +2373,6 @@ static struct clk sdma_fck = {
        .name           = "sdma_fck",
        .ops            = &clkops_null, /* RMK: missing? */
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l3_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -2491,7 +2381,6 @@ static struct clk sdma_ick = {
        .name           = "sdma_ick",
        .ops            = &clkops_null, /* RMK: missing? */
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l3_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -2500,7 +2389,6 @@ static struct clk vlynq_ick = {
        .name           = "vlynq_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2536,7 +2424,7 @@ static struct clk vlynq_fck = {
        .name           = "vlynq_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2553,7 +2441,7 @@ static struct clk sdrc_ick = {
        .name           = "sdrc_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
@@ -2564,7 +2452,6 @@ static struct clk des_ick = {
        .name           = "des_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
@@ -2575,7 +2462,6 @@ static struct clk sha_ick = {
        .name           = "sha_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
@@ -2586,7 +2472,6 @@ static struct clk rng_ick = {
        .name           = "rng_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
@@ -2597,7 +2482,6 @@ static struct clk aes_ick = {
        .name           = "aes_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
@@ -2608,7 +2492,6 @@ static struct clk pka_ick = {
        .name           = "pka_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
@@ -2619,7 +2502,6 @@ static struct clk usb_fck = {
        .name           = "usb_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_48m_ck,
-       .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
@@ -2630,7 +2512,6 @@ static struct clk usbhs_ick = {
        .name           = "usbhs_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_l3_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
@@ -2641,7 +2522,6 @@ static struct clk mmchs1_ick = {
        .name           = "mmchs_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2652,7 +2532,6 @@ static struct clk mmchs1_fck = {
        .name           = "mmchs_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l3_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2664,7 +2543,6 @@ static struct clk mmchs2_ick = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2676,7 +2554,6 @@ static struct clk mmchs2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_96m_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
        .recalc         = &followparent_recalc,
@@ -2686,7 +2563,6 @@ static struct clk gpio5_ick = {
        .name           = "gpio5_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
@@ -2697,7 +2573,6 @@ static struct clk gpio5_fck = {
        .name           = "gpio5_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
@@ -2708,7 +2583,6 @@ static struct clk mdm_intc_ick = {
        .name           = "mdm_intc_ick",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &l4_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2719,7 +2593,6 @@ static struct clk mmchsdb1_fck = {
        .name           = "mmchsdb_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2731,7 +2604,6 @@ static struct clk mmchsdb2_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .id             = 1,
        .parent         = &func_32k_ck,
-       .flags          = CLOCK_IN_OMAP243X,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2755,166 +2627,12 @@ static struct clk mmchsdb2_fck = {
 static struct clk virt_prcm_set = {
        .name           = "virt_prcm_set",
        .ops            = &clkops_null,
-       .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                               DELAYED_APP,
+       .flags          = DELAYED_APP,
        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
        .set_rate       = &omap2_select_table_rate,
        .round_rate     = &omap2_round_to_table_rate,
 };
 
-static struct clk *onchip_24xx_clks[] __initdata = {
-       /* external root sources */
-       &func_32k_ck,
-       &osc_ck,
-       &sys_ck,
-       &alt_ck,
-       /* internal analog sources */
-       &dpll_ck,
-       &apll96_ck,
-       &apll54_ck,
-       /* internal prcm root sources */
-       &func_54m_ck,
-       &core_ck,
-       &func_96m_ck,
-       &func_48m_ck,
-       &func_12m_ck,
-       &wdt1_osc_ck,
-       &sys_clkout_src,
-       &sys_clkout,
-       &sys_clkout2_src,
-       &sys_clkout2,
-       &emul_ck,
-       /* mpu domain clocks */
-       &mpu_ck,
-       /* dsp domain clocks */
-       &dsp_fck,
-       &dsp_irate_ick,
-       &dsp_ick,               /* 242x */
-       &iva2_1_ick,            /* 243x */
-       &iva1_ifck,             /* 242x */
-       &iva1_mpu_int_ifck,     /* 242x */
-       /* GFX domain clocks */
-       &gfx_3d_fck,
-       &gfx_2d_fck,
-       &gfx_ick,
-       /* Modem domain clocks */
-       &mdm_ick,
-       &mdm_osc_ck,
-       /* DSS domain clocks */
-       &dss_ick,
-       &dss1_fck,
-       &dss2_fck,
-       &dss_54m_fck,
-       /* L3 domain clocks */
-       &core_l3_ck,
-       &ssi_ssr_sst_fck,
-       &usb_l4_ick,
-       /* L4 domain clocks */
-       &l4_ck,                 /* used as both core_l4 and wu_l4 */
-       /* virtual meta-group clock */
-       &virt_prcm_set,
-       /* general l4 interface ck, multi-parent functional clk */
-       &gpt1_ick,
-       &gpt1_fck,
-       &gpt2_ick,
-       &gpt2_fck,
-       &gpt3_ick,
-       &gpt3_fck,
-       &gpt4_ick,
-       &gpt4_fck,
-       &gpt5_ick,
-       &gpt5_fck,
-       &gpt6_ick,
-       &gpt6_fck,
-       &gpt7_ick,
-       &gpt7_fck,
-       &gpt8_ick,
-       &gpt8_fck,
-       &gpt9_ick,
-       &gpt9_fck,
-       &gpt10_ick,
-       &gpt10_fck,
-       &gpt11_ick,
-       &gpt11_fck,
-       &gpt12_ick,
-       &gpt12_fck,
-       &mcbsp1_ick,
-       &mcbsp1_fck,
-       &mcbsp2_ick,
-       &mcbsp2_fck,
-       &mcbsp3_ick,
-       &mcbsp3_fck,
-       &mcbsp4_ick,
-       &mcbsp4_fck,
-       &mcbsp5_ick,
-       &mcbsp5_fck,
-       &mcspi1_ick,
-       &mcspi1_fck,
-       &mcspi2_ick,
-       &mcspi2_fck,
-       &mcspi3_ick,
-       &mcspi3_fck,
-       &uart1_ick,
-       &uart1_fck,
-       &uart2_ick,
-       &uart2_fck,
-       &uart3_ick,
-       &uart3_fck,
-       &gpios_ick,
-       &gpios_fck,
-       &mpu_wdt_ick,
-       &mpu_wdt_fck,
-       &sync_32k_ick,
-       &wdt1_ick,
-       &omapctrl_ick,
-       &icr_ick,
-       &cam_fck,
-       &cam_ick,
-       &mailboxes_ick,
-       &wdt4_ick,
-       &wdt4_fck,
-       &wdt3_ick,
-       &wdt3_fck,
-       &mspro_ick,
-       &mspro_fck,
-       &mmc_ick,
-       &mmc_fck,
-       &fac_ick,
-       &fac_fck,
-       &eac_ick,
-       &eac_fck,
-       &hdq_ick,
-       &hdq_fck,
-       &i2c1_ick,
-       &i2c1_fck,
-       &i2chs1_fck,
-       &i2c2_ick,
-       &i2c2_fck,
-       &i2chs2_fck,
-       &gpmc_fck,
-       &sdma_fck,
-       &sdma_ick,
-       &vlynq_ick,
-       &vlynq_fck,
-       &sdrc_ick,
-       &des_ick,
-       &sha_ick,
-       &rng_ick,
-       &aes_ick,
-       &pka_ick,
-       &usb_fck,
-       &usbhs_ick,
-       &mmchs1_ick,
-       &mmchs1_fck,
-       &mmchs2_ick,
-       &mmchs2_fck,
-       &gpio5_ick,
-       &gpio5_fck,
-       &mdm_intc_ick,
-       &mmchsdb1_fck,
-       &mmchsdb2_fck,
-};
-
 #endif
 
Pandora Kernel Repository