#include <mach/cpu.h>
#include <asm/div64.h>
-#include "memory.h"
+#include <mach/sdrc.h>
#include "sdrc.h"
#include "clock.h"
#include "prm.h"
* OMAP2/3 specific clock functions
*-------------------------------------------------------------------------*/
+/**
+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * @clk: struct clk *
+ *
+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
+ * don't take effect until the VALID_CONFIG bit is written, write the
+ * VALID_CONFIG bit and wait for the write to complete. No return value.
+ */
+static void _omap2xxx_clk_commit(struct clk *clk)
+{
+ if (!cpu_is_omap24xx())
+ return;
+
+ if (!(clk->flags & DELAYED_APP))
+ return;
+
+ prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
+ OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+ /* OCP barrier */
+ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+}
+
/*
* _dpll_test_fint - test whether an Fint value is valid for the DPLL
* @clk: DPLL struct clk to test
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
- clk->parent = clks->parent;
+ clk_reparent(clk, clks->parent);
};
found = 1;
}
return;
}
-/* Returns the DPLL rate */
+/**
+ * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
+ * @clk: struct clk * of a DPLL
+ *
+ * DPLLs can be locked or bypassed - basically, enabled or disabled.
+ * When locked, the DPLL output depends on the M and N values. When
+ * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
+ * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
+ * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
+ * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
+ * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
+ * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
+ * if the clock @clk is not a DPLL.
+ */
u32 omap2_get_dpll_rate(struct clk *clk)
{
long long dpll_clk;
- u32 dpll_mult, dpll_div, dpll;
+ u32 dpll_mult, dpll_div, v;
struct dpll_data *dd;
dd = clk->dpll_data;
- /* REVISIT: What do we return on error? */
if (!dd)
return 0;
- dpll = __raw_readl(dd->mult_div1_reg);
- dpll_mult = dpll & dd->mult_mask;
+ /* Return bypass rate if DPLL is bypassed */
+ v = __raw_readl(dd->control_reg);
+ v &= dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+
+ if (cpu_is_omap24xx()) {
+ if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP2XXX_EN_DPLL_FRBYPASS)
+ return dd->clk_bypass->rate;
+ } else if (cpu_is_omap34xx()) {
+ if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS)
+ return dd->clk_bypass->rate;
+ }
+
+ v = __raw_readl(dd->mult_div1_reg);
+ dpll_mult = v & dd->mult_mask;
dpll_mult >>= __ffs(dd->mult_mask);
- dpll_div = dpll & dd->div1_mask;
+ dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
- dpll_clk = (long long)clk->parent->rate * dpll_mult;
+ dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
* Used for clocks that have the same value as the parent clock,
* divided by some factor
*/
-void omap2_fixed_divisor_recalc(struct clk *clk)
+unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
{
WARN_ON(!clk->fixed_div);
- clk->rate = clk->parent->rate / clk->fixed_div;
+ return clk->parent->rate / clk->fixed_div;
}
/**
else
v |= (1 << clk->enable_bit);
__raw_writel(v, clk->enable_reg);
- wmb();
+ v = __raw_readl(clk->enable_reg); /* OCP barrier */
return 0;
}
else
v &= ~(1 << clk->enable_bit);
__raw_writel(v, clk->enable_reg);
- wmb();
+ /* No OCP barrier needed here since it is a disable operation */
}
const struct clkops clkops_omap2_dflt_wait = {
int ret = 0;
if (clk->usecount++ == 0) {
- if (clk->parent)
- ret = omap2_clk_enable(clk->parent);
-
- if (ret != 0) {
- clk->usecount--;
- return ret;
- }
-
if (clk->clkdm)
omap2_clkdm_clk_enable(clk->clkdm, clk);
- ret = _omap2_clk_enable(clk);
-
- if (ret != 0) {
- if (clk->clkdm)
- omap2_clkdm_clk_disable(clk->clkdm, clk);
+ if (clk->parent) {
+ ret = omap2_clk_enable(clk->parent);
+ if (ret)
+ goto err;
+ }
- if (clk->parent) {
+ ret = _omap2_clk_enable(clk);
+ if (ret) {
+ if (clk->parent)
omap2_clk_disable(clk->parent);
- clk->usecount--;
- }
+
+ goto err;
}
}
+ return ret;
+err:
+ if (clk->clkdm)
+ omap2_clkdm_clk_disable(clk->clkdm, clk);
+ clk->usecount--;
return ret;
}
* Used for clocks that are part of CLKSEL_xyz governed clocks.
* REVISIT: Maybe change to use clk->enable() functions like on omap1?
*/
-void omap2_clksel_recalc(struct clk *clk)
+unsigned long omap2_clksel_recalc(struct clk *clk)
{
+ unsigned long rate;
u32 div = 0;
pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
div = omap2_clksel_get_divisor(clk);
if (div == 0)
- return;
+ return clk->rate;
- if (clk->rate == (clk->parent->rate / div))
- return;
- clk->rate = clk->parent->rate / div;
+ rate = clk->parent->rate / div;
+
+ pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
- pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
+ return rate;
}
/**
*
* Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
* find the corresponding register field value. The return register value is
- * the value before left-shifting. Returns 0xffffffff on error
+ * the value before left-shifting. Returns ~0 on error
*/
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
{
clks = omap2_get_clksel_by_parent(clk, clk->parent);
if (!clks)
- return 0;
+ return ~0;
for (clkr = clks->rates; clkr->div; clkr++) {
if ((clkr->flags & cpu_mask) && (clkr->div == div))
printk(KERN_ERR "clock: Could not find divisor %d for "
"clock %s parent %s\n", div, clk->name,
clk->parent->name);
- return 0;
+ return ~0;
}
return clkr->val;
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
__raw_writel(v, clk->clksel_reg);
- wmb();
+ v = __raw_readl(clk->clksel_reg); /* OCP barrier */
clk->rate = clk->parent->rate / new_div;
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
return 0;
}
return 0;
for (clkr = clks->rates; clkr->div; clkr++) {
- if (clkr->flags & (cpu_mask | DEFAULT_RATE))
+ if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
break; /* Found the default rate for this platform */
}
if (!parent_div)
return -EINVAL;
- if (clk->usecount > 0)
- _omap2_clk_disable(clk);
-
/* Set new source value (previous dividers if any in effect) */
v = __raw_readl(clk->clksel_reg);
v &= ~clk->clksel_mask;
v |= field_val << __ffs(clk->clksel_mask);
__raw_writel(v, clk->clksel_reg);
- wmb();
+ v = __raw_readl(clk->clksel_reg); /* OCP barrier */
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
- wmb();
- }
+ _omap2xxx_clk_commit(clk);
- if (clk->usecount > 0)
- _omap2_clk_enable(clk);
-
- clk->parent = new_parent;
+ clk_reparent(clk, new_parent);
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
clk->rate = new_parent->rate;
pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
"%ld\n", clk->name, target_rate);
- scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
+ scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- clk->parent->rate);
+ dd->clk_ref->rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
dd->last_rounded_m = min_e_m;
dd->last_rounded_n = min_e_n;
- dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
+ dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
min_e_m, min_e_n);
pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
return;
printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
- _omap2_clk_disable(clk);
+ if (cpu_is_omap34xx()) {
+ omap2_clk_enable(clk);
+ omap2_clk_disable(clk);
+ } else
+ _omap2_clk_disable(clk);
}
#endif
git.openpandora.org / pandora-kernel.git / blobdiff