ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.

[pandora-kernel.git] / arch / arm / mach-omap2 / Kconfig

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b662513..50f4394 100644 (file)
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -353,6 +353,27 @@ config OMAP3_SDRC_AC_TIMING
          wish to say no.  Selecting yes without understanding what is
          going on could result in system crashes;
 
+config OMAP4_ERRATA_I688
+       bool "OMAP4 errata: Async Bridge Corruption"
+       depends on ARCH_OMAP4
+       select ARCH_HAS_BARRIERS
+       help
+         If a data is stalled inside asynchronous bridge because of back
+         pressure, it may be accepted multiple times, creating pointer
+         misalignment that will corrupt next transfers on that data path
+         until next reset of the system (No recovery procedure once the
+         issue is hit, the path remains consistently broken). Async bridge
+         can be found on path between MPU to EMIF and MPU to L3 interconnect.
+         This situation can happen only when the idle is initiated by a
+         Master Request Disconnection (which is trigged by software when
+         executing WFI on CPU).
+         The work-around for this errata needs all the initiators connected
+         through async bridge must ensure that data path is properly drained
+         before issuing WFI. This condition will be met if one Strongly ordered
+         access is performed to the target right before executing the WFI.
+         In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+         IO barrier ensure that there is no synchronisation loss on initiators
+         operating on both interconnect port simultaneously.
 endmenu
 
 endif