Merge branch 'fix/asoc' into for-linus

[pandora-kernel.git] / arch / arm / mach-omap1 / clock.h

diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index ed343af..17f8742 100644 (file)
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -13,14 +13,14 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 
-static void omap1_ckctl_recalc(struct clk * clk);
-static void omap1_watchdog_recalc(struct clk * clk);
+static unsigned long omap1_ckctl_recalc(struct clk *clk);
+static unsigned long omap1_watchdog_recalc(struct clk *clk);
 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
-static void omap1_sossi_recalc(struct clk *clk);
-static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
+static unsigned long omap1_sossi_recalc(struct clk *clk);
+static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
-static void omap1_uart_recalc(struct clk * clk);
+static unsigned long omap1_uart_recalc(struct clk *clk);
 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
 static void omap1_init_ext_clk(struct clk * clk);
@@ -155,7 +155,6 @@ static struct clk ck_dpll1 = {
        .name           = "ck_dpll1",
        .ops            = &clkops_null,
        .parent         = &ck_ref,
-       .flags          = RATE_PROPAGATES,
 };
 
 static struct arm_idlect1_clk ck_dpll1out = {
@@ -163,9 +162,8 @@ static struct arm_idlect1_clk ck_dpll1out = {
                .name           = "ck_dpll1out",
                .ops            = &clkops_generic,
                .parent         = &ck_dpll1,
-               .flags          = CLOCK_IDLE_CONTROL |
-                                 ENABLE_REG_32BIT | RATE_PROPAGATES,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_CKOUT_ARM,
                .recalc         = &followparent_recalc,
        },
@@ -177,7 +175,7 @@ static struct clk sossi_ck = {
        .ops            = &clkops_generic,
        .parent         = &ck_dpll1out.clk,
        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_1,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
        .enable_bit     = 16,
        .recalc         = &omap1_sossi_recalc,
        .set_rate       = &omap1_set_sossi_rate,
@@ -187,7 +185,6 @@ static struct clk arm_ck = {
        .name           = "arm_ck",
        .ops            = &clkops_null,
        .parent         = &ck_dpll1,
-       .flags          = RATE_PROPAGATES,
        .rate_offset    = CKCTL_ARMDIV_OFFSET,
        .recalc         = &omap1_ckctl_recalc,
        .round_rate     = omap1_clk_round_rate_ckctl_arm,
@@ -200,7 +197,7 @@ static struct arm_idlect1_clk armper_ck = {
                .ops            = &clkops_generic,
                .parent         = &ck_dpll1,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_PERCK,
                .rate_offset    = CKCTL_PERDIV_OFFSET,
                .recalc         = &omap1_ckctl_recalc,
@@ -214,7 +211,7 @@ static struct clk arm_gpio_ck = {
        .name           = "arm_gpio_ck",
        .ops            = &clkops_generic,
        .parent         = &ck_dpll1,
-       .enable_reg     = (void __iomem *)ARM_IDLECT2,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
        .enable_bit     = EN_GPIOCK,
        .recalc         = &followparent_recalc,
 };
@@ -225,7 +222,7 @@ static struct arm_idlect1_clk armxor_ck = {
                .ops            = &clkops_generic,
                .parent         = &ck_ref,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_XORPCK,
                .recalc         = &followparent_recalc,
        },
@@ -238,7 +235,7 @@ static struct arm_idlect1_clk armtim_ck = {
                .ops            = &clkops_generic,
                .parent         = &ck_ref,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_TIMCK,
                .recalc         = &followparent_recalc,
        },
@@ -251,7 +248,7 @@ static struct arm_idlect1_clk armwdt_ck = {
                .ops            = &clkops_generic,
                .parent         = &ck_ref,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_WDTCK,
                .recalc         = &omap1_watchdog_recalc,
        },
@@ -274,7 +271,7 @@ static struct clk dsp_ck = {
        .name           = "dsp_ck",
        .ops            = &clkops_generic,
        .parent         = &ck_dpll1,
-       .enable_reg     = (void __iomem *)ARM_CKCTL,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
        .enable_bit     = EN_DSPCK,
        .rate_offset    = CKCTL_DSPDIV_OFFSET,
        .recalc         = &omap1_ckctl_recalc,
@@ -296,7 +293,6 @@ static struct clk dspper_ck = {
        .name           = "dspper_ck",
        .ops            = &clkops_dspck,
        .parent         = &ck_dpll1,
-       .flags          = VIRTUAL_IO_ADDRESS,
        .enable_reg     = DSP_IDLECT2,
        .enable_bit     = EN_PERCK,
        .rate_offset    = CKCTL_PERDIV_OFFSET,
@@ -309,7 +305,6 @@ static struct clk dspxor_ck = {
        .name           = "dspxor_ck",
        .ops            = &clkops_dspck,
        .parent         = &ck_ref,
-       .flags          = VIRTUAL_IO_ADDRESS,
        .enable_reg     = DSP_IDLECT2,
        .enable_bit     = EN_XORPCK,
        .recalc         = &followparent_recalc,
@@ -319,7 +314,6 @@ static struct clk dsptim_ck = {
        .name           = "dsptim_ck",
        .ops            = &clkops_dspck,
        .parent         = &ck_ref,
-       .flags          = VIRTUAL_IO_ADDRESS,
        .enable_reg     = DSP_IDLECT2,
        .enable_bit     = EN_DSPTIMCK,
        .recalc         = &followparent_recalc,
@@ -331,7 +325,7 @@ static struct arm_idlect1_clk tc_ck = {
                .name           = "tc_ck",
                .ops            = &clkops_null,
                .parent         = &ck_dpll1,
-               .flags          = RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
+               .flags          = CLOCK_IDLE_CONTROL,
                .rate_offset    = CKCTL_TCDIV_OFFSET,
                .recalc         = &omap1_ckctl_recalc,
                .round_rate     = omap1_clk_round_rate_ckctl_arm,
@@ -364,7 +358,7 @@ static struct clk l3_ocpi_ck = {
        .name           = "l3_ocpi_ck",
        .ops            = &clkops_generic,
        .parent         = &tc_ck.clk,
-       .enable_reg     = (void __iomem *)ARM_IDLECT3,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
        .enable_bit     = EN_OCPI_CK,
        .recalc         = &followparent_recalc,
 };
@@ -373,7 +367,7 @@ static struct clk tc1_ck = {
        .name           = "tc1_ck",
        .ops            = &clkops_generic,
        .parent         = &tc_ck.clk,
-       .enable_reg     = (void __iomem *)ARM_IDLECT3,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
        .enable_bit     = EN_TC1_CK,
        .recalc         = &followparent_recalc,
 };
@@ -382,7 +376,7 @@ static struct clk tc2_ck = {
        .name           = "tc2_ck",
        .ops            = &clkops_generic,
        .parent         = &tc_ck.clk,
-       .enable_reg     = (void __iomem *)ARM_IDLECT3,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
        .enable_bit     = EN_TC2_CK,
        .recalc         = &followparent_recalc,
 };
@@ -408,7 +402,7 @@ static struct arm_idlect1_clk api_ck = {
                .ops            = &clkops_generic,
                .parent         = &tc_ck.clk,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_APICK,
                .recalc         = &followparent_recalc,
        },
@@ -421,7 +415,7 @@ static struct arm_idlect1_clk lb_ck = {
                .ops            = &clkops_generic,
                .parent         = &tc_ck.clk,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_LBCK,
                .recalc         = &followparent_recalc,
        },
@@ -446,7 +440,7 @@ static struct clk lcd_ck_16xx = {
        .name           = "lcd_ck",
        .ops            = &clkops_generic,
        .parent         = &ck_dpll1,
-       .enable_reg     = (void __iomem *)ARM_IDLECT2,
+       .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
        .enable_bit     = EN_LCDCK,
        .rate_offset    = CKCTL_LCDDIV_OFFSET,
        .recalc         = &omap1_ckctl_recalc,
@@ -460,7 +454,7 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
                .ops            = &clkops_generic,
                .parent         = &ck_dpll1,
                .flags          = CLOCK_IDLE_CONTROL,
-               .enable_reg     = (void __iomem *)ARM_IDLECT2,
+               .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                .enable_bit     = EN_LCDCK,
                .rate_offset    = CKCTL_LCDDIV_OFFSET,
                .recalc         = &omap1_ckctl_recalc,
@@ -477,7 +471,7 @@ static struct clk uart1_1510 = {
        .parent         = &armper_ck.clk,
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
@@ -492,7 +486,7 @@ static struct uart_clk uart1_16xx = {
                .rate           = 48000000,
                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
                                  CLOCK_NO_IDLE_PARENT,
-               .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+               .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                .enable_bit     = 29,
        },
        .sysc_addr      = 0xfffb0054,
@@ -505,7 +499,7 @@ static struct clk uart2_ck = {
        .parent         = &armper_ck.clk,
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
@@ -518,7 +512,7 @@ static struct clk uart3_1510 = {
        .parent         = &armper_ck.clk,
        .rate           = 12000000,
        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
        .set_rate       = &omap1_set_uart_rate,
        .recalc         = &omap1_uart_recalc,
@@ -533,7 +527,7 @@ static struct uart_clk uart3_16xx = {
                .rate           = 48000000,
                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
                                  CLOCK_NO_IDLE_PARENT,
-               .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+               .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                .enable_bit     = 31,
        },
        .sysc_addr      = 0xfffb9854,
@@ -545,7 +539,7 @@ static struct clk usb_clko = {      /* 6 MHz output on W4_USB_CLKO */
        /* Direct from ULPD, no parent */
        .rate           = 6000000,
        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
+       .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
        .enable_bit     = USB_MCLK_EN_BIT,
 };
 
@@ -555,7 +549,7 @@ static struct clk usb_hhc_ck1510 = {
        /* Direct from ULPD, no parent */
        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = USB_HOST_HHC_UHOST_EN,
 };
 
@@ -566,7 +560,7 @@ static struct clk usb_hhc_ck16xx = {
        .rate           = 48000000,
        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-       .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
+       .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
        .enable_bit     = 8 /* UHOST_EN */,
 };
 
@@ -576,7 +570,7 @@ static struct clk usb_dc_ck = {
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
        .flags          = RATE_FIXED,
-       .enable_reg     = (void __iomem *)SOFT_REQ_REG,
+       .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
        .enable_bit     = 4,
 };
 
@@ -586,15 +580,15 @@ static struct clk mclk_1510 = {
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
        .rate           = 12000000,
        .flags          = RATE_FIXED,
-       .enable_reg     = (void __iomem *)SOFT_REQ_REG,
-       .enable_bit     = 6,
+       .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+       .enable_bit     = 6,
 };
 
 static struct clk mclk_16xx = {
        .name           = "mclk",
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
+       .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
        .enable_bit     = COM_ULPD_PLL_CLK_REQ,
        .set_rate       = &omap1_set_ext_clk_rate,
        .round_rate     = &omap1_round_ext_clk_rate,
@@ -613,7 +607,7 @@ static struct clk bclk_16xx = {
        .name           = "bclk",
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-       .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
+       .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
        .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
        .set_rate       = &omap1_set_ext_clk_rate,
        .round_rate     = &omap1_round_ext_clk_rate,
@@ -627,7 +621,7 @@ static struct clk mmc1_ck = {
        .parent         = &armper_ck.clk,
        .rate           = 48000000,
        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 23,
 };
 
@@ -639,7 +633,7 @@ static struct clk mmc2_ck = {
        .parent         = &armper_ck.clk,
        .rate           = 48000000,
        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-       .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
+       .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 20,
 };