mx5: change usb clock source from pll3 to pll2

[pandora-kernel.git] / arch / arm / mach-mx5 / clock-mx51.c

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index dcca330..566cfda 100644 (file)
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -36,6 +36,7 @@ static struct clk lp_apm_clk;
 static struct clk periph_apm_clk;
 static struct clk ahb_clk;
 static struct clk ipg_clk;
+static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
 
@@ -569,6 +570,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
        return 0;
 }
 
+static unsigned long clk_usboh3_get_rate(struct clk *clk)
+{
+       u32 reg, prediv, podf;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CSCDR1);
+       prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
+                 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
+       podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
+               MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+
+       return parent_rate / (prediv * podf);
+}
+
+static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg, mux;
+
+       mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+                      &lp_apm_clk);
+       reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+       reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 {
        return external_high_reference;
@@ -690,6 +720,12 @@ static struct clk uart_root_clk = {
        .set_parent = _clk_uart_set_parent,
 };
 
+static struct clk usboh3_clk = {
+       .parent = &pll2_sw_clk,
+       .get_rate = clk_usboh3_get_rate,
+       .set_parent = _clk_usboh3_set_parent,
+};
+
 static struct clk ahb_max_clk = {
        .parent = &ahb_clk,
        .enable_reg = MXC_CCM_CCGR0,
@@ -761,10 +797,6 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
        NULL,  NULL, &ipg_clk, NULL);
 
-/* USB */
-DEFINE_CLOCK(usboh3_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG14_OFFSET,
-       NULL, NULL, &pll3_sw_clk, NULL);
-
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
        NULL,  NULL, &ipg_clk, NULL);
@@ -826,6 +858,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
        clk_enable(&cpu_clk);
        clk_enable(&main_bus_clk);
 
+       /* set the usboh3_clk parent to pll2_sw_clk */
+       clk_set_parent(&usboh3_clk, &pll2_sw_clk);
+
        /* System timer */
        mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
                MX51_MXC_INT_GPT);