static struct irq_chip icu_irq_chip = {
.name = "icu_irq",
+ .mask = icu_mask_irq,
.mask_ack = icu_mask_irq,
.unmask = icu_unmask_irq,
};
+static void pmic_irq_ack(unsigned int irq)
+{
+ if (irq == IRQ_MMP2_PMIC)
+ mmp2_clear_pmic_int();
+}
+
#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
static void _name_##_mask_irq(unsigned int irq) \
{ \
SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
static struct irq_chip _name_##_irq_chip = { \
.name = #_name_, \
- .mask_ack = _name_##_mask_irq, \
+ .mask = _name_##_mask_irq, \
.unmask = _name_##_unmask_irq, \
}
int irq;
for (irq = start; num > 0; irq++, num--) {
- chip->mask_ack(irq);
+ /* mask and clear the IRQ */
+ chip->mask(irq);
+ if (chip->ack)
+ chip->ack(irq);
+
set_irq_chip(irq, chip);
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
}
}
-void __init mmp2_init_irq(void)
+void __init mmp2_init_icu(void)
{
int irq;
}
}
+ /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
+ * to be written to clear the interrupt
+ */
+ pmic_irq_chip.ack = pmic_irq_ack;
+
init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);