Merge branch 'agp-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...

[pandora-kernel.git] / arch / arm / mach-ixp4xx / include / mach / io.h

diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index c06d4a2..6ea7e2f 100644 (file)
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -26,22 +26,20 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 /*
  * IXP4xx provides two methods of accessing PCI memory space:
  *
- * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+ * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
  *    To access PCI via this space, we simply ioremap() the BAR
  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  *    macros. This is the preffered method due to speed but it
- *    limits the system to just 64MB of PCI memory. This can be 
- *    problamatic if using video cards and other memory-heavy
- *    targets.
- *
- * 2) If > 64MB of memory space is required, the IXP4xx can be configured
- *    to use indirect registers to access PCI (as we do below for I/O
- *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
- *    of memory on the bus. The disadvantage of this is that every 
- *    PCI access requires three local register accesses plus a spinlock,
- *    but in some cases the performance hit is acceptable. In addition,
- *    you cannot mmap() PCI devices in this case.
+ *    limits the system to just 64MB of PCI memory. This can be
+ *    problematic if using video cards and other memory-heavy targets.
  *
+ * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
+ *    registers to access the whole 4 GB of PCI memory space (as we do below
+ *    for I/O transactions). This allows currently for up to 1 GB (0x10000000
+ *    to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
+ *    every PCI access requires three local register accesses plus a spinlock,
+ *    but in some cases the performance hit is acceptable. In addition, you
+ *    cannot mmap() PCI devices in this case.
  */
 #ifndef        CONFIG_IXP4XX_INDIRECT_PCI
 
@@ -55,10 +53,16 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  * access registers. If something outside of PCI is ioremap'd, we
  * fallback to the default.
  */
+
+static inline int is_pci_memory(u32 addr)
+{
+       return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
+}
+
 static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
                                                unsigned int mtype)
 {
-       if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
+       if (!is_pci_memory(addr))
                return __arm_ioremap(addr, size, mtype);
 
        return (void __iomem *)addr;
@@ -66,7 +70,7 @@ static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
 
 static inline void __indirect_iounmap(void __iomem *addr)
 {
-       if ((__force u32)addr >= VMALLOC_START)
+       if (!is_pci_memory((__force u32)addr))
                __iounmap(addr);
 }
 
@@ -94,7 +98,7 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
        u32 addr = (u32)p;
        u32 n, byte_enables, data;
 
-       if (addr >= VMALLOC_START) {
+       if (!is_pci_memory(addr)) {
                __raw_writeb(value, addr);
                return;
        }
@@ -117,7 +121,7 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
        u32 addr = (u32)p;
        u32 n, byte_enables, data;
 
-       if (addr >= VMALLOC_START) {
+       if (!is_pci_memory(addr)) {
                __raw_writew(value, addr);
                return;
        }
@@ -138,7 +142,8 @@ static inline void __indirect_writesw(volatile void __iomem *bus_addr,
 static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 {
        u32 addr = (__force u32)p;
-       if (addr >= VMALLOC_START) {
+
+       if (!is_pci_memory(addr)) {
                __raw_writel(value, p);
                return;
        }
@@ -158,7 +163,7 @@ static inline unsigned char __indirect_readb(const volatile void __iomem *p)
        u32 addr = (u32)p;
        u32 n, byte_enables, data;
 
-       if (addr >= VMALLOC_START)
+       if (!is_pci_memory(addr))
                return __raw_readb(addr);
 
        n = addr % 4;
@@ -181,7 +186,7 @@ static inline unsigned short __indirect_readw(const volatile void __iomem *p)
        u32 addr = (u32)p;
        u32 n, byte_enables, data;
 
-       if (addr >= VMALLOC_START)
+       if (!is_pci_memory(addr))
                return __raw_readw(addr);
 
        n = addr % 4;
@@ -204,7 +209,7 @@ static inline unsigned long __indirect_readl(const volatile void __iomem *p)
        u32 addr = (__force u32)p;
        u32 data;
 
-       if (addr >= VMALLOC_START)
+       if (!is_pci_memory(addr))
                return __raw_readl(p);
 
        if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))