firewire: core: handle ack_busy when fetching the Config ROM

[pandora-kernel.git] / arch / arm / mach-exynos4 / gpiolib.c

diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
index c46fdc5..d54ca6a 100644 (file)
--- a/arch/arm/mach-exynos4/gpiolib.c
+++ b/arch/arm/mach-exynos4/gpiolib.c
@@ -198,6 +198,55 @@ static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
                        .ngpio  = EXYNOS4_GPIO_L2_NR,
                        .label  = "GPL2",
                },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY0(0),
+                       .ngpio  = EXYNOS4_GPIO_Y0_NR,
+                       .label  = "GPY0",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY1(0),
+                       .ngpio  = EXYNOS4_GPIO_Y1_NR,
+                       .label  = "GPY1",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY2(0),
+                       .ngpio  = EXYNOS4_GPIO_Y2_NR,
+                       .label  = "GPY2",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY3(0),
+                       .ngpio  = EXYNOS4_GPIO_Y3_NR,
+                       .label  = "GPY3",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY4(0),
+                       .ngpio  = EXYNOS4_GPIO_Y4_NR,
+                       .label  = "GPY4",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY5(0),
+                       .ngpio  = EXYNOS4_GPIO_Y5_NR,
+                       .label  = "GPY5",
+               },
+       }, {
+               .config = &gpio_cfg_noint,
+               .chip   = {
+                       .base   = EXYNOS4_GPY6(0),
+                       .ngpio  = EXYNOS4_GPIO_Y6_NR,
+                       .label  = "GPY6",
+               },
        }, {
                .base   = (S5P_VA_GPIO2 + 0xC00),
                .config = &gpio_cfg_noint,
@@ -255,6 +304,7 @@ static __init int exynos4_gpiolib_init(void)
 {
        struct s3c_gpio_chip *chip;
        int i;
+       int group = 0;
        int nr_chips;
 
        /* GPIO part 1 */
@@ -263,8 +313,11 @@ static __init int exynos4_gpiolib_init(void)
        nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
 
        for (i = 0; i < nr_chips; i++, chip++) {
-               if (chip->config == NULL)
+               if (chip->config == NULL) {
                        chip->config = &gpio_cfg;
+                       /* Assign the GPIO interrupt group */
+                       chip->group = group++;
+               }
                if (chip->base == NULL)
                        chip->base = S5P_VA_GPIO1 + (i) * 0x20;
        }
@@ -277,8 +330,11 @@ static __init int exynos4_gpiolib_init(void)
        nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
 
        for (i = 0; i < nr_chips; i++, chip++) {
-               if (chip->config == NULL)
+               if (chip->config == NULL) {
                        chip->config = &gpio_cfg;
+                       /* Assign the GPIO interrupt group */
+                       chip->group = group++;
+               }
                if (chip->base == NULL)
                        chip->base = S5P_VA_GPIO2 + (i) * 0x20;
        }
@@ -291,13 +347,18 @@ static __init int exynos4_gpiolib_init(void)
        nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
 
        for (i = 0; i < nr_chips; i++, chip++) {
-               if (chip->config == NULL)
+               if (chip->config == NULL) {
                        chip->config = &gpio_cfg;
+                       /* Assign the GPIO interrupt group */
+                       chip->group = group++;
+               }
                if (chip->base == NULL)
                        chip->base = S5P_VA_GPIO3 + (i) * 0x20;
        }
 
        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
+       s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
+       s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
 
        return 0;
 }