ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+

[pandora-kernel.git] / arch / arm / kernel / head.S

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 2c35f0f..664eee8 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -140,7 +140,7 @@ ENTRY(stext)
        mov     r8, r4                          @ set TTBR1 to swapper_pg_dir
  ARM(  add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB(        add     r12, r10, #PROCINFO_INITFUNC    )
- THUMB(        mov     pc, r12                         )
+ THUMB(        ret     r12                             )
 1:     b       __enable_mmu
 ENDPROC(stext)
        .ltorg
@@ -335,7 +335,7 @@ __create_page_tables:
        sub     r4, r4, #0x1000         @ point to the PGD table
        mov     r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
-       mov     pc, lr
+       ret     lr
 ENDPROC(__create_page_tables)
        .ltorg
        .align
@@ -383,7 +383,7 @@ ENTRY(secondary_startup)
  ARM(  add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
                                                  @ (return control reg)
  THUMB(        add     r12, r10, #PROCINFO_INITFUNC    )
- THUMB(        mov     pc, r12                         )
+ THUMB(        ret     r12                             )
 ENDPROC(secondary_startup)
 
        /*
@@ -468,7 +468,7 @@ ENTRY(__turn_mmu_on)
        instr_sync
        mov     r3, r3
        mov     r3, r13
-       mov     pc, r3
+       ret     r3
 __turn_mmu_on_end:
 ENDPROC(__turn_mmu_on)
        .popsection
@@ -487,7 +487,7 @@ __fixup_smp:
        orr     r4, r4, #0x0000b000
        orr     r4, r4, #0x00000020     @ val 0x4100b020
        teq     r3, r4                  @ ARM 11MPCore?
-       moveq   pc, lr                  @ yes, assume SMP
+       reteq   lr                      @ yes, assume SMP
 
        mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
        and     r0, r0, #0xc0000000     @ multiprocessing extensions and
@@ -500,7 +500,7 @@ __fixup_smp:
        orr     r4, r4, #0x0000c000
        orr     r4, r4, #0x00000090
        teq     r3, r4                  @ Check for ARM Cortex-A9
-       movne   pc, lr                  @ Not ARM Cortex-A9,
+       retne   lr                      @ Not ARM Cortex-A9,
 
        @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
        @ below address check will need to be #ifdef'd or equivalent
@@ -512,7 +512,7 @@ __fixup_smp:
 ARM_BE8(rev    r0, r0)                 @ byteswap if big endian
        and     r0, r0, #0x3            @ number of CPUs
        teq     r0, #0x0                @ is 1?
-       movne   pc, lr
+       retne   lr
 
 __fixup_smp_on_up:
        adr     r0, 1f
@@ -539,7 +539,7 @@ smp_on_up:
        .text
 __do_fixup_smp_on_up:
        cmp     r4, r5
-       movhs   pc, lr
+       reths   lr
        ldmia   r4!, {r0, r6}
  ARM(  str     r6, [r0, r3]    )
  THUMB(        add     r0, r0, r3      )
@@ -672,7 +672,7 @@ ARM_BE8(rev16       ip, ip)
 2:     cmp     r4, r5
        ldrcc   r7, [r4], #4    @ use branch for delay slot
        bcc     1b
-       mov     pc, lr
+       ret     lr
 #endif
 ENDPROC(__fixup_a_pv_table)