W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
+ .word 0x560f5810 @ Marvell PJ4 ARMv6
+ .word 0xff0ffff0
+ W(b) __armv4_mmu_cache_on
+ W(b) __armv4_mmu_cache_off
+ W(b) __armv6_mmu_cache_flush
+
.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on