select HAVE_IDE
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
+ select GENERIC_ATOMIC64 if (!CPU_32v6K)
select HAVE_OPROFILE
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_GENERIC_DMA_COHERENT
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO
+ select HAVE_PERF_EVENTS
+ select PERF_USE_VMALLOC
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
bool
select GENERIC_ALLOCATOR
+config HAVE_PROC_CPU
+ bool
+
config NO_IOPORT
bool
config ZONE_DMA
bool
+config NEED_DMA_MAP_STATE
+ def_bool y
+
config GENERIC_ISA_DMA
bool
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
+config ARM_L1_CACHE_SHIFT_6
+ bool
+ help
+ Setting ARM L1 cache line size to 64 Bytes.
+
if OPROFILE
config OPROFILE_ARMV6
bool "Freescale MXC/iMX-based"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
- select ARCH_MTD_XIP
- select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
+ select COMMON_CLKDEV
help
Support for Freescale MXC/iMX-based family of processors
Orion-2 (5281), Orion-1-90 (6183).
config ARCH_MMP
- bool "Marvell PXA168/910"
+ bool "Marvell PXA168/910/MMP2"
depends on MMU
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select TICK_ONESHOT
select PLAT_PXA
help
- Support for Marvell's PXA168/910 processor line.
+ Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
config ARCH_KS8695
bool "Micrel/Kendin KS8695"
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
+config ARCH_NUC93X
+ bool "Nuvoton NUC93X CPU"
+ select CPU_ARM926T
+ select HAVE_CLK
+ select COMMON_CLKDEV
+ help
+ Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+ low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
select HAVE_CLK
+ select COMMON_CLKDEV
help
This enables support for Philips PNX4008 mobile platform.
interface to the ARM9 modem processor which runs the baseband stack
and controls some vital subsystems (clock and power control, etc).
+config ARCH_SHMOBILE
+ bool "Renesas SH-Mobile"
+ help
+ Support for Renesas's SH-Mobile ARM platforms
+
config ARCH_RPC
bool "RiscPC"
select ARCH_ACORN
config ARCH_S3C64XX
bool "Samsung S3C64XX"
+ select PLAT_SAMSUNG
+ select CPU_V6
select GENERIC_GPIO
+ select ARM_VIC
select HAVE_CLK
+ select NO_IOPORT
select ARCH_HAS_CPUFREQ
+ select ARCH_REQUIRE_GPIOLIB
+ select SAMSUNG_CLKSRC
+ select SAMSUNG_IRQ_VIC_TIMER
+ select SAMSUNG_IRQ_UART
+ select S3C_GPIO_TRACK
+ select S3C_GPIO_PULL_UPDOWN
+ select S3C_GPIO_CFG_S3C24XX
+ select S3C_GPIO_CFG_S3C64XX
+ select S3C_DEV_NAND
+ select USB_ARCH_HAS_OHCI
+ select SAMSUNG_GPIOLIB_4BIT
help
Samsung S3C64XX series based systems
+config ARCH_S5P6440
+ bool "Samsung S5P6440"
+ select CPU_V6
+ select GENERIC_GPIO
+ select HAVE_CLK
+ help
+ Samsung S5P6440 CPU based systems
+
+config ARCH_S5P6442
+ bool "Samsung S5P6442"
+ select CPU_V6
+ select GENERIC_GPIO
+ select HAVE_CLK
+ help
+ Samsung S5P6442 CPU based systems
+
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
help
Samsung S5PC1XX series based systems
+config ARCH_S5PV210
+ bool "Samsung S5PV210/S5PC110"
+ select CPU_V7
+ select GENERIC_GPIO
+ select HAVE_CLK
+ select ARM_L1_CACHE_SHIFT_6
+ help
+ Samsung S5PV210/S5PC110 series based systems
+
config ARCH_SHARK
bool "Shark"
select CPU_SA110
source "arch/arm/mach-ns9xxx/Kconfig"
+source "arch/arm/mach-nuc93x/Kconfig"
+
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
-source "arch/arm/plat-s3c64xx/Kconfig"
-source "arch/arm/plat-s3c/Kconfig"
+source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-s5pc1xx/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2440/Kconfig"
-source "arch/arm/mach-s3c2442/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig"
endif
if ARCH_S3C64XX
-source "arch/arm/mach-s3c6400/Kconfig"
-source "arch/arm/mach-s3c6410/Kconfig"
+source "arch/arm/mach-s3c64xx/Kconfig"
endif
-source "arch/arm/plat-stmp3xxx/Kconfig"
+source "arch/arm/mach-s5p6440/Kconfig"
+
+source "arch/arm/mach-s5p6442/Kconfig"
if ARCH_S5PC1XX
source "arch/arm/mach-s5pc100/Kconfig"
endif
+source "arch/arm/mach-s5pv210/Kconfig"
+
+source "arch/arm/mach-shmobile/Kconfig"
+
+source "arch/arm/plat-stmp3xxx/Kconfig"
+
source "arch/arm/mach-u300/Kconfig"
source "arch/arm/mach-ux500/Kconfig"
depends on CPU_XSCALE && !XSCALE_PMU_TIMER
default y
+config CPU_HAS_PMU
+ depends on CPU_V6 || CPU_V7 || XSCALE_PMU
+ default y
+ bool
+
if !MMU
source "arch/arm/Kconfig-nommu"
endif
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+config PL310_ERRATA_588369
+ bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+ depends on CACHE_L2X0 && ARCH_OMAP4
+ help
+ The PL310 L2 cache controller implements three types of Clean &
+ Invalidate maintenance operations: by Physical Address
+ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+ They are architecturally defined to behave as the execution of a
+ clean operation followed immediately by an invalidate operation,
+ both performing to the same memory location. This functionality
+ is not correctly implemented in PL310 as clean lines are not
+ invalidated as a result of these operations. Note that this errata
+ uses Texas Instrument's secure monitor api.
endmenu
source "arch/arm/common/Kconfig"
config HZ
int
default 128 if ARCH_L7200
- default 200 if ARCH_EBSA110 || ARCH_S3C2410
+ default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default 100
depends on HIGHMEM
depends on !OUTER_CACHE
+config HW_PERF_EVENTS
+ bool "Enable hardware performance counter support for perf events"
+ depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
+ default y
+ help
+ Enable hardware performance counter support for perf events. If
+ disabled, perf events will use software events only.
+
source "mm/Kconfig"
config LEDS
bool
depends on CPU_CP15_MMU
default y if !ARCH_EBSA110
+ select HAVE_PROC_CPU if PROC_FS
help
ARM processors cannot fetch/store information which is not
naturally aligned on the bus, i.e., a 4 byte fetch must start at an
git.openpandora.org / pandora-kernel.git / blobdiff