Merge branch 'highbank/soc' into next/soc

[pandora-kernel.git] / arch / arm / Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2686959..6147d30 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,6 +330,20 @@ config ARCH_BCMRING
        help
          Support for Broadcom's BCMRing platform.
 
+config ARCH_HIGHBANK
+       bool "Calxeda Highbank-based"
+       select ARCH_WANT_OPTIONAL_GPIOLIB
+       select ARM_AMBA
+       select ARM_GIC
+       select ARM_TIMER_SP804
+       select CLKDEV_LOOKUP
+       select CPU_V7
+       select GENERIC_CLOCKEVENTS
+       select HAVE_ARM_SCU
+       select USE_OF
+       help
+         Support for the Calxeda Highbank SoC based boards.
+
 config ARCH_CLPS711X
        bool "Cirrus Logic CLPS711x/EP721x-based"
        select CPU_ARM720T
@@ -413,6 +427,7 @@ config ARCH_MXC
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP
        select HAVE_SCHED_CLOCK
+       select MULTI_IRQ_HANDLER
        help
          Support for Freescale MXC/iMX-based family of processors
 
@@ -861,6 +876,7 @@ config ARCH_U300
        select CLKDEV_LOOKUP
        select HAVE_MACH_CLKDEV
        select GENERIC_GPIO
+       select ARCH_REQUIRE_GPIOLIB
        select NEED_MACH_MEMORY_H
        help
          Support for ST-Ericsson U300 series mobile platforms.
@@ -1310,6 +1326,20 @@ config ARM_ERRATA_364296
          processor into full low interrupt latency mode. ARM11MPCore
          is not affected.
 
+config ARM_ERRATA_764369
+       bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+       depends on CPU_V7 && SMP
+       help
+         This option enables the workaround for erratum 764369
+         affecting Cortex-A9 MPCore with two or more processors (all
+         current revisions). Under certain timing circumstances, a data
+         cache line maintenance operation by MVA targeting an Inner
+         Shareable memory region may fail to proceed up to either the
+         Point of Coherency or to the Point of Unification of the
+         system. This workaround adds a DSB instruction before the
+         relevant cache maintenance functions and sets a specific bit
+         in the diagnostic control register of the SCU.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1387,7 +1417,7 @@ config SMP
        depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
                 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK
        select USE_GENERIC_SMP_HELPERS
        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
        help