powerpc/sysdev: implement FSL GTM support

[pandora-kernel.git] / Documentation / powerpc / booting-without-of.txt

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 948f641..8675ebc 100644 (file)
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -61,6 +61,7 @@ Table of Contents
       r) Freescale Display Interface Unit
       s) Freescale on board FPGA
       t) Freescael MSI interrupt controller
+      u) Freescale General-purpose Timers Module
 
   VII - Marvell Discovery mv64[345]6x System Controller chips
     1) The /system-controller node
@@ -2907,6 +2908,37 @@ platforms are moved over to use the flattened-device-tree model.
                interrupt-parent = <&mpic>;
        };
 
+    u) Freescale General-purpose Timers Module
+
+    Required properties:
+      - compatible : should be
+        "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
+        "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
+        "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
+      - reg : should contain gtm registers location and length (0x40).
+      - interrupts : should contain four interrupts.
+      - interrupt-parent : interrupt source phandle.
+      - clock-frequency : specifies the frequency driving the timer.
+
+    Example:
+
+    timer@500 {
+       compatible = "fsl,mpc8360-gtm", "fsl,gtm";
+       reg = <0x500 0x40>;
+       interrupts = <90 8 78 8 84 8 72 8>;
+       interrupt-parent = <&ipic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+    };
+
+    timer@440 {
+       compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
+       reg = <0x440 0x40>;
+       interrupts = <12 13 14 15>;
+       interrupt-parent = <&qeic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+    };
 
 VII - Marvell Discovery mv64[345]6x System Controller chips
 ===========================================================