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Merge branch 'slab/urgent' into slab/next
[pandora-kernel.git]
/
drivers
/
net
/
ixgbe
/
ixgbe_phy.c
diff --git
a/drivers/net/ixgbe/ixgbe_phy.c
b/drivers/net/ixgbe/ixgbe_phy.c
index
df5b8aa
..
f7ca351
100644
(file)
--- a/
drivers/net/ixgbe/ixgbe_phy.c
+++ b/
drivers/net/ixgbe/ixgbe_phy.c
@@
-449,7
+449,8
@@
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
MDIO_MMD_AN,
&autoneg_reg);
MDIO_MMD_AN,
&autoneg_reg);
- autoneg_reg &= ~ADVERTISE_100FULL;
+ autoneg_reg &= ~(ADVERTISE_100FULL |
+ ADVERTISE_100HALF);
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= ADVERTISE_100FULL;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= ADVERTISE_100FULL;
@@
-656,7
+657,8
@@
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
MDIO_MMD_AN,
&autoneg_reg);
MDIO_MMD_AN,
&autoneg_reg);
- autoneg_reg &= ~ADVERTISE_100FULL;
+ autoneg_reg &= ~(ADVERTISE_100FULL |
+ ADVERTISE_100HALF);
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= ADVERTISE_100FULL;
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
autoneg_reg |= ADVERTISE_100FULL;
@@
-753,7
+755,7
@@
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
&phy_data);
if ((phy_data & MDIO_CTRL1_RESET) == 0)
break;
&phy_data);
if ((phy_data & MDIO_CTRL1_RESET) == 0)
break;
-
msleep(1
0);
+
usleep_range(10000, 2000
0);
}
if ((phy_data & MDIO_CTRL1_RESET) != 0) {
}
if ((phy_data & MDIO_CTRL1_RESET) != 0) {
@@
-782,7
+784,7
@@
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
case IXGBE_DELAY_NL:
data_offset++;
hw_dbg(hw, "DELAY: %d MS\n", edata);
case IXGBE_DELAY_NL:
data_offset++;
hw_dbg(hw, "DELAY: %d MS\n", edata);
-
msleep(edata
);
+
usleep_range(edata * 1000, edata * 2000
);
break;
case IXGBE_DATA_NL:
hw_dbg(hw, "DATA:\n");
break;
case IXGBE_DATA_NL:
hw_dbg(hw, "DATA:\n");
@@
-1220,7
+1222,7
@@
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
swfw_mask = IXGBE_GSSR_PHY0_SM;
do {
swfw_mask = IXGBE_GSSR_PHY0_SM;
do {
- if (
ixgbe_
acquire_swfw_sync(hw, swfw_mask) != 0) {
+ if (
hw->mac.ops.
acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out;
}
status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out;
}
@@
-1267,7
+1269,7
@@
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
break;
fail:
break;
fail:
-
ixgbe_
release_swfw_sync(hw, swfw_mask);
+
hw->mac.ops.
release_swfw_sync(hw, swfw_mask);
msleep(100);
ixgbe_i2c_bus_clear(hw);
retry++;
msleep(100);
ixgbe_i2c_bus_clear(hw);
retry++;
@@
-1278,7
+1280,7
@@
fail:
} while (retry < max_retry);
} while (retry < max_retry);
-
ixgbe_
release_swfw_sync(hw, swfw_mask);
+
hw->mac.ops.
release_swfw_sync(hw, swfw_mask);
read_byte_out:
return status;
read_byte_out:
return status;
@@
-1306,7
+1308,7
@@
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
else
swfw_mask = IXGBE_GSSR_PHY0_SM;
else
swfw_mask = IXGBE_GSSR_PHY0_SM;
- if (
ixgbe_
acquire_swfw_sync(hw, swfw_mask) != 0) {
+ if (
hw->mac.ops.
acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC;
goto write_byte_out;
}
status = IXGBE_ERR_SWFW_SYNC;
goto write_byte_out;
}
@@
-1350,7
+1352,7
@@
fail:
hw_dbg(hw, "I2C byte write error.\n");
} while (retry < max_retry);
hw_dbg(hw, "I2C byte write error.\n");
} while (retry < max_retry);
-
ixgbe_
release_swfw_sync(hw, swfw_mask);
+
hw->mac.ops.
release_swfw_sync(hw, swfw_mask);
write_byte_out:
return status;
write_byte_out:
return status;
@@
-1583,6
+1585,7
@@
static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
*i2cctl |= IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
*i2cctl |= IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
/* SCL rise time (1000ns) */
udelay(IXGBE_I2C_T_RISE);
/* SCL rise time (1000ns) */
udelay(IXGBE_I2C_T_RISE);
@@
-1603,6
+1606,7
@@
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
/* SCL fall time (300ns) */
udelay(IXGBE_I2C_T_FALL);
/* SCL fall time (300ns) */
udelay(IXGBE_I2C_T_FALL);
@@
-1626,6
+1630,7
@@
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);