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powerpc/perf_event: Fix Power6 L1 cache read & write event codes]
[pandora-kernel.git]
/
arch
/
powerpc
/
kernel
/
power6-pmu.c
diff --git
a/arch/powerpc/kernel/power6-pmu.c
b/arch/powerpc/kernel/power6-pmu.c
index
03b95e2
..
0bbc901
100644
(file)
--- a/
arch/powerpc/kernel/power6-pmu.c
+++ b/
arch/powerpc/kernel/power6-pmu.c
@@
-487,8
+487,8
@@
static int power6_generic_events[] = {
*/
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
*/
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
- [C(OP_READ)] = { 0x
80082,
0x80080 },
- [C(OP_WRITE)] = { 0x
80086,
0x80088 },
+ [C(OP_READ)] = { 0x
280030,
0x80080 },
+ [C(OP_WRITE)] = { 0x
180032,
0x80088 },
[C(OP_PREFETCH)] = { 0x810a4, 0 },
},
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_PREFETCH)] = { 0x810a4, 0 },
},
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */