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powerpc: Base support for exceptions using HSRR0/1
[pandora-kernel.git]
/
arch
/
powerpc
/
kernel
/
cpu_setup_power7.S
diff --git
a/arch/powerpc/kernel/cpu_setup_power7.S
b/arch/powerpc/kernel/cpu_setup_power7.S
index
f2b3178
..
e801ef1
100644
(file)
--- a/
arch/powerpc/kernel/cpu_setup_power7.S
+++ b/
arch/powerpc/kernel/cpu_setup_power7.S
@@
-52,13
+52,14
@@
__init_hvmode_206:
__init_LPCR:
/* Setup a sane LPCR:
*
__init_LPCR:
/* Setup a sane LPCR:
*
- * LPES = 0b
11 (
SRR0/1 used for 0x500)
+ * LPES = 0b
01 (H
SRR0/1 used for 0x500)
* PECE = 0b111
*
* Other bits untouched for now
*/
mfspr r3,SPRN_LPCR
ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
* PECE = 0b111
*
* Other bits untouched for now
*/
mfspr r3,SPRN_LPCR
ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
+ xori r3,r3, LPCR_LPES0
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
mtspr SPRN_LPCR,r3
isync
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
mtspr SPRN_LPCR,r3
isync