ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode

[pandora-kernel.git] / arch / arm / Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e084b7e..082bd36 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,7 +1,7 @@
 config ARM
        bool
        default y
 config ARM
        bool
        default y

-       select HAVE_AOUT
+       select ARCH_SUPPORTS_ATOMIC_RMW

        select HAVE_DMA_API_DEBUG
        select HAVE_IDE if PCI || ISA || PCMCIA
        select HAVE_MEMBLOCK
        select HAVE_DMA_API_DEBUG
        select HAVE_IDE if PCI || ISA || PCMCIA
        select HAVE_MEMBLOCK


@@ -220,8 +220,9 @@ config NEED_MACH_MEMORY_H
          be avoided when possible.
 
 config PHYS_OFFSET
          be avoided when possible.
 
 config PHYS_OFFSET

-       hex "Physical address of main memory"
+       hex "Physical address of main memory" if MMU

        depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
        depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H

+       default DRAM_BASE if !MMU

        help
          Please provide the physical address corresponding to the
          location of main memory in your system.
        help
          Please provide the physical address corresponding to the
          location of main memory in your system.


@@ -519,7 +520,7 @@ config ARCH_IXP4XX
        depends on MMU
        select CLKSRC_MMIO
        select CPU_XSCALE
        depends on MMU
        select CLKSRC_MMIO
        select CPU_XSCALE

-       select GENERIC_GPIO
+       select ARCH_REQUIRE_GPIOLIB

        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
        select MIGHT_HAVE_PCI
        select GENERIC_CLOCKEVENTS
        select HAVE_SCHED_CLOCK
        select MIGHT_HAVE_PCI


@@ -541,6 +542,7 @@ config ARCH_KIRKWOOD
        bool "Marvell Kirkwood"
        select CPU_FEROCEON
        select PCI
        bool "Marvell Kirkwood"
        select CPU_FEROCEON
        select PCI

+       select PCI_QUIRKS

        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
        select PLAT_ORION
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
        select PLAT_ORION


@@ -1154,6 +1156,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
 source "arch/arm/Kconfig-nommu"
 endif
 

+config ARM_ERRATA_326103
+       bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+       depends on CPU_V6
+       help
+         Executing a SWP instruction to read-only memory does not set bit 11
+         of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+         treat the access as a read, preventing a COW from occurring and
+         causing the faulting task to livelock.
+

 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K


@@ -1245,7 +1256,7 @@ config PL310_ERRATA_588369
 
 config ARM_ERRATA_720789
        bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
 
 config ARM_ERRATA_720789
        bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"

-       depends on CPU_V7 && SMP
+       depends on CPU_V7

        help
          This option enables the workaround for the 720789 Cortex-A9 (prior to
          r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
        help
          This option enables the workaround for the 720789 Cortex-A9 (prior to
          r2p0) erratum. A faulty ASID can be sent to the other CPUs for the


@@ -1271,7 +1282,7 @@ config ARM_ERRATA_743622
        depends on CPU_V7
        help
          This option enables the workaround for the 743622 Cortex-A9
        depends on CPU_V7
        help
          This option enables the workaround for the 743622 Cortex-A9

-         (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+         (r2p*) erratum. Under very rare conditions, a faulty

          optimisation in the Cortex-A9 Store Buffer may lead to data
          corruption. This workaround sets a specific bit in the diagnostic
          register of the Cortex-A9 which disables the Store Buffer
          optimisation in the Cortex-A9 Store Buffer may lead to data
          corruption. This workaround sets a specific bit in the diagnostic
          register of the Cortex-A9 which disables the Store Buffer


@@ -1281,7 +1292,7 @@ config ARM_ERRATA_743622
 
 config ARM_ERRATA_751472
        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
 
 config ARM_ERRATA_751472
        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"

-       depends on CPU_V7 && SMP
+       depends on CPU_V7

        help
          This option enables the workaround for the 751472 Cortex-A9 (prior
          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
        help
          This option enables the workaround for the 751472 Cortex-A9 (prior
          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the


@@ -2055,6 +2066,7 @@ source "drivers/cpufreq/Kconfig"
 config CPU_FREQ_IMX
        tristate "CPUfreq driver for i.MX CPUs"
        depends on ARCH_MXC && CPU_FREQ
 config CPU_FREQ_IMX
        tristate "CPUfreq driver for i.MX CPUs"
        depends on ARCH_MXC && CPU_FREQ

+       select CPU_FREQ_TABLE

        help
          This enables the CPUfreq driver for i.MX CPUs.
 
        help
          This enables the CPUfreq driver for i.MX CPUs.