2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
11 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCstation 10, 20, LX and Voyager models.
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formarly AT&T microelectronics) home
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, nr 0-15) or between two serial
31 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and nr of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) timemultiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the onboard
44 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
49 * I've tried to stick to the following function naming conventions:
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
56 #include <sound/driver.h>
57 #include <linux/interrupt.h>
58 #include <linux/delay.h>
60 #include <sound/core.h>
61 #include <sound/pcm.h>
62 #include <sound/pcm_params.h>
63 #include <sound/info.h>
64 #include <sound/control.h>
65 #include <sound/initval.h>
70 #include <asm/atomic.h>
72 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73 MODULE_DESCRIPTION("Sun DBRI");
74 MODULE_LICENSE("GPL");
75 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
77 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
79 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
97 static int dbri_debug;
98 module_param(dbri_debug, int, 0644);
99 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
102 static char *cmds[] = {
103 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
104 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
107 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
110 #define dprintk(a, x...) do { } while (0)
112 #endif /* DBRI_DEBUG */
114 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
118 /***************************************************************************
119 CS4215 specific definitions and structures
120 ****************************************************************************/
123 __u8 data[4]; /* Data mode: Time slots 5-8 */
124 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
126 __u8 offset; /* Bit offset from frame sync to time slot 1 */
127 volatile __u32 status;
128 volatile __u32 version;
129 __u8 precision; /* In bits, either 8 or 16 */
130 __u8 channels; /* 1 or 2 */
137 /* Time Slot 1, Status register */
138 #define CS4215_CLB (1<<2) /* Control Latch Bit */
139 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
140 /* 0: line: 2.8V, speaker 8V */
141 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
142 #define CS4215_RSRVD_1 (1<<5)
144 /* Time Slot 2, Data Format Register */
145 #define CS4215_DFR_LINEAR16 0
146 #define CS4215_DFR_ULAW 1
147 #define CS4215_DFR_ALAW 2
148 #define CS4215_DFR_LINEAR8 3
149 #define CS4215_DFR_STEREO (1<<2)
155 { 8000, (1 << 4), (0 << 3) },
156 { 16000, (1 << 4), (1 << 3) },
157 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
158 { 32000, (1 << 4), (3 << 3) },
159 /* { NA, (1 << 4), (4 << 3) }, */
160 /* { NA, (1 << 4), (5 << 3) }, */
161 { 48000, (1 << 4), (6 << 3) },
162 { 9600, (1 << 4), (7 << 3) },
163 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
164 { 11025, (2 << 4), (1 << 3) },
165 { 18900, (2 << 4), (2 << 3) },
166 { 22050, (2 << 4), (3 << 3) },
167 { 37800, (2 << 4), (4 << 3) },
168 { 44100, (2 << 4), (5 << 3) },
169 { 33075, (2 << 4), (6 << 3) },
170 { 6615, (2 << 4), (7 << 3) },
174 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
176 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
178 /* Time Slot 3, Serial Port Control register */
179 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
180 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
181 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
182 #define CS4215_BSEL_128 (1<<2)
183 #define CS4215_BSEL_256 (2<<2)
184 #define CS4215_MCK_MAST (0<<4) /* Master clock */
185 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
186 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
187 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
188 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
190 /* Time Slot 4, Test Register */
191 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
192 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
194 /* Time Slot 5, Parallel Port Register */
195 /* Read only here and the same as the in data mode */
197 /* Time Slot 6, Reserved */
199 /* Time Slot 7, Version Register */
200 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
202 /* Time Slot 8, Reserved */
207 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
209 /* Time Slot 5, Output Setting */
210 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
211 #define CS4215_LE (1<<6) /* Line Out Enable */
212 #define CS4215_HE (1<<7) /* Headphone Enable */
214 /* Time Slot 6, Output Setting */
215 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_SE (1<<6) /* Speaker Enable */
217 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
219 /* Time Slot 7, Input Setting */
220 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
221 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
222 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
223 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
224 #define CS4215_PIO1 (1<<7)
226 /* Time Slot 8, Input Setting */
227 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
228 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
230 /***************************************************************************
231 DBRI specific definitions and structures
232 ****************************************************************************/
234 /* DBRI main registers */
235 #define REG0 0x00UL /* Status and Control */
236 #define REG1 0x04UL /* Mode and Interrupt */
237 #define REG2 0x08UL /* Parallel IO */
238 #define REG3 0x0cUL /* Test */
239 #define REG8 0x20UL /* Command Queue Pointer */
240 #define REG9 0x24UL /* Interrupt Queue Pointer */
242 #define DBRI_NO_CMDS 64
243 #define DBRI_INT_BLK 64
244 #define DBRI_NO_DESCS 64
245 #define DBRI_NO_PIPES 32
246 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
250 #define DBRI_NO_STREAMS 2
252 /* One transmit/receive descriptor */
253 /* When ba != 0 descriptor is used */
255 volatile __u32 word1;
256 __u32 ba; /* Transmit/Receive Buffer Address */
257 __u32 nda; /* Next Descriptor Address */
258 volatile __u32 word4;
261 /* This structure is in a DMA region where it can accessed by both
262 * the CPU and the DBRI
265 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
266 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
267 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
270 #define dbri_dma_off(member, elem) \
271 ((u32)(unsigned long) \
272 (&(((struct dbri_dma *)0)->member[elem])))
274 enum in_or_out { PIPEinput, PIPEoutput };
277 u32 sdp; /* SDP command word */
278 int nextpipe; /* Next pipe in linked list */
279 int length; /* Length of timeslot (bits) */
280 int first_desc; /* Index of first descriptor */
281 int desc; /* Index of active descriptor */
282 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
285 /* Per stream (playback or record) information */
286 struct dbri_streaminfo {
287 struct snd_pcm_substream *substream;
288 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
289 int size; /* Size of DMA buffer */
290 size_t offset; /* offset in user buffer */
291 int pipe; /* Data pipe used */
292 int left_gain; /* mixer elements */
296 /* This structure holds the information for both chips (DBRI & CS4215) */
298 struct snd_card *card; /* ALSA card */
300 int regs_size, irq; /* Needed for unload */
301 struct sbus_dev *sdev; /* SBUS device info */
304 struct dbri_dma *dma; /* Pointer to our DMA block */
305 u32 dma_dvma; /* DBRI visible DMA address */
307 void __iomem *regs; /* dbri HW regs */
308 int dbri_irqp; /* intr queue pointer */
310 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
311 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
312 spinlock_t cmdlock; /* Protects cmd queue accesses */
313 s32 *cmdptr; /* Pointer to the last queued cmd */
317 struct cs4215 mm; /* mmcodec special info */
318 /* per stream (playback/record) info */
319 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
321 struct snd_dbri *next;
324 #define DBRI_MAX_VOLUME 63 /* Output volume */
325 #define DBRI_MAX_GAIN 15 /* Input gain */
327 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328 #define D_P (1<<15) /* Program command & queue pointer valid */
329 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
330 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
331 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
332 #define D_X (1<<7) /* Sanity Timer Disable */
333 #define D_T (1<<6) /* Permit activation of the TE interface */
334 #define D_N (1<<5) /* Permit activation of the NT interface */
335 #define D_C (1<<4) /* Permit activation of the CHI interface */
336 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
337 #define D_D (1<<2) /* Disable Master Mode */
338 #define D_H (1<<1) /* Halt for Analysis */
339 #define D_R (1<<0) /* Soft Reset */
341 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342 #define D_LITTLE_END (1<<8) /* Byte Order */
343 #define D_BIG_END (0<<8) /* Byte Order */
344 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
345 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
346 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
347 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
348 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
350 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355 #define D_ENPIO (0xf0) /* Enable all the pins */
356 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
361 /* DBRI Commands (Page 20) */
362 #define D_WAIT 0x0 /* Stop execution */
363 #define D_PAUSE 0x1 /* Flush long pipes */
364 #define D_JUMP 0x2 /* New command queue */
365 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
366 #define D_REX 0x4 /* Report command execution via interrupt */
367 #define D_SDP 0x5 /* Setup Data Pipe */
368 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369 #define D_DTS 0x7 /* Define Time Slot */
370 #define D_SSP 0x8 /* Set short Data Pipe */
371 #define D_CHI 0x9 /* Set CHI Global Mode */
372 #define D_NT 0xa /* NT Command */
373 #define D_TE 0xb /* TE Command */
374 #define D_CDEC 0xc /* Codec setup */
375 #define D_TEST 0xd /* No comment */
376 #define D_CDM 0xe /* CHI Data mode command */
378 /* Special bits for some commands */
379 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
381 /* Setup Data Pipe */
383 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
384 #define D_SDP_CHANGE (2<<18) /* Report any changes */
385 #define D_SDP_EVERY (3<<18) /* Report any changes */
386 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
390 #define D_SDP_MEM (0<<13) /* To/from memory */
391 #define D_SDP_HDLC (2<<13)
392 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393 #define D_SDP_SER (4<<13) /* Serial to serial */
394 #define D_SDP_FIXED (6<<13) /* Short only */
395 #define D_SDP_MODE(v) ((v)&(7<<13))
397 #define D_SDP_TO_SER (1<<12) /* Direction */
398 #define D_SDP_FROM_SER (0<<12) /* Direction */
399 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
400 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
401 #define D_SDP_P (1<<10) /* Pointer Valid */
402 #define D_SDP_A (1<<8) /* Abort */
403 #define D_SDP_C (1<<7) /* Clear */
405 /* Define Time Slot */
406 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408 #define D_DTS_INS (1<<15) /* Insert Time Slot */
409 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
410 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
413 /* Time Slot defines */
414 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416 #define D_TS_DI (1<<13) /* Data Invert */
417 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
419 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
424 /* Concentration Highway Interface Modes */
425 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428 #define D_CHI_OD (1<<13) /* Open Drain Enable */
429 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430 #define D_CHI_FD (1<<11) /* Frame Drive */
431 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
433 /* NT: These are here for completeness */
434 #define D_NT_FBIT (1<<17) /* Frame Bit */
435 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
439 #define D_NT_FT (1<<12) /* Fixed Timing */
440 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442 #define D_NT_ACT (1<<9) /* Activate Interface */
443 #define D_NT_MFE (1<<8) /* Multiframe Enable */
444 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446 #define D_NT_FACT (1<<1) /* Force Activation */
447 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
450 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
455 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456 #define D_TEST_SIZE(v) ((v)<<11) /* */
457 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458 #define D_TEST_PROC 0x6 /* MicroProcessor test */
459 #define D_TEST_SER 0x7 /* Serial-Controller test */
460 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464 #define D_TEST_DUMP 0xe /* ROM Dump */
467 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
468 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
469 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
470 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
471 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
472 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
475 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
476 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479 #define D_INTR_EOL 5 /* End of List */
480 #define D_INTR_CMDI 6 /* Command has bean read */
481 #define D_INTR_XCMP 8 /* Transmission of frame complete */
482 #define D_INTR_SBRI 9 /* BRI status change info */
483 #define D_INTR_FXDT 10 /* Fixed data change */
484 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486 #define D_INTR_DBYT 12 /* Dropped by frame slip */
487 #define D_INTR_RBYT 13 /* Repeated by frame slip */
488 #define D_INTR_LINT 14 /* Lost Interrupt */
489 #define D_INTR_UNDR 15 /* DMA underrun */
493 #define D_INTR_CHI 36
494 #define D_INTR_CMD 38
496 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
497 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
498 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
499 #define D_INTR_GETVAL(v) ((v) & 0xffff)
500 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
502 #define D_P_0 0 /* TE receive anchor */
503 #define D_P_1 1 /* TE transmit anchor */
504 #define D_P_2 2 /* NT transmit anchor */
505 #define D_P_3 3 /* NT receive anchor */
506 #define D_P_4 4 /* CHI send data */
507 #define D_P_5 5 /* CHI receive data */
508 #define D_P_6 6 /* */
509 #define D_P_7 7 /* */
510 #define D_P_8 8 /* */
511 #define D_P_9 9 /* */
512 #define D_P_10 10 /* */
513 #define D_P_11 11 /* */
514 #define D_P_12 12 /* */
515 #define D_P_13 13 /* */
516 #define D_P_14 14 /* */
517 #define D_P_15 15 /* */
518 #define D_P_16 16 /* CHI anchor pipe */
519 #define D_P_17 17 /* CHI send */
520 #define D_P_18 18 /* CHI receive */
521 #define D_P_19 19 /* CHI receive */
522 #define D_P_20 20 /* CHI receive */
523 #define D_P_21 21 /* */
524 #define D_P_22 22 /* */
525 #define D_P_23 23 /* */
526 #define D_P_24 24 /* */
527 #define D_P_25 25 /* */
528 #define D_P_26 26 /* */
529 #define D_P_27 27 /* */
530 #define D_P_28 28 /* */
531 #define D_P_29 29 /* */
532 #define D_P_30 30 /* */
533 #define D_P_31 31 /* */
535 /* Transmit descriptor defines */
536 #define DBRI_TD_F (1<<31) /* End of Frame */
537 #define DBRI_TD_D (1<<30) /* Do not append CRC */
538 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
539 #define DBRI_TD_B (1<<15) /* Final interrupt */
540 #define DBRI_TD_M (1<<14) /* Marker interrupt */
541 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
542 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
543 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
544 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
545 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
546 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8Kb */
548 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
550 /* Receive descriptor defines */
551 #define DBRI_RD_F (1<<31) /* End of Frame */
552 #define DBRI_RD_C (1<<30) /* Completed buffer */
553 #define DBRI_RD_B (1<<15) /* Final interrupt */
554 #define DBRI_RD_M (1<<14) /* Marker interrupt */
555 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
556 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
557 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
558 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
559 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
560 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
561 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
563 /* stream_info[] access */
564 /* Translate the ALSA direction into the array index */
565 #define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
569 /* Return a pointer to dbri_streaminfo */
570 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
572 static struct snd_dbri *dbri_list; /* All DBRI devices */
575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
576 * So we have to reverse the bits. Note: not all bit lengths are supported
578 static __u32 reverse_bytes(__u32 b, int len)
582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
584 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
586 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
588 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
590 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
595 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
602 ****************************************************************************
603 ************** DBRI initialization and command synchronization *************
604 ****************************************************************************
606 Commands are sent to the DBRI by building a list of them in memory,
607 then writing the address of the first list item to DBRI register 8.
608 The list is terminated with a WAIT command, which generates a
609 CPU interrupt to signal completion.
611 Since the DBRI can run in parallel with the CPU, several means of
612 synchronization present themselves. The method implemented here is only
613 use of the dbri_cmdwait() to wait for execution of batch of sent commands.
615 A circular command buffer is used here. A new command is being added
616 while another can be executed. The scheme works by adding two WAIT commands
617 after each sent batch of commands. When the next batch is prepared it is
618 added after the WAIT commands then the WAITs are replaced with single JUMP
619 command to the new batch. The the DBRI is forced to reread the last WAIT
620 command (replaced by the JUMP by then). If the DBRI is still executing
621 previous commands the request to reread the WAIT command is ignored.
623 Every time a routine wants to write commands to the DBRI, it must
624 first call dbri_cmdlock() and get pointer to a free space in
625 dbri->dma->cmd buffer. After this, the commands can be written to
626 the buffer, and dbri_cmdsend() is called with the final pointer value
627 to send them to the DBRI.
633 * Wait for the current command string to execute
635 static void dbri_cmdwait(struct snd_dbri *dbri)
637 int maxloops = MAXLOOPS;
639 /* Delay if previous commands are still being processed */
640 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P))
641 msleep_interruptible(1);
644 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
646 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
647 MAXLOOPS - maxloops - 1);
651 * Lock the command queue and returns pointer to a space for len cmd words
652 * It locks the cmdlock spinlock.
654 static s32 *dbri_cmdlock(struct snd_dbri * dbri, int len)
656 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
658 spin_lock(&dbri->cmdlock);
659 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
660 return dbri->cmdptr + 2;
661 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
662 return dbri->dma->cmd;
664 printk(KERN_ERR "DBRI: no space for commands.");
670 * Send prepared cmd string. It works by writting a JUMP cmd into
671 * the last WAIT cmd and force DBRI to reread the cmd.
672 * The JUMP cmd points to the new cmd string.
673 * It also releases the cmdlock spinlock.
675 static void dbri_cmdsend(struct snd_dbri * dbri, s32 * cmd,int len)
679 static int wait_id = 0;
682 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
683 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
684 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
686 /* Replace the last command with JUMP */
687 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
688 *(dbri->cmdptr+1) = addr;
689 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
692 if (cmd > dbri->cmdptr) {
695 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
696 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
698 s32 *ptr = dbri->cmdptr;
700 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
702 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
703 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) {
704 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
709 spin_lock_irqsave(&dbri->lock, flags);
710 /* Reread the last command */
711 tmp = sbus_readl(dbri->regs + REG0);
713 sbus_writel(tmp, dbri->regs + REG0);
714 spin_unlock_irqrestore(&dbri->lock, flags);
717 spin_unlock(&dbri->cmdlock);
720 /* Lock must be held when calling this */
721 static void dbri_reset(struct snd_dbri * dbri)
726 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
727 sbus_readl(dbri->regs + REG0),
728 sbus_readl(dbri->regs + REG2),
729 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
731 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
732 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
735 /* A brute approach - DBRI falls back to working burst size by itself
736 * On SS20 D_S does not work, so do not try so high. */
737 tmp = sbus_readl(dbri->regs + REG0);
740 sbus_writel(tmp, dbri->regs + REG0);
743 /* Lock must not be held before calling this */
744 static void dbri_initialize(struct snd_dbri * dbri)
751 spin_lock_irqsave(&dbri->lock, flags);
755 /* Initialize pipes */
756 for (n = 0; n < DBRI_NO_PIPES; n++)
757 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
759 spin_lock_init(&dbri->cmdlock);
761 * Initialize the interrupt ringbuffer.
763 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
764 dbri->dma->intr[0] = dma_addr;
767 * Set up the interrupt queue
769 spin_lock(&dbri->cmdlock);
770 cmd = dbri->cmdptr = dbri->dma->cmd;
771 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
773 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
775 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
776 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
777 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
778 sbus_writel(dma_addr, dbri->regs + REG8);
779 spin_unlock(&dbri->cmdlock);
782 spin_unlock_irqrestore(&dbri->lock, flags);
786 ****************************************************************************
787 ************************** DBRI data pipe management ***********************
788 ****************************************************************************
790 While DBRI control functions use the command and interrupt buffers, the
791 main data path takes the form of data pipes, which can be short (command
792 and interrupt driven), or long (attached to DMA buffers). These functions
793 provide a rudimentary means of setting up and managing the DBRI's pipes,
794 but the calling functions have to make sure they respect the pipes' linked
795 list ordering, among other things. The transmit and receive functions
796 here interface closely with the transmit and receive interrupt code.
799 static int pipe_active(struct snd_dbri * dbri, int pipe)
801 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
804 /* reset_pipe(dbri, pipe)
806 * Called on an in-use pipe to clear anything being transmitted or received
807 * Lock must be held before calling this.
809 static void reset_pipe(struct snd_dbri * dbri, int pipe)
815 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
816 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
820 sdp = dbri->pipes[pipe].sdp;
822 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
826 cmd = dbri_cmdlock(dbri, 3);
827 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
829 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
830 dbri_cmdsend(dbri, cmd, 3);
832 desc = dbri->pipes[pipe].first_desc;
835 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
836 desc = dbri->next_desc[desc];
837 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
839 dbri->pipes[pipe].desc = -1;
840 dbri->pipes[pipe].first_desc = -1;
843 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
845 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
846 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
850 if ((sdp & 0xf800) != sdp) {
851 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
855 /* If this is a fixed receive pipe, arrange for an interrupt
856 * every time its data changes
858 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
862 dbri->pipes[pipe].sdp = sdp;
863 dbri->pipes[pipe].desc = -1;
864 dbri->pipes[pipe].first_desc = -1;
866 reset_pipe(dbri, pipe);
869 static void link_time_slot(struct snd_dbri * dbri, int pipe,
870 int prevpipe, int nextpipe,
871 int length, int cycle)
876 if (pipe < 0 || pipe > DBRI_MAX_PIPE
877 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
878 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
880 "DBRI: link_time_slot called with illegal pipe number\n");
884 if (dbri->pipes[pipe].sdp == 0
885 || dbri->pipes[prevpipe].sdp == 0
886 || dbri->pipes[nextpipe].sdp == 0) {
887 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
891 dbri->pipes[prevpipe].nextpipe = pipe;
892 dbri->pipes[pipe].nextpipe = nextpipe;
893 dbri->pipes[pipe].length = length;
895 cmd = dbri_cmdlock(dbri, 4);
897 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
898 /* Deal with CHI special case:
899 * "If transmission on edges 0 or 1 is desired, then cycle n
900 * (where n = # of bit times per frame...) must be used."
901 * - DBRI data sheet, page 11
903 if (prevpipe == 16 && cycle == 0)
904 cycle = dbri->chi_bpf;
906 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
907 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
910 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
912 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
913 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
915 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
918 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
920 dbri_cmdsend(dbri, cmd, 4);
923 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
924 enum in_or_out direction, int prevpipe,
930 if (pipe < 0 || pipe > DBRI_MAX_PIPE
931 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
932 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
934 "DBRI: unlink_time_slot called with illegal pipe number\n");
938 cmd = dbri_cmdlock(dbri, 4);
940 if (direction == PIPEinput) {
941 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
942 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
943 *(cmd++) = D_TS_NEXT(nextpipe);
946 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
947 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
949 *(cmd++) = D_TS_NEXT(nextpipe);
951 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
953 dbri_cmdsend(dbri, cmd, 4);
956 /* xmit_fixed() / recv_fixed()
958 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
959 * expected to change much, and which we don't need to buffer.
960 * The DBRI only interrupts us when the data changes (receive pipes),
961 * or only changes the data when this function is called (transmit pipes).
962 * Only short pipes (numbers 16-31) can be used in fixed data mode.
964 * These function operate on a 32-bit field, no matter how large
965 * the actual time slot is. The interrupt handler takes care of bit
966 * ordering and alignment. An 8-bit time slot will always end up
967 * in the low-order 8 bits, filled either MSB-first or LSB-first,
968 * depending on the settings passed to setup_pipe()
970 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
974 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
975 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
979 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
980 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
984 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
985 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
989 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
990 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
994 /* DBRI short pipes always transmit LSB first */
996 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
997 data = reverse_bytes(data, dbri->pipes[pipe].length);
999 cmd = dbri_cmdlock(dbri, 3);
1001 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1003 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1005 dbri_cmdsend(dbri, cmd, 3);
1009 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1011 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1012 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1016 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1017 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1021 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1022 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1026 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1031 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1032 * with a DMA buffer.
1034 * Only pipe numbers 0-15 can be used in this mode.
1036 * This function takes a stream number pointing to a data buffer,
1037 * and work by building chains of descriptors which identify the
1038 * data buffers. Buffers too large for a single descriptor will
1039 * be spread across multiple descriptors.
1041 * All descriptors create a ring buffer.
1043 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1045 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1049 int first_desc = -1;
1052 if (info->pipe < 0 || info->pipe > 15) {
1053 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1057 if (dbri->pipes[info->pipe].sdp == 0) {
1058 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1063 dvma_buffer = info->dvma_buffer;
1066 if (streamno == DBRI_PLAY) {
1067 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1068 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1073 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1075 "DBRI: setup_descs: Called on transmit pipe %d\n",
1079 /* Should be able to queue multiple buffers to receive on a pipe */
1080 if (pipe_active(dbri, info->pipe)) {
1081 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1086 /* Make sure buffer size is multiple of four */
1090 /* Free descriptors if pipe has any */
1091 desc = dbri->pipes[info->pipe].first_desc;
1094 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
1095 desc = dbri->next_desc[desc];
1096 } while (desc != -1 && desc != dbri->pipes[info->pipe].first_desc);
1098 dbri->pipes[info->pipe].desc = -1;
1099 dbri->pipes[info->pipe].first_desc = -1;
1105 for (; desc < DBRI_NO_DESCS; desc++) {
1106 if (!dbri->dma->desc[desc].ba)
1109 if (desc == DBRI_NO_DESCS) {
1110 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1114 if (len > DBRI_TD_MAXCNT)
1115 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1122 dbri->next_desc[desc] = -1;
1123 dbri->dma->desc[desc].ba = dvma_buffer;
1124 dbri->dma->desc[desc].nda = 0;
1126 if (streamno == DBRI_PLAY) {
1127 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1128 dbri->dma->desc[desc].word4 = 0;
1129 dbri->dma->desc[desc].word1 |=
1130 DBRI_TD_F | DBRI_TD_B;
1132 dbri->dma->desc[desc].word1 = 0;
1133 dbri->dma->desc[desc].word4 =
1134 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1137 if (first_desc == -1)
1140 dbri->next_desc[last_desc] = desc;
1141 dbri->dma->desc[last_desc].nda =
1142 dbri->dma_dvma + dbri_dma_off(desc, desc);
1146 dvma_buffer += mylen;
1150 if (first_desc == -1 || last_desc == -1) {
1151 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1155 dbri->dma->desc[last_desc].nda =
1156 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1157 dbri->next_desc[last_desc] = first_desc;
1158 dbri->pipes[info->pipe].first_desc = first_desc;
1159 dbri->pipes[info->pipe].desc = first_desc;
1162 for (desc = first_desc; desc != -1; ) {
1163 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1165 dbri->dma->desc[desc].word1,
1166 dbri->dma->desc[desc].ba,
1167 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1168 desc = dbri->next_desc[desc];
1169 if ( desc == first_desc )
1177 ****************************************************************************
1178 ************************** DBRI - CHI interface ****************************
1179 ****************************************************************************
1181 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1182 multiplexed serial interface which the DBRI can operate in either master
1183 (give clock/frame sync) or slave (take clock/frame sync) mode.
1187 enum master_or_slave { CHImaster, CHIslave };
1189 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1195 /* Set CHI Anchor: Pipe 16 */
1197 cmd = dbri_cmdlock(dbri, 4);
1198 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1199 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1200 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1201 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1202 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1203 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1204 dbri_cmdsend(dbri, cmd, 4);
1206 dbri->pipes[16].sdp = 1;
1207 dbri->pipes[16].nextpipe = 16;
1209 cmd = dbri_cmdlock(dbri, 4);
1211 if (master_or_slave == CHIslave) {
1212 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1214 * CHICM = 0 (slave mode, 8 kHz frame rate)
1215 * IR = give immediate CHI status interrupt
1216 * EN = give CHI status interrupt upon change
1218 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1220 /* Setup DBRI for CHI Master - generate clock, FS
1222 * BPF = bits per 8 kHz frame
1223 * 12.288 MHz / CHICM_divisor = clock rate
1224 * FD = 1 - drive CHIFS on rising edge of CHICK
1226 int clockrate = bits_per_frame * 8;
1227 int divisor = 12288 / clockrate;
1229 if (divisor > 255 || divisor * clockrate != 12288)
1230 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1232 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1233 | D_CHI_BPF(bits_per_frame));
1236 dbri->chi_bpf = bits_per_frame;
1240 * RCE = 0 - receive on falling edge of CHICK
1241 * XCE = 1 - transmit on rising edge of CHICK
1242 * XEN = 1 - enable transmitter
1243 * REN = 1 - enable receiver
1246 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1247 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1248 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1250 dbri_cmdsend(dbri, cmd, 4);
1254 ****************************************************************************
1255 *********************** CS4215 audio codec management **********************
1256 ****************************************************************************
1258 In the standard SPARC audio configuration, the CS4215 codec is attached
1259 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1262 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1266 * Pipe 4: Send timeslots 1-4 (audio data)
1267 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1268 * Pipe 6: Receive timeslots 1-4 (audio data)
1269 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1270 * interrupt, and the rest of the data (slot 5 and 8) is
1271 * not relevant for us (only for doublechecking).
1274 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1275 * Pipe 18: Receive timeslot 1 (clb).
1276 * Pipe 19: Receive timeslot 7 (version).
1279 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1280 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1281 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1282 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1284 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1285 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1286 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1291 static int cs4215_init_data(struct cs4215 *mm)
1294 * No action, memory resetting only.
1296 * Data Time Slot 5-8
1297 * Speaker,Line and Headphone enable. Gain set to the half.
1300 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1301 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1302 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1303 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1306 * Control Time Slot 1-4
1307 * 0: Default I/O voltage scale
1308 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1309 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1312 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1313 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1314 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1319 mm->precision = 8; /* For ULAW */
1325 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1328 dbri->mm.data[0] |= 63;
1329 dbri->mm.data[1] |= 63;
1330 dbri->mm.data[2] &= ~15;
1331 dbri->mm.data[3] &= ~15;
1333 /* Start by setting the playback attenuation. */
1334 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1335 int left_gain = info->left_gain & 0x3f;
1336 int right_gain = info->right_gain & 0x3f;
1338 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1339 dbri->mm.data[1] &= ~0x3f;
1340 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1341 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1343 /* Now set the recording gain. */
1344 info = &dbri->stream_info[DBRI_REC];
1345 left_gain = info->left_gain & 0xf;
1346 right_gain = info->right_gain & 0xf;
1347 dbri->mm.data[2] |= CS4215_LG(left_gain);
1348 dbri->mm.data[3] |= CS4215_RG(right_gain);
1351 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1355 * Set the CS4215 to data mode.
1357 static void cs4215_open(struct snd_dbri * dbri)
1362 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1363 dbri->mm.channels, dbri->mm.precision);
1365 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1366 * to make sure this takes. This avoids clicking noises.
1369 cs4215_setdata(dbri, 1);
1374 * Pipe 4: Send timeslots 1-4 (audio data)
1375 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1376 * Pipe 6: Receive timeslots 1-4 (audio data)
1377 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1378 * interrupt, and the rest of the data (slot 5 and 8) is
1379 * not relevant for us (only for doublechecking).
1381 * Just like in control mode, the time slots are all offset by eight
1382 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1383 * even if it's the CHI master. Don't ask me...
1385 tmp = sbus_readl(dbri->regs + REG0);
1386 tmp &= ~(D_C); /* Disable CHI */
1387 sbus_writel(tmp, dbri->regs + REG0);
1389 /* Switch CS4215 to data mode - set PIO3 to 1 */
1390 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1391 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1393 reset_chi(dbri, CHIslave, 128);
1395 /* Note: this next doesn't work for 8-bit stereo, because the two
1396 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1397 * (See CS4215 datasheet Fig 15)
1399 * DBRI non-contiguous mode would be required to make this work.
1401 data_width = dbri->mm.channels * dbri->mm.precision;
1403 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1404 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1405 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1406 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1408 /* FIXME: enable CHI after _setdata? */
1409 tmp = sbus_readl(dbri->regs + REG0);
1410 tmp |= D_C; /* Enable CHI */
1411 sbus_writel(tmp, dbri->regs + REG0);
1413 cs4215_setdata(dbri, 0);
1417 * Send the control information (i.e. audio format)
1419 static int cs4215_setctrl(struct snd_dbri * dbri)
1424 /* FIXME - let the CPU do something useful during these delays */
1426 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1427 * to make sure this takes. This avoids clicking noises.
1429 cs4215_setdata(dbri, 1);
1433 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1434 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1436 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1437 sbus_writel(val, dbri->regs + REG2);
1438 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1441 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1442 * operate as CHI master, supplying clocking and frame synchronization.
1444 * In Data mode, however, the CS4215 must be CHI master to insure
1445 * that its data stream is synchronous with its codec.
1447 * The upshot of all this? We start by putting the DBRI into master
1448 * mode, program the CS4215 in Control mode, then switch the CS4215
1449 * into Data mode and put the DBRI into slave mode. Various timing
1450 * requirements must be observed along the way.
1452 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1453 * others?), the addressing of the CS4215's time slots is
1454 * offset by eight bits, so we add eight to all the "cycle"
1455 * values in the Define Time Slot (DTS) commands. This is
1456 * done in hardware by a TI 248 that delays the DBRI->4215
1457 * frame sync signal by eight clock cycles. Anybody know why?
1459 tmp = sbus_readl(dbri->regs + REG0);
1460 tmp &= ~D_C; /* Disable CHI */
1461 sbus_writel(tmp, dbri->regs + REG0);
1463 reset_chi(dbri, CHImaster, 128);
1467 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1468 * Pipe 18: Receive timeslot 1 (clb).
1469 * Pipe 19: Receive timeslot 7 (version).
1472 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1473 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1474 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1476 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1477 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1478 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1480 tmp = sbus_readl(dbri->regs + REG0);
1481 tmp |= D_C; /* Enable CHI */
1482 sbus_writel(tmp, dbri->regs + REG0);
1484 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1485 msleep_interruptible(1);
1488 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1493 /* Disable changes to our copy of the version number, as we are about
1494 * to leave control mode.
1496 recv_fixed(dbri, 19, NULL);
1498 /* Terminate CS4215 control mode - data sheet says
1499 * "Set CLB=1 and send two more frames of valid control info"
1501 dbri->mm.ctrl[0] |= CS4215_CLB;
1502 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1504 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1507 cs4215_setdata(dbri, 0);
1513 * Setup the codec with the sampling rate, audio format and number of
1515 * As part of the process we resend the settings for the data
1516 * timeslots as well.
1518 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1519 snd_pcm_format_t format, unsigned int channels)
1524 /* Lookup index for this rate */
1525 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1526 if (CS4215_FREQ[freq_idx].freq == rate)
1529 if (CS4215_FREQ[freq_idx].freq != rate) {
1530 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1535 case SNDRV_PCM_FORMAT_MU_LAW:
1536 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1537 dbri->mm.precision = 8;
1539 case SNDRV_PCM_FORMAT_A_LAW:
1540 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1541 dbri->mm.precision = 8;
1543 case SNDRV_PCM_FORMAT_U8:
1544 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1545 dbri->mm.precision = 8;
1547 case SNDRV_PCM_FORMAT_S16_BE:
1548 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1549 dbri->mm.precision = 16;
1552 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1556 /* Add rate parameters */
1557 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1558 dbri->mm.ctrl[2] = CS4215_XCLK |
1559 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1561 dbri->mm.channels = channels;
1563 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1565 ret = cs4215_setctrl(dbri);
1567 cs4215_open(dbri); /* set codec to data mode */
1575 static int cs4215_init(struct snd_dbri * dbri)
1577 u32 reg2 = sbus_readl(dbri->regs + REG2);
1578 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1580 /* Look for the cs4215 chips */
1581 if (reg2 & D_PIO2) {
1582 dprintk(D_MM, "Onboard CS4215 detected\n");
1583 dbri->mm.onboard = 1;
1585 if (reg2 & D_PIO0) {
1586 dprintk(D_MM, "Speakerbox detected\n");
1587 dbri->mm.onboard = 0;
1589 if (reg2 & D_PIO2) {
1590 printk(KERN_INFO "DBRI: Using speakerbox / "
1591 "ignoring onboard mmcodec.\n");
1592 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1596 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1597 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1601 cs4215_setup_pipes(dbri);
1602 cs4215_init_data(&dbri->mm);
1604 /* Enable capture of the status & version timeslots. */
1605 recv_fixed(dbri, 18, &dbri->mm.status);
1606 recv_fixed(dbri, 19, &dbri->mm.version);
1608 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1609 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1610 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1614 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1620 ****************************************************************************
1621 *************************** DBRI interrupt handler *************************
1622 ****************************************************************************
1624 The DBRI communicates with the CPU mainly via a circular interrupt
1625 buffer. When an interrupt is signaled, the CPU walks through the
1626 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1627 Complicated interrupts are handled by dedicated functions (which
1628 appear first in this file). Any pending interrupts can be serviced by
1629 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1630 interrupts are disabled.
1636 * Starts transmiting the current TD's for recording/playing.
1637 * For playback, ALSA has filled the DMA memory with new data (we hope).
1639 static void xmit_descs(struct snd_dbri *dbri)
1641 struct dbri_streaminfo *info;
1643 unsigned long flags;
1647 return; /* Disabled */
1649 info = &dbri->stream_info[DBRI_REC];
1650 spin_lock_irqsave(&dbri->lock, flags);
1652 if (info->pipe >= 0) {
1653 first_td = dbri->pipes[info->pipe].first_desc;
1655 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1657 /* Stream could be closed by the time we run. */
1658 if (first_td >= 0) {
1659 cmd = dbri_cmdlock(dbri, 2);
1660 *(cmd++) = DBRI_CMD(D_SDP, 0,
1661 dbri->pipes[info->pipe].sdp
1662 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1663 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1664 dbri_cmdsend(dbri, cmd, 2);
1666 /* Reset our admin of the pipe. */
1667 dbri->pipes[info->pipe].desc = first_td;
1671 info = &dbri->stream_info[DBRI_PLAY];
1673 if (info->pipe >= 0) {
1674 first_td = dbri->pipes[info->pipe].first_desc;
1676 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1678 /* Stream could be closed by the time we run. */
1679 if (first_td >= 0) {
1680 cmd = dbri_cmdlock(dbri, 2);
1681 *(cmd++) = DBRI_CMD(D_SDP, 0,
1682 dbri->pipes[info->pipe].sdp
1683 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1684 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1685 dbri_cmdsend(dbri, cmd, 2);
1687 /* Reset our admin of the pipe. */
1688 dbri->pipes[info->pipe].desc = first_td;
1691 spin_unlock_irqrestore(&dbri->lock, flags);
1694 /* transmission_complete_intr()
1696 * Called by main interrupt handler when DBRI signals transmission complete
1697 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1699 * Walks through the pipe's list of transmit buffer descriptors and marks
1700 * them as available. Stops when the first descriptor is found without
1701 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1703 * The DMA buffers are not released. They form a ring buffer and
1704 * they are filled by ALSA while others are transmitted by DMA.
1708 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1710 struct dbri_streaminfo *info;
1714 info = &dbri->stream_info[DBRI_PLAY];
1716 td = dbri->pipes[pipe].desc;
1718 if (td >= DBRI_NO_DESCS) {
1719 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1723 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1724 if (!(status & DBRI_TD_TBC)) {
1728 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1730 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1731 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1733 td = dbri->next_desc[td];
1734 dbri->pipes[pipe].desc = td;
1738 if (spin_is_locked(&dbri->lock)) {
1739 spin_unlock(&dbri->lock);
1740 snd_pcm_period_elapsed(info->substream);
1741 spin_lock(&dbri->lock);
1743 snd_pcm_period_elapsed(info->substream);
1746 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1748 struct dbri_streaminfo *info;
1749 int rd = dbri->pipes[pipe].desc;
1752 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1753 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1757 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1758 status = dbri->dma->desc[rd].word1;
1759 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1761 info = &dbri->stream_info[DBRI_REC];
1762 info->offset += DBRI_RD_CNT(status);
1764 /* FIXME: Check status */
1766 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1767 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1770 if (spin_is_locked(&dbri->lock)) {
1771 spin_unlock(&dbri->lock);
1772 snd_pcm_period_elapsed(info->substream);
1773 spin_lock(&dbri->lock);
1775 snd_pcm_period_elapsed(info->substream);
1778 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1780 int val = D_INTR_GETVAL(x);
1781 int channel = D_INTR_GETCHAN(x);
1782 int command = D_INTR_GETCMD(x);
1783 int code = D_INTR_GETCODE(x);
1785 int rval = D_INTR_GETRVAL(x);
1788 if (channel == D_INTR_CMD) {
1789 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1790 cmds[command], val);
1792 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1793 channel, code, rval);
1798 if (command != D_WAIT)
1799 printk(KERN_ERR "DBRI: Command read interrupt\n");
1802 reception_complete_intr(dbri, channel);
1806 transmission_complete_intr(dbri, channel);
1809 /* UNDR - Transmission underrun
1810 * resend SDP command with clear pipe bit (C) set
1813 /* FIXME: do something useful in case of underrun */
1814 printk(KERN_ERR "DBRI: Underrun error\n");
1818 int td = dbri->pipes[pipe].desc;
1820 dbri->dma->desc[td].word4 = 0;
1821 cmd = dbri_cmdlock(dbri, NoGetLock);
1822 *(cmd++) = DBRI_CMD(D_SDP, 0,
1823 dbri->pipes[pipe].sdp
1824 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1825 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1826 dbri_cmdsend(dbri, cmd);
1831 /* FXDT - Fixed data change */
1832 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1833 val = reverse_bytes(val, dbri->pipes[channel].length);
1835 if (dbri->pipes[channel].recv_fixed_ptr)
1836 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1839 if (channel != D_INTR_CMD)
1841 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1845 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1846 * buffer until it finds a zero word (indicating nothing more to do
1847 * right now). Non-zero words require processing and are handed off
1848 * to dbri_process_one_interrupt AFTER advancing the pointer.
1850 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1854 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1855 dbri->dma->intr[dbri->dbri_irqp] = 0;
1857 if (dbri->dbri_irqp == DBRI_INT_BLK)
1858 dbri->dbri_irqp = 1;
1860 dbri_process_one_interrupt(dbri, x);
1864 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1865 struct pt_regs *regs)
1867 struct snd_dbri *dbri = dev_id;
1868 static int errcnt = 0;
1873 spin_lock(&dbri->lock);
1876 * Read it, so the interrupt goes away.
1878 x = sbus_readl(dbri->regs + REG1);
1880 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1885 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1889 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1893 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1896 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1898 /* Some of these SBus errors cause the chip's SBus circuitry
1899 * to be disabled, so just re-enable and try to keep going.
1901 * The only one I've seen is MRR, which will be triggered
1902 * if you let a transmit pipe underrun, then try to CDP it.
1904 * If these things persist, we reset the chip.
1906 if ((++errcnt) % 10 == 0) {
1907 dprintk(D_INT, "Interrupt errors exceeded.\n");
1910 tmp = sbus_readl(dbri->regs + REG0);
1912 sbus_writel(tmp, dbri->regs + REG0);
1916 dbri_process_interrupt_buffer(dbri);
1918 spin_unlock(&dbri->lock);
1923 /****************************************************************************
1925 ****************************************************************************/
1926 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1927 .info = (SNDRV_PCM_INFO_MMAP |
1928 SNDRV_PCM_INFO_INTERLEAVED |
1929 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1930 SNDRV_PCM_INFO_MMAP_VALID),
1931 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1932 SNDRV_PCM_FMTBIT_A_LAW |
1933 SNDRV_PCM_FMTBIT_U8 |
1934 SNDRV_PCM_FMTBIT_S16_BE,
1935 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1940 .buffer_bytes_max = (64 * 1024),
1941 .period_bytes_min = 1,
1942 .period_bytes_max = DBRI_TD_MAXCNT,
1944 .periods_max = 1024,
1947 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1948 struct snd_pcm_hw_rule *rule)
1950 struct snd_interval *c = hw_param_interval(params,
1951 SNDRV_PCM_HW_PARAM_CHANNELS);
1952 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1953 struct snd_mask fmt;
1957 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
1958 return snd_mask_refine(f, &fmt);
1963 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
1964 struct snd_pcm_hw_rule *rule)
1966 struct snd_interval *c = hw_param_interval(params,
1967 SNDRV_PCM_HW_PARAM_CHANNELS);
1968 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1969 struct snd_interval ch;
1971 snd_interval_any(&ch);
1972 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
1973 ch.min = ch.max = 1;
1975 return snd_interval_refine(c, &ch);
1980 static int snd_dbri_open(struct snd_pcm_substream *substream)
1982 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1983 struct snd_pcm_runtime *runtime = substream->runtime;
1984 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1985 unsigned long flags;
1987 dprintk(D_USR, "open audio output.\n");
1988 runtime->hw = snd_dbri_pcm_hw;
1990 spin_lock_irqsave(&dbri->lock, flags);
1991 info->substream = substream;
1993 info->dvma_buffer = 0;
1995 spin_unlock_irqrestore(&dbri->lock, flags);
1997 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_CHANNELS,
1998 snd_hw_rule_format, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2000 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_FORMAT,
2001 snd_hw_rule_channels, 0,
2002 SNDRV_PCM_HW_PARAM_CHANNELS,
2010 static int snd_dbri_close(struct snd_pcm_substream *substream)
2012 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2013 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2015 dprintk(D_USR, "close audio output.\n");
2016 info->substream = NULL;
2022 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2023 struct snd_pcm_hw_params *hw_params)
2025 struct snd_pcm_runtime *runtime = substream->runtime;
2026 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2027 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2031 /* set sampling rate, audio format and number of channels */
2032 ret = cs4215_prepare(dbri, params_rate(hw_params),
2033 params_format(hw_params),
2034 params_channels(hw_params));
2038 if ((ret = snd_pcm_lib_malloc_pages(substream,
2039 params_buffer_bytes(hw_params))) < 0) {
2040 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2044 /* hw_params can get called multiple times. Only map the DMA once.
2046 if (info->dvma_buffer == 0) {
2047 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2048 direction = SBUS_DMA_TODEVICE;
2050 direction = SBUS_DMA_FROMDEVICE;
2052 info->dvma_buffer = sbus_map_single(dbri->sdev,
2054 params_buffer_bytes(hw_params),
2058 direction = params_buffer_bytes(hw_params);
2059 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2060 direction, info->dvma_buffer);
2064 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2066 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2067 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2070 dprintk(D_USR, "hw_free.\n");
2072 /* hw_free can get called multiple times. Only unmap the DMA once.
2074 if (info->dvma_buffer) {
2075 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2076 direction = SBUS_DMA_TODEVICE;
2078 direction = SBUS_DMA_FROMDEVICE;
2080 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2081 substream->runtime->buffer_size, direction);
2082 info->dvma_buffer = 0;
2084 if (info->pipe != -1) {
2085 reset_pipe(dbri, info->pipe);
2089 return snd_pcm_lib_free_pages(substream);
2092 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2094 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2095 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2096 struct snd_pcm_runtime *runtime = substream->runtime;
2099 info->size = snd_pcm_lib_buffer_bytes(substream);
2100 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2101 info->pipe = 4; /* Send pipe */
2103 info->pipe = 6; /* Receive pipe */
2105 spin_lock_irq(&dbri->lock);
2108 /* Setup the all the transmit/receive desciptors to cover the
2111 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2112 snd_pcm_lib_period_bytes(substream));
2114 spin_unlock_irq(&dbri->lock);
2116 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2120 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2122 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2123 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2127 case SNDRV_PCM_TRIGGER_START:
2128 dprintk(D_USR, "start audio, period is %d bytes\n",
2129 (int)snd_pcm_lib_period_bytes(substream));
2130 /* Re-submit the TDs. */
2133 case SNDRV_PCM_TRIGGER_STOP:
2134 dprintk(D_USR, "stop audio.\n");
2135 reset_pipe(dbri, info->pipe);
2144 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2146 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2147 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2148 snd_pcm_uframes_t ret;
2150 ret = bytes_to_frames(substream->runtime, info->offset)
2151 % substream->runtime->buffer_size;
2152 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2153 ret, substream->runtime->buffer_size);
2157 static struct snd_pcm_ops snd_dbri_ops = {
2158 .open = snd_dbri_open,
2159 .close = snd_dbri_close,
2160 .ioctl = snd_pcm_lib_ioctl,
2161 .hw_params = snd_dbri_hw_params,
2162 .hw_free = snd_dbri_hw_free,
2163 .prepare = snd_dbri_prepare,
2164 .trigger = snd_dbri_trigger,
2165 .pointer = snd_dbri_pointer,
2168 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2170 struct snd_pcm *pcm;
2173 if ((err = snd_pcm_new(dbri->card,
2174 /* ID */ "sun_dbri",
2176 /* playback count */ 1,
2177 /* capture count */ 1, &pcm)) < 0)
2179 snd_assert(pcm != NULL, return -EINVAL);
2181 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2182 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2184 pcm->private_data = dbri;
2185 pcm->info_flags = 0;
2186 strcpy(pcm->name, dbri->card->shortname);
2188 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2189 SNDRV_DMA_TYPE_CONTINUOUS,
2190 snd_dma_continuous_data(GFP_KERNEL),
2191 64 * 1024, 64 * 1024)) < 0) {
2198 /*****************************************************************************
2200 *****************************************************************************/
2202 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2203 struct snd_ctl_elem_info *uinfo)
2205 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2207 uinfo->value.integer.min = 0;
2208 if (kcontrol->private_value == DBRI_PLAY) {
2209 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2211 uinfo->value.integer.max = DBRI_MAX_GAIN;
2216 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2217 struct snd_ctl_elem_value *ucontrol)
2219 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2220 struct dbri_streaminfo *info;
2221 snd_assert(dbri != NULL, return -EINVAL);
2222 info = &dbri->stream_info[kcontrol->private_value];
2223 snd_assert(info != NULL, return -EINVAL);
2225 ucontrol->value.integer.value[0] = info->left_gain;
2226 ucontrol->value.integer.value[1] = info->right_gain;
2230 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2231 struct snd_ctl_elem_value *ucontrol)
2233 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2234 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2235 unsigned long flags;
2238 if (info->left_gain != ucontrol->value.integer.value[0]) {
2239 info->left_gain = ucontrol->value.integer.value[0];
2242 if (info->right_gain != ucontrol->value.integer.value[1]) {
2243 info->right_gain = ucontrol->value.integer.value[1];
2247 /* First mute outputs, and wait 1/8000 sec (125 us)
2248 * to make sure this takes. This avoids clicking noises.
2250 spin_lock_irqsave(&dbri->lock, flags);
2252 cs4215_setdata(dbri, 1);
2254 cs4215_setdata(dbri, 0);
2256 spin_unlock_irqrestore(&dbri->lock, flags);
2261 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_info *uinfo)
2264 int mask = (kcontrol->private_value >> 16) & 0xff;
2266 uinfo->type = (mask == 1) ?
2267 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2269 uinfo->value.integer.min = 0;
2270 uinfo->value.integer.max = mask;
2274 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2275 struct snd_ctl_elem_value *ucontrol)
2277 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2278 int elem = kcontrol->private_value & 0xff;
2279 int shift = (kcontrol->private_value >> 8) & 0xff;
2280 int mask = (kcontrol->private_value >> 16) & 0xff;
2281 int invert = (kcontrol->private_value >> 24) & 1;
2282 snd_assert(dbri != NULL, return -EINVAL);
2285 ucontrol->value.integer.value[0] =
2286 (dbri->mm.data[elem] >> shift) & mask;
2288 ucontrol->value.integer.value[0] =
2289 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2293 ucontrol->value.integer.value[0] =
2294 mask - ucontrol->value.integer.value[0];
2299 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2300 struct snd_ctl_elem_value *ucontrol)
2302 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2303 unsigned long flags;
2304 int elem = kcontrol->private_value & 0xff;
2305 int shift = (kcontrol->private_value >> 8) & 0xff;
2306 int mask = (kcontrol->private_value >> 16) & 0xff;
2307 int invert = (kcontrol->private_value >> 24) & 1;
2310 snd_assert(dbri != NULL, return -EINVAL);
2312 val = (ucontrol->value.integer.value[0] & mask);
2318 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2319 ~(mask << shift)) | val;
2320 changed = (val != dbri->mm.data[elem]);
2322 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2323 ~(mask << shift)) | val;
2324 changed = (val != dbri->mm.ctrl[elem - 4]);
2327 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2328 "mixer-value=%ld, mm-value=0x%x\n",
2329 mask, changed, ucontrol->value.integer.value[0],
2330 dbri->mm.data[elem & 3]);
2333 /* First mute outputs, and wait 1/8000 sec (125 us)
2334 * to make sure this takes. This avoids clicking noises.
2336 spin_lock_irqsave(&dbri->lock, flags);
2338 cs4215_setdata(dbri, 1);
2340 cs4215_setdata(dbri, 0);
2342 spin_unlock_irqrestore(&dbri->lock, flags);
2347 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2348 timeslots. Shift is the bit offset in the timeslot, mask defines the
2349 number of bits. invert is a boolean for use with attenuation.
2351 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2352 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2353 .info = snd_cs4215_info_single, \
2354 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2355 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2357 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2359 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2360 .name = "Playback Volume",
2361 .info = snd_cs4215_info_volume,
2362 .get = snd_cs4215_get_volume,
2363 .put = snd_cs4215_put_volume,
2364 .private_value = DBRI_PLAY,
2366 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2367 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2368 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2370 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2371 .name = "Capture Volume",
2372 .info = snd_cs4215_info_volume,
2373 .get = snd_cs4215_get_volume,
2374 .put = snd_cs4215_put_volume,
2375 .private_value = DBRI_REC,
2377 /* FIXME: mic/line switch */
2378 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2379 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2380 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2381 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2384 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2386 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2388 struct snd_card *card;
2391 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2394 strcpy(card->mixername, card->shortname);
2396 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2397 if ((err = snd_ctl_add(card,
2398 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2402 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2403 dbri->stream_info[idx].left_gain = 0;
2404 dbri->stream_info[idx].right_gain = 0;
2410 /****************************************************************************
2412 ****************************************************************************/
2413 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2415 struct snd_dbri *dbri = entry->private_data;
2417 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2418 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2419 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2420 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2424 static void dbri_debug_read(struct snd_info_entry * entry,
2425 struct snd_info_buffer *buffer)
2427 struct snd_dbri *dbri = entry->private_data;
2429 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2431 for (pipe = 0; pipe < 32; pipe++) {
2432 if (pipe_active(dbri, pipe)) {
2433 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2435 "Pipe %d: %s SDP=0x%x desc=%d, "
2438 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2439 pptr->sdp, pptr->desc,
2440 pptr->length, pptr->nextpipe);
2446 void snd_dbri_proc(struct snd_dbri * dbri)
2448 struct snd_info_entry *entry;
2450 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2451 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2454 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2455 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2456 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2462 ****************************************************************************
2463 **************************** Initialization ********************************
2464 ****************************************************************************
2466 static void snd_dbri_free(struct snd_dbri * dbri);
2468 static int __init snd_dbri_create(struct snd_card *card,
2469 struct sbus_dev *sdev,
2470 struct linux_prom_irqs *irq, int dev)
2472 struct snd_dbri *dbri = card->private_data;
2475 spin_lock_init(&dbri->lock);
2478 dbri->irq = irq->pri;
2480 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2482 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2484 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2485 dbri->dma, dbri->dma_dvma);
2487 /* Map the registers into memory. */
2488 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2489 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2490 dbri->regs_size, "DBRI Registers");
2492 printk(KERN_ERR "DBRI: could not allocate registers\n");
2493 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2494 (void *)dbri->dma, dbri->dma_dvma);
2498 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2499 "DBRI audio", dbri);
2501 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2502 sbus_iounmap(dbri->regs, dbri->regs_size);
2503 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2504 (void *)dbri->dma, dbri->dma_dvma);
2508 /* Do low level initialization of the DBRI and CS4215 chips */
2509 dbri_initialize(dbri);
2510 err = cs4215_init(dbri);
2512 snd_dbri_free(dbri);
2516 dbri->next = dbri_list;
2522 static void snd_dbri_free(struct snd_dbri * dbri)
2524 dprintk(D_GEN, "snd_dbri_free\n");
2528 free_irq(dbri->irq, dbri);
2531 sbus_iounmap(dbri->regs, dbri->regs_size);
2534 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2535 (void *)dbri->dma, dbri->dma_dvma);
2538 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2540 struct snd_dbri *dbri;
2541 struct linux_prom_irqs irq;
2542 struct resource *rp;
2543 struct snd_card *card;
2547 if (sdev->prom_name[9] < 'e') {
2548 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2549 sdev->prom_name[9]);
2553 if (dev >= SNDRV_CARDS)
2560 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2562 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2566 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2567 sizeof(struct snd_dbri));
2571 strcpy(card->driver, "DBRI");
2572 strcpy(card->shortname, "Sun DBRI");
2573 rp = &sdev->resource[0];
2574 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2576 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2578 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2579 snd_card_free(card);
2583 dbri = card->private_data;
2584 if ((err = snd_dbri_pcm(dbri)) < 0)
2587 if ((err = snd_dbri_mixer(dbri)) < 0)
2590 /* /proc file handling */
2591 snd_dbri_proc(dbri);
2593 if ((err = snd_card_register(card)) < 0)
2596 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2598 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2604 snd_dbri_free(dbri);
2605 snd_card_free(card);
2609 /* Probe for the dbri chip and then attach the driver. */
2610 static int __init dbri_init(void)
2612 struct sbus_bus *sbus;
2613 struct sbus_dev *sdev;
2616 /* Probe each SBUS for the DBRI chip(s). */
2617 for_all_sbusdev(sdev, sbus) {
2619 * The version is coded in the last character
2621 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2622 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2623 sdev->prom_name, sdev->slot);
2625 if (dbri_attach(sdev->prom_node, sdev) == 0)
2630 return (found > 0) ? 0 : -EIO;
2633 static void __exit dbri_exit(void)
2635 struct snd_dbri *this = dbri_list;
2637 while (this != NULL) {
2638 struct snd_dbri *next = this->next;
2639 struct snd_card *card = this->card;
2641 snd_dbri_free(this);
2642 snd_card_free(card);
2648 module_init(dbri_init);
2649 module_exit(dbri_exit);