2 * soc-cache.c -- ASoC register cache helpers
4 * Copyright 2009 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/i2c.h>
15 #include <linux/spi/spi.h>
16 #include <sound/soc.h>
18 static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
21 u16 *cache = codec->reg_cache;
22 if (reg >= codec->reg_cache_size)
27 static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
30 u16 *cache = codec->reg_cache;
34 BUG_ON(codec->volatile_register);
36 data[0] = (reg << 4) | ((value >> 8) & 0x000f);
37 data[1] = value & 0x00ff;
39 if (reg < codec->reg_cache_size)
42 if (codec->cache_only) {
43 codec->cache_sync = 1;
47 ret = codec->hw_write(codec->control_data, data, 2);
56 #if defined(CONFIG_SPI_MASTER)
57 static int snd_soc_4_12_spi_write(void *control_data, const char *data,
60 struct spi_device *spi = control_data;
61 struct spi_transfer t;
72 memset(&t, 0, (sizeof t));
77 spi_message_add_tail(&t, &m);
83 #define snd_soc_4_12_spi_write NULL
86 static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
89 u16 *cache = codec->reg_cache;
90 if (reg >= codec->reg_cache_size)
95 static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
98 u16 *cache = codec->reg_cache;
102 BUG_ON(codec->volatile_register);
104 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
105 data[1] = value & 0x00ff;
107 if (reg < codec->reg_cache_size)
110 if (codec->cache_only) {
111 codec->cache_sync = 1;
115 ret = codec->hw_write(codec->control_data, data, 2);
124 #if defined(CONFIG_SPI_MASTER)
125 static int snd_soc_7_9_spi_write(void *control_data, const char *data,
128 struct spi_device *spi = control_data;
129 struct spi_transfer t;
130 struct spi_message m;
139 spi_message_init(&m);
140 memset(&t, 0, (sizeof t));
145 spi_message_add_tail(&t, &m);
151 #define snd_soc_7_9_spi_write NULL
154 static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
157 u8 *cache = codec->reg_cache;
160 BUG_ON(codec->volatile_register);
164 data[1] = value & 0xff;
166 if (reg < codec->reg_cache_size)
169 if (codec->cache_only) {
170 codec->cache_sync = 1;
174 if (codec->hw_write(codec->control_data, data, 2) == 2)
180 static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
183 u8 *cache = codec->reg_cache;
185 if (reg >= codec->reg_cache_size)
190 static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
193 u16 *reg_cache = codec->reg_cache;
197 data[1] = (value >> 8) & 0xff;
198 data[2] = value & 0xff;
200 if (!snd_soc_codec_volatile_register(codec, reg))
201 reg_cache[reg] = value;
203 if (codec->cache_only) {
204 codec->cache_sync = 1;
208 if (codec->hw_write(codec->control_data, data, 3) == 3)
214 static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
217 u16 *cache = codec->reg_cache;
219 if (reg >= codec->reg_cache_size ||
220 snd_soc_codec_volatile_register(codec, reg)) {
221 if (codec->cache_only)
224 return codec->hw_read(codec, reg);
230 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
231 static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
234 struct i2c_msg xfer[2];
238 struct i2c_client *client = codec->control_data;
241 xfer[0].addr = client->addr;
247 xfer[1].addr = client->addr;
248 xfer[1].flags = I2C_M_RD;
252 ret = i2c_transfer(client->adapter, xfer, 2);
254 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
261 #define snd_soc_8_8_read_i2c NULL
264 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
265 static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
268 struct i2c_msg xfer[2];
272 struct i2c_client *client = codec->control_data;
275 xfer[0].addr = client->addr;
281 xfer[1].addr = client->addr;
282 xfer[1].flags = I2C_M_RD;
284 xfer[1].buf = (u8 *)&data;
286 ret = i2c_transfer(client->adapter, xfer, 2);
288 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
292 return (data >> 8) | ((data & 0xff) << 8);
295 #define snd_soc_8_16_read_i2c NULL
298 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
299 static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
302 struct i2c_msg xfer[2];
306 struct i2c_client *client = codec->control_data;
309 xfer[0].addr = client->addr;
312 xfer[0].buf = (u8 *)®
315 xfer[1].addr = client->addr;
316 xfer[1].flags = I2C_M_RD;
320 ret = i2c_transfer(client->adapter, xfer, 2);
322 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
329 #define snd_soc_16_8_read_i2c NULL
332 static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
335 u16 *cache = codec->reg_cache;
338 if (reg >= codec->reg_cache_size)
343 static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
346 u16 *cache = codec->reg_cache;
350 BUG_ON(codec->volatile_register);
352 data[0] = (reg >> 8) & 0xff;
353 data[1] = reg & 0xff;
357 if (reg < codec->reg_cache_size)
360 if (codec->cache_only) {
361 codec->cache_sync = 1;
365 ret = codec->hw_write(codec->control_data, data, 3);
374 #if defined(CONFIG_SPI_MASTER)
375 static int snd_soc_16_8_spi_write(void *control_data, const char *data,
378 struct spi_device *spi = control_data;
379 struct spi_transfer t;
380 struct spi_message m;
390 spi_message_init(&m);
391 memset(&t, 0, (sizeof t));
396 spi_message_add_tail(&t, &m);
402 #define snd_soc_16_8_spi_write NULL
405 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
406 static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
409 struct i2c_msg xfer[2];
410 u16 reg = cpu_to_be16(r);
413 struct i2c_client *client = codec->control_data;
416 xfer[0].addr = client->addr;
419 xfer[0].buf = (u8 *)®
422 xfer[1].addr = client->addr;
423 xfer[1].flags = I2C_M_RD;
425 xfer[1].buf = (u8 *)&data;
427 ret = i2c_transfer(client->adapter, xfer, 2);
429 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
433 return be16_to_cpu(data);
436 #define snd_soc_16_16_read_i2c NULL
439 static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
442 u16 *cache = codec->reg_cache;
444 if (reg >= codec->reg_cache_size ||
445 snd_soc_codec_volatile_register(codec, reg)) {
446 if (codec->cache_only)
449 return codec->hw_read(codec, reg);
455 static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
458 u16 *cache = codec->reg_cache;
462 data[0] = (reg >> 8) & 0xff;
463 data[1] = reg & 0xff;
464 data[2] = (value >> 8) & 0xff;
465 data[3] = value & 0xff;
467 if (reg < codec->reg_cache_size)
470 if (codec->cache_only) {
471 codec->cache_sync = 1;
475 ret = codec->hw_write(codec->control_data, data, 4);
487 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
488 int (*spi_write)(void *, const char *, int);
489 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
490 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
493 .addr_bits = 4, .data_bits = 12,
494 .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
495 .spi_write = snd_soc_4_12_spi_write,
498 .addr_bits = 7, .data_bits = 9,
499 .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
500 .spi_write = snd_soc_7_9_spi_write,
503 .addr_bits = 8, .data_bits = 8,
504 .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
505 .i2c_read = snd_soc_8_8_read_i2c,
508 .addr_bits = 8, .data_bits = 16,
509 .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
510 .i2c_read = snd_soc_8_16_read_i2c,
513 .addr_bits = 16, .data_bits = 8,
514 .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
515 .i2c_read = snd_soc_16_8_read_i2c,
516 .spi_write = snd_soc_16_8_spi_write,
519 .addr_bits = 16, .data_bits = 16,
520 .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
521 .i2c_read = snd_soc_16_16_read_i2c,
526 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
528 * @codec: CODEC to configure.
529 * @type: Type of cache.
530 * @addr_bits: Number of bits of register address data.
531 * @data_bits: Number of bits of data per register.
532 * @control: Control bus used.
534 * Register formats are frequently shared between many I2C and SPI
535 * devices. In order to promote code reuse the ASoC core provides
536 * some standard implementations of CODEC read and write operations
537 * which can be set up using this function.
539 * The caller is responsible for allocating and initialising the
542 * Note that at present this code cannot be used by CODECs with
543 * volatile registers.
545 int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
546 int addr_bits, int data_bits,
547 enum snd_soc_control_type control)
551 for (i = 0; i < ARRAY_SIZE(io_types); i++)
552 if (io_types[i].addr_bits == addr_bits &&
553 io_types[i].data_bits == data_bits)
555 if (i == ARRAY_SIZE(io_types)) {
557 "No I/O functions for %d bit address %d bit data\n",
558 addr_bits, data_bits);
562 codec->write = io_types[i].write;
563 codec->read = io_types[i].read;
570 #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
571 codec->hw_write = (hw_write_t)i2c_master_send;
573 if (io_types[i].i2c_read)
574 codec->hw_read = io_types[i].i2c_read;
578 if (io_types[i].spi_write)
579 codec->hw_write = io_types[i].spi_write;
585 EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);