2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
83 #define BP (1 << 4) /* Fix the signal of Biphase output */
84 #define SE (1 << 0) /* Fix the master clock */
87 #define B_CLK 0x00000010
88 #define A_CLK 0x00000001
90 /* IO SHIFT / MACRO */
95 #define AB_IO(param, shift) (param << shift)
98 #define PBSR (1 << 12) /* Port B Software Reset */
99 #define PASR (1 << 8) /* Port A Software Reset */
100 #define IR (1 << 4) /* Interrupt Reset */
101 #define FSISR (1 << 0) /* Software Reset */
104 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
105 /* 1: Biphase and serial */
108 #define FIFO_SZ_MASK 0x7
110 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
112 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115 * FSI driver use below type name for variable
117 * xxx_len : data length
118 * xxx_width : data width
119 * xxx_offset : data offset
120 * xxx_num : number of data
128 struct snd_pcm_substream *substream;
141 struct fsi_master *master;
143 struct fsi_stream playback;
144 struct fsi_stream capture;
162 struct fsi_priv fsia;
163 struct fsi_priv fsib;
164 struct fsi_core *core;
165 struct sh_fsi_platform_info *info;
170 * basic read write function
173 static void __fsi_reg_write(u32 reg, u32 data)
175 /* valid data area is 24bit */
178 __raw_writel(data, reg);
181 static u32 __fsi_reg_read(u32 reg)
183 return __raw_readl(reg);
186 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
188 u32 val = __fsi_reg_read(reg);
193 __fsi_reg_write(reg, val);
196 #define fsi_reg_write(p, r, d)\
197 __fsi_reg_write((u32)(p->base + REG_##r), d)
199 #define fsi_reg_read(p, r)\
200 __fsi_reg_read((u32)(p->base + REG_##r))
202 #define fsi_reg_mask_set(p, r, m, d)\
203 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
205 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
206 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
207 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
212 spin_lock_irqsave(&master->lock, flags);
213 ret = __fsi_reg_read((u32)(master->base + reg));
214 spin_unlock_irqrestore(&master->lock, flags);
219 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
220 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
221 static void _fsi_master_mask_set(struct fsi_master *master,
222 u32 reg, u32 mask, u32 data)
226 spin_lock_irqsave(&master->lock, flags);
227 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
228 spin_unlock_irqrestore(&master->lock, flags);
235 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
240 static int fsi_is_port_a(struct fsi_priv *fsi)
242 return fsi->master->base == fsi->base;
245 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
247 struct snd_soc_pcm_runtime *rtd = substream->private_data;
252 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
254 struct snd_soc_dai *dai = fsi_get_dai(substream);
255 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
258 return &master->fsia;
260 return &master->fsib;
263 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
265 int is_porta = fsi_is_port_a(fsi);
266 struct fsi_master *master = fsi_get_master(fsi);
268 return is_porta ? master->info->porta_flags :
269 master->info->portb_flags;
272 static inline int fsi_stream_is_play(int stream)
274 return stream == SNDRV_PCM_STREAM_PLAYBACK;
277 static inline int fsi_is_play(struct snd_pcm_substream *substream)
279 return fsi_stream_is_play(substream->stream);
282 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
285 return is_play ? &fsi->playback : &fsi->capture;
288 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
291 u32 flags = fsi_get_info_flags(fsi);
293 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
300 return (mode & flags) != mode;
303 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
305 int is_porta = fsi_is_port_a(fsi);
309 shift = is_play ? AO_SHIFT : AI_SHIFT;
311 shift = is_play ? BO_SHIFT : BI_SHIFT;
316 static void fsi_stream_push(struct fsi_priv *fsi,
318 struct snd_pcm_substream *substream,
322 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
324 io->substream = substream;
325 io->buff_len = buffer_len;
327 io->period_len = period_len;
331 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
333 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
335 io->substream = NULL;
342 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
345 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
349 fsi_reg_read(fsi, DOFF_ST) :
350 fsi_reg_read(fsi, DIFF_ST);
352 data_num = 0x1ff & (status >> 8);
353 data_num *= io->chan_num;
358 static int fsi_len2num(int len, int width)
363 #define fsi_num2offset(a, b) fsi_num2len(a, b)
364 static int fsi_num2len(int num, int width)
369 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
371 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
372 struct snd_pcm_substream *substream = io->substream;
373 struct snd_pcm_runtime *runtime = substream->runtime;
375 return frames_to_bytes(runtime, 1) / io->chan_num;
382 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
384 int is_play = fsi_stream_is_play(stream);
385 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
387 return io->substream->runtime->dma_area + io->buff_offset;
390 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
395 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
397 for (i = 0; i < num; i++)
398 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
401 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
406 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
409 for (i = 0; i < num; i++)
410 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
413 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
418 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
421 for (i = 0; i < num; i++)
422 fsi_reg_write(fsi, DODT, *(start + i));
425 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
430 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
432 for (i = 0; i < num; i++)
433 *(start + i) = fsi_reg_read(fsi, DIDT);
440 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
442 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
443 struct fsi_master *master = fsi_get_master(fsi);
445 fsi_core_mask_set(master, imsk, data, data);
446 fsi_core_mask_set(master, iemsk, data, data);
449 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
451 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
452 struct fsi_master *master = fsi_get_master(fsi);
454 fsi_core_mask_set(master, imsk, data, 0);
455 fsi_core_mask_set(master, iemsk, data, 0);
458 static u32 fsi_irq_get_status(struct fsi_master *master)
460 return fsi_core_read(master, int_st);
463 static void fsi_irq_clear_status(struct fsi_priv *fsi)
466 struct fsi_master *master = fsi_get_master(fsi);
468 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
469 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
471 /* clear interrupt factor */
472 fsi_core_mask_set(master, int_st, data, 0);
476 * SPDIF master clock function
478 * These functions are used later FSI2
480 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
482 struct fsi_master *master = fsi_get_master(fsi);
485 if (master->core->ver < 2) {
486 pr_err("fsi: register access err (%s)\n", __func__);
491 val = enable ? mask : 0;
494 fsi_core_mask_set(master, a_mclk, mask, val) :
495 fsi_core_mask_set(master, b_mclk, mask, val);
502 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
504 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
505 struct fsi_master *master = fsi_get_master(fsi);
508 fsi_master_mask_set(master, CLK_RST, val, val);
510 fsi_master_mask_set(master, CLK_RST, val, 0);
513 static void fsi_fifo_init(struct fsi_priv *fsi,
515 struct snd_soc_dai *dai)
517 struct fsi_master *master = fsi_get_master(fsi);
518 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
521 /* get on-chip RAM capacity */
522 shift = fsi_master_read(master, FIFO_SZ);
523 shift >>= fsi_get_port_shift(fsi, is_play);
524 shift &= FIFO_SZ_MASK;
525 io->fifo_max_num = 256 << shift;
526 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
529 * The maximum number of sample data varies depending
530 * on the number of channels selected for the format.
532 * FIFOs are used in 4-channel units in 3-channel mode
533 * and in 8-channel units in 5- to 7-channel mode
534 * meaning that more FIFOs than the required size of DPRAM
537 * ex) if 256 words of DP-RAM is connected
538 * 1 channel: 256 (256 x 1 = 256)
539 * 2 channels: 128 (128 x 2 = 256)
540 * 3 channels: 64 ( 64 x 3 = 192)
541 * 4 channels: 64 ( 64 x 4 = 256)
542 * 5 channels: 32 ( 32 x 5 = 160)
543 * 6 channels: 32 ( 32 x 6 = 192)
544 * 7 channels: 32 ( 32 x 7 = 224)
545 * 8 channels: 32 ( 32 x 8 = 256)
547 for (i = 1; i < io->chan_num; i <<= 1)
548 io->fifo_max_num >>= 1;
549 dev_dbg(dai->dev, "%d channel %d store\n",
550 io->chan_num, io->fifo_max_num);
553 * set interrupt generation factor
557 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
558 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
560 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
561 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
565 static void fsi_soft_all_reset(struct fsi_master *master)
568 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
572 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
573 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
577 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
579 struct snd_pcm_runtime *runtime;
580 struct snd_pcm_substream *substream = NULL;
581 int is_play = fsi_stream_is_play(stream);
582 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
583 int data_residue_num;
588 void (*fn)(struct fsi_priv *fsi, int size);
592 !io->substream->runtime)
596 substream = io->substream;
597 runtime = substream->runtime;
599 /* FSI FIFO has limit.
600 * So, this driver can not send periods data at a time
602 if (io->buff_offset >=
603 fsi_num2offset(io->period_num + 1, io->period_len)) {
606 io->period_num = (io->period_num + 1) % runtime->periods;
608 if (0 == io->period_num)
612 /* get 1 channel data width */
613 ch_width = fsi_get_frame_width(fsi, is_play);
615 /* get residue data number of alsa */
616 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
623 * data_num_max : number of FSI fifo free space
624 * data_num : number of ALSA residue data
626 data_num_max = io->fifo_max_num * io->chan_num;
627 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
629 data_num = data_residue_num;
633 fn = fsi_dma_soft_push16;
636 fn = fsi_dma_soft_push32;
645 * data_num_max : number of ALSA free space
646 * data_num : number of data in FSI fifo
648 data_num_max = data_residue_num;
649 data_num = fsi_get_fifo_data_num(fsi, is_play);
653 fn = fsi_dma_soft_pop16;
656 fn = fsi_dma_soft_pop32;
663 data_num = min(data_num, data_num_max);
667 /* update buff_offset */
668 io->buff_offset += fsi_num2offset(data_num, ch_width);
670 /* check fifo status */
672 struct snd_soc_dai *dai = fsi_get_dai(substream);
673 u32 status = is_play ?
674 fsi_reg_read(fsi, DOFF_ST) :
675 fsi_reg_read(fsi, DIFF_ST);
677 if (status & ERR_OVER)
678 dev_err(dai->dev, "over run\n");
679 if (status & ERR_UNDER)
680 dev_err(dai->dev, "under run\n");
684 fsi_reg_write(fsi, DOFF_ST, 0) :
685 fsi_reg_write(fsi, DIFF_ST, 0);
688 snd_pcm_period_elapsed(substream);
693 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
695 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE);
698 static int fsi_data_push(struct fsi_priv *fsi, int startup)
700 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK);
703 static irqreturn_t fsi_interrupt(int irq, void *data)
705 struct fsi_master *master = data;
706 u32 int_st = fsi_irq_get_status(master);
708 /* clear irq status */
709 fsi_master_mask_set(master, SOFT_RST, IR, 0);
710 fsi_master_mask_set(master, SOFT_RST, IR, IR);
712 if (int_st & AB_IO(1, AO_SHIFT))
713 fsi_data_push(&master->fsia, 0);
714 if (int_st & AB_IO(1, BO_SHIFT))
715 fsi_data_push(&master->fsib, 0);
716 if (int_st & AB_IO(1, AI_SHIFT))
717 fsi_data_pop(&master->fsia, 0);
718 if (int_st & AB_IO(1, BI_SHIFT))
719 fsi_data_pop(&master->fsib, 0);
721 fsi_irq_clear_status(&master->fsia);
722 fsi_irq_clear_status(&master->fsib);
731 static int fsi_dai_startup(struct snd_pcm_substream *substream,
732 struct snd_soc_dai *dai)
734 struct fsi_priv *fsi = fsi_get_priv(substream);
735 struct fsi_master *master = fsi_get_master(fsi);
736 struct fsi_stream *io;
737 u32 flags = fsi_get_info_flags(fsi);
740 int is_play = fsi_is_play(substream);
743 io = fsi_get_stream(fsi, is_play);
745 pm_runtime_get_sync(dai->dev);
748 data = is_play ? (1 << 0) : (1 << 4);
749 is_master = fsi_is_master_mode(fsi, is_play);
751 fsi_reg_mask_set(fsi, CKG1, data, data);
753 fsi_reg_mask_set(fsi, CKG1, data, 0);
755 /* clock inversion (CKG2) */
757 if (SH_FSI_LRM_INV & flags)
759 if (SH_FSI_BRM_INV & flags)
761 if (SH_FSI_LRS_INV & flags)
763 if (SH_FSI_BRS_INV & flags)
766 fsi_reg_write(fsi, CKG2, data);
770 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
772 case SH_FSI_FMT_MONO:
776 case SH_FSI_FMT_MONO_DELAY:
789 io->chan_num = is_play ?
790 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
791 data = CR_TDM | (io->chan_num - 1);
793 case SH_FSI_FMT_TDM_DELAY:
794 io->chan_num = is_play ?
795 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
796 data = CR_TDM_D | (io->chan_num - 1);
798 case SH_FSI_FMT_SPDIF:
799 if (master->core->ver < 2) {
800 dev_err(dai->dev, "This FSI can not use SPDIF\n");
803 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
805 fsi_spdif_clk_ctrl(fsi, 1);
806 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
809 dev_err(dai->dev, "unknown format.\n");
813 fsi_reg_write(fsi, DO_FMT, data) :
814 fsi_reg_write(fsi, DI_FMT, data);
817 fsi_irq_disable(fsi, is_play);
818 fsi_irq_clear_status(fsi);
821 fsi_fifo_init(fsi, is_play, dai);
826 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
827 struct snd_soc_dai *dai)
829 struct fsi_priv *fsi = fsi_get_priv(substream);
830 int is_play = fsi_is_play(substream);
831 struct fsi_master *master = fsi_get_master(fsi);
832 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
834 fsi_irq_disable(fsi, is_play);
835 fsi_clk_ctrl(fsi, 0);
837 set_rate = master->info->set_rate;
838 if (set_rate && fsi->rate)
839 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
842 pm_runtime_put_sync(dai->dev);
845 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
846 struct snd_soc_dai *dai)
848 struct fsi_priv *fsi = fsi_get_priv(substream);
849 struct snd_pcm_runtime *runtime = substream->runtime;
850 int is_play = fsi_is_play(substream);
854 case SNDRV_PCM_TRIGGER_START:
855 fsi_stream_push(fsi, is_play, substream,
856 frames_to_bytes(runtime, runtime->buffer_size),
857 frames_to_bytes(runtime, runtime->period_size));
858 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
859 fsi_irq_enable(fsi, is_play);
861 case SNDRV_PCM_TRIGGER_STOP:
862 fsi_irq_disable(fsi, is_play);
863 fsi_stream_pop(fsi, is_play);
870 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
871 struct snd_pcm_hw_params *params,
872 struct snd_soc_dai *dai)
874 struct fsi_priv *fsi = fsi_get_priv(substream);
875 struct fsi_master *master = fsi_get_master(fsi);
876 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
877 int fsi_ver = master->core->ver;
878 long rate = params_rate(params);
881 set_rate = master->info->set_rate;
885 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
886 if (ret < 0) /* error */
893 switch (ret & SH_FSI_ACKMD_MASK) {
896 case SH_FSI_ACKMD_512:
899 case SH_FSI_ACKMD_256:
902 case SH_FSI_ACKMD_128:
905 case SH_FSI_ACKMD_64:
908 case SH_FSI_ACKMD_32:
910 dev_err(dai->dev, "unsupported ACKMD\n");
916 switch (ret & SH_FSI_BPFMD_MASK) {
919 case SH_FSI_BPFMD_32:
922 case SH_FSI_BPFMD_64:
925 case SH_FSI_BPFMD_128:
928 case SH_FSI_BPFMD_256:
931 case SH_FSI_BPFMD_512:
934 case SH_FSI_BPFMD_16:
936 dev_err(dai->dev, "unsupported ACKMD\n");
942 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
944 fsi_clk_ctrl(fsi, 1);
952 static struct snd_soc_dai_ops fsi_dai_ops = {
953 .startup = fsi_dai_startup,
954 .shutdown = fsi_dai_shutdown,
955 .trigger = fsi_dai_trigger,
956 .hw_params = fsi_dai_hw_params,
963 static struct snd_pcm_hardware fsi_pcm_hardware = {
964 .info = SNDRV_PCM_INFO_INTERLEAVED |
965 SNDRV_PCM_INFO_MMAP |
966 SNDRV_PCM_INFO_MMAP_VALID |
967 SNDRV_PCM_INFO_PAUSE,
974 .buffer_bytes_max = 64 * 1024,
975 .period_bytes_min = 32,
976 .period_bytes_max = 8192,
982 static int fsi_pcm_open(struct snd_pcm_substream *substream)
984 struct snd_pcm_runtime *runtime = substream->runtime;
987 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
989 ret = snd_pcm_hw_constraint_integer(runtime,
990 SNDRV_PCM_HW_PARAM_PERIODS);
995 static int fsi_hw_params(struct snd_pcm_substream *substream,
996 struct snd_pcm_hw_params *hw_params)
998 return snd_pcm_lib_malloc_pages(substream,
999 params_buffer_bytes(hw_params));
1002 static int fsi_hw_free(struct snd_pcm_substream *substream)
1004 return snd_pcm_lib_free_pages(substream);
1007 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1009 struct snd_pcm_runtime *runtime = substream->runtime;
1010 struct fsi_priv *fsi = fsi_get_priv(substream);
1011 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1014 location = (io->buff_offset - 1);
1018 return bytes_to_frames(runtime, location);
1021 static struct snd_pcm_ops fsi_pcm_ops = {
1022 .open = fsi_pcm_open,
1023 .ioctl = snd_pcm_lib_ioctl,
1024 .hw_params = fsi_hw_params,
1025 .hw_free = fsi_hw_free,
1026 .pointer = fsi_pointer,
1033 #define PREALLOC_BUFFER (32 * 1024)
1034 #define PREALLOC_BUFFER_MAX (32 * 1024)
1036 static void fsi_pcm_free(struct snd_pcm *pcm)
1038 snd_pcm_lib_preallocate_free_for_all(pcm);
1041 static int fsi_pcm_new(struct snd_card *card,
1042 struct snd_soc_dai *dai,
1043 struct snd_pcm *pcm)
1046 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1047 * in MMAP mode (i.e. aplay -M)
1049 return snd_pcm_lib_preallocate_pages_for_all(
1051 SNDRV_DMA_TYPE_CONTINUOUS,
1052 snd_dma_continuous_data(GFP_KERNEL),
1053 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1060 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1065 .formats = FSI_FMTS,
1071 .formats = FSI_FMTS,
1075 .ops = &fsi_dai_ops,
1081 .formats = FSI_FMTS,
1087 .formats = FSI_FMTS,
1091 .ops = &fsi_dai_ops,
1095 static struct snd_soc_platform_driver fsi_soc_platform = {
1096 .ops = &fsi_pcm_ops,
1097 .pcm_new = fsi_pcm_new,
1098 .pcm_free = fsi_pcm_free,
1105 static int fsi_probe(struct platform_device *pdev)
1107 struct fsi_master *master;
1108 const struct platform_device_id *id_entry;
1109 struct resource *res;
1113 id_entry = pdev->id_entry;
1115 dev_err(&pdev->dev, "unknown fsi device\n");
1119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 irq = platform_get_irq(pdev, 0);
1121 if (!res || (int)irq <= 0) {
1122 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1127 master = kzalloc(sizeof(*master), GFP_KERNEL);
1129 dev_err(&pdev->dev, "Could not allocate master\n");
1134 master->base = ioremap_nocache(res->start, resource_size(res));
1135 if (!master->base) {
1137 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1141 /* master setting */
1143 master->info = pdev->dev.platform_data;
1144 master->core = (struct fsi_core *)id_entry->driver_data;
1145 spin_lock_init(&master->lock);
1148 master->fsia.base = master->base;
1149 master->fsia.master = master;
1152 master->fsib.base = master->base + 0x40;
1153 master->fsib.master = master;
1155 pm_runtime_enable(&pdev->dev);
1156 pm_runtime_resume(&pdev->dev);
1157 dev_set_drvdata(&pdev->dev, master);
1159 fsi_soft_all_reset(master);
1161 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1162 id_entry->name, master);
1164 dev_err(&pdev->dev, "irq request err\n");
1168 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1170 dev_err(&pdev->dev, "cannot snd soc register\n");
1174 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1177 free_irq(irq, master);
1179 iounmap(master->base);
1180 pm_runtime_disable(&pdev->dev);
1188 static int fsi_remove(struct platform_device *pdev)
1190 struct fsi_master *master;
1192 master = dev_get_drvdata(&pdev->dev);
1194 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1195 snd_soc_unregister_platform(&pdev->dev);
1197 pm_runtime_disable(&pdev->dev);
1199 free_irq(master->irq, master);
1201 iounmap(master->base);
1207 static int fsi_runtime_nop(struct device *dev)
1209 /* Runtime PM callback shared between ->runtime_suspend()
1210 * and ->runtime_resume(). Simply returns success.
1212 * This driver re-initializes all registers after
1213 * pm_runtime_get_sync() anyway so there is no need
1214 * to save and restore registers here.
1219 static struct dev_pm_ops fsi_pm_ops = {
1220 .runtime_suspend = fsi_runtime_nop,
1221 .runtime_resume = fsi_runtime_nop,
1224 static struct fsi_core fsi1_core = {
1233 static struct fsi_core fsi2_core = {
1237 .int_st = CPU_INT_ST,
1240 .a_mclk = A_MST_CTLR,
1241 .b_mclk = B_MST_CTLR,
1244 static struct platform_device_id fsi_id_table[] = {
1245 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1246 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1249 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1251 static struct platform_driver fsi_driver = {
1253 .name = "fsi-pcm-audio",
1257 .remove = fsi_remove,
1258 .id_table = fsi_id_table,
1261 static int __init fsi_mobile_init(void)
1263 return platform_driver_register(&fsi_driver);
1266 static void __exit fsi_mobile_exit(void)
1268 platform_driver_unregister(&fsi_driver);
1271 module_init(fsi_mobile_init);
1272 module_exit(fsi_mobile_exit);
1274 MODULE_LICENSE("GPL");
1275 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1276 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");