sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/initval.h>
  31 #include <sound/soc.h>
  32
  33 #include <mach/control.h>
  34 #include <mach/dma.h>
  35 #include <mach/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  40
  41 struct omap_mcbsp_data {
  42         unsigned int                    bus_id;
  43         struct omap_mcbsp_reg_cfg       regs;
  44         unsigned int                    fmt;
  45         /*
  46          * Flags indicating is the bus already activated and configured by
  47          * another substream
  48          */
  49         int                             active;
  50         int                             configured;
  51 };
  52
  53 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  54
  55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  56
  57 /*
  58  * Stream DMA parameters. DMA request line and port address are set runtime
  59  * since they are different between OMAP1 and later OMAPs
  60  */
  61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  62
  63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  64 static const int omap1_dma_reqs[][2] = {
  65         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  66         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  67         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  68 };
  69 static const unsigned long omap1_mcbsp_port[][2] = {
  70         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  71           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  72         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  73           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  74         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  75           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  76 };
  77 #else
  78 static const int omap1_dma_reqs[][2] = {};
  79 static const unsigned long omap1_mcbsp_port[][2] = {};
  80 #endif
  81
  82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  83 static const int omap24xx_dma_reqs[][2] = {
  84         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  85         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  87         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  88         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  89         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  90 #endif
  91 };
  92 #else
  93 static const int omap24xx_dma_reqs[][2] = {};
  94 #endif
  95
  96 #if defined(CONFIG_ARCH_OMAP2420)
  97 static const unsigned long omap2420_mcbsp_port[][2] = {
  98         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  99           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 100         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 101           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 102 };
 103 #else
 104 static const unsigned long omap2420_mcbsp_port[][2] = {};
 105 #endif
 106
 107 #if defined(CONFIG_ARCH_OMAP2430)
 108 static const unsigned long omap2430_mcbsp_port[][2] = {
 109         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 110           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 111         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 112           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 113         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 114           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 115         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 116           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 117         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 118           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 119 };
 120 #else
 121 static const unsigned long omap2430_mcbsp_port[][2] = {};
 122 #endif
 123
 124 #if defined(CONFIG_ARCH_OMAP34XX)
 125 static const unsigned long omap34xx_mcbsp_port[][2] = {
 126         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 127           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 128         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 129           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 130         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 131           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 132         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 133           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 134         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 135           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 136 };
 137 #else
 138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 139 #endif
 140
 141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
 142 {
 143         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 144         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 145         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 146         int err = 0;
 147
 148         if (!cpu_dai->active)
 149                 err = omap_mcbsp_request(mcbsp_data->bus_id);
 150
 151         return err;
 152 }
 153
 154 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
 155 {
 156         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 157         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 158         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 159
 160         if (!cpu_dai->active) {
 161                 omap_mcbsp_free(mcbsp_data->bus_id);
 162                 mcbsp_data->configured = 0;
 163         }
 164 }
 165
 166 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
 167 {
 168         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 169         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 170         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 171         int err = 0;
 172
 173         switch (cmd) {
 174         case SNDRV_PCM_TRIGGER_START:
 175         case SNDRV_PCM_TRIGGER_RESUME:
 176         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 177                 if (!mcbsp_data->active++)
 178                         omap_mcbsp_start(mcbsp_data->bus_id);
 179                 break;
 180
 181         case SNDRV_PCM_TRIGGER_STOP:
 182         case SNDRV_PCM_TRIGGER_SUSPEND:
 183         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 184                 if (!--mcbsp_data->active)
 185                         omap_mcbsp_stop(mcbsp_data->bus_id);
 186                 break;
 187         default:
 188                 err = -EINVAL;
 189         }
 190
 191         return err;
 192 }
 193
 194 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 195                                     struct snd_pcm_hw_params *params)
 196 {
 197         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 198         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 199         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 200         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 201         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 202         int wlen, channels;
 203         unsigned long port;
 204
 205         if (cpu_class_is_omap1()) {
 206                 dma = omap1_dma_reqs[bus_id][substream->stream];
 207                 port = omap1_mcbsp_port[bus_id][substream->stream];
 208         } else if (cpu_is_omap2420()) {
 209                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 210                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 211         } else if (cpu_is_omap2430()) {
 212                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 213                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 214         } else if (cpu_is_omap343x()) {
 215                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 216                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 217         } else {
 218                 return -ENODEV;
 219         }
 220         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 221                 substream->stream ? "Audio Capture" : "Audio Playback";
 222         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 223         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 224         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 225
 226         if (mcbsp_data->configured) {
 227                 /* McBSP already configured by another stream */
 228                 return 0;
 229         }
 230
 231         channels = params_channels(params);
 232         switch (channels) {
 233         case 2:
 234                 /* Use dual-phase frames */
 235                 regs->rcr2      |= RPHASE;
 236                 regs->xcr2      |= XPHASE;
 237         case 1:
 238                 /* Set 1 word per (McBSP) frame */
 239                 regs->rcr2      |= RFRLEN2(1 - 1);
 240                 regs->rcr1      |= RFRLEN1(1 - 1);
 241                 regs->xcr2      |= XFRLEN2(1 - 1);
 242                 regs->xcr1      |= XFRLEN1(1 - 1);
 243                 break;
 244         default:
 245                 /* Unsupported number of channels */
 246                 return -EINVAL;
 247         }
 248
 249         switch (params_format(params)) {
 250         case SNDRV_PCM_FORMAT_S16_LE:
 251                 /* Set word lengths */
 252                 wlen = 16;
 253                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 254                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 255                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 256                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 257                 break;
 258         default:
 259                 /* Unsupported PCM format */
 260                 return -EINVAL;
 261         }
 262
 263         /* Set FS period and length in terms of bit clock periods */
 264         switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 265         case SND_SOC_DAIFMT_I2S:
 266                 regs->srgr2     |= FPER(wlen * 2 - 1);
 267                 regs->srgr1     |= FWID(wlen - 1);
 268                 break;
 269         case SND_SOC_DAIFMT_DSP_A:
 270                 regs->srgr2     |= FPER(wlen * channels - 1);
 271                 regs->srgr1     |= FWID(wlen * channels - 2);
 272                 break;
 273         }
 274
 275         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 276         mcbsp_data->configured = 1;
 277
 278         return 0;
 279 }
 280
 281 /*
 282  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 283  * cache is initialized here
 284  */
 285 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 286                                       unsigned int fmt)
 287 {
 288         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 289         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 290
 291         if (mcbsp_data->configured)
 292                 return 0;
 293
 294         mcbsp_data->fmt = fmt;
 295         memset(regs, 0, sizeof(*regs));
 296         /* Generic McBSP register settings */
 297         regs->spcr2     |= XINTM(3) | FREE;
 298         regs->spcr1     |= RINTM(3);
 299         regs->rcr2      |= RFIG;
 300         regs->xcr2      |= XFIG;
 301
 302         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 303         case SND_SOC_DAIFMT_I2S:
 304                 /* 0-bit data delay */
 305                 regs->rcr2      |= RDATDLY(0);
 306                 regs->xcr2      |= XDATDLY(0);
 307                 break;
 308         default:
 309                 /* Unsupported data format */
 310                 return -EINVAL;
 311         }
 312
 313         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 314         case SND_SOC_DAIFMT_CBS_CFS:
 315                 /* McBSP master. Set FS and bit clocks as outputs */
 316                 regs->pcr0      |= FSXM | FSRM |
 317                                    CLKXM | CLKRM;
 318                 /* Sample rate generator drives the FS */
 319                 regs->srgr2     |= FSGM;
 320                 break;
 321         case SND_SOC_DAIFMT_CBM_CFM:
 322                 /* McBSP slave */
 323                 break;
 324         default:
 325                 /* Unsupported master/slave configuration */
 326                 return -EINVAL;
 327         }
 328
 329         /* Set bit clock (CLKX/CLKR) and FS polarities */
 330         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 331         case SND_SOC_DAIFMT_NB_NF:
 332                 /*
 333                  * Normal BCLK + FS.
 334                  * FS active low. TX data driven on falling edge of bit clock
 335                  * and RX data sampled on rising edge of bit clock.
 336                  */
 337                 regs->pcr0      |= FSXP | FSRP |
 338                                    CLKXP | CLKRP;
 339                 break;
 340         case SND_SOC_DAIFMT_NB_IF:
 341                 regs->pcr0      |= CLKXP | CLKRP;
 342                 break;
 343         case SND_SOC_DAIFMT_IB_NF:
 344                 regs->pcr0      |= FSXP | FSRP;
 345                 break;
 346         case SND_SOC_DAIFMT_IB_IF:
 347                 break;
 348         default:
 349                 return -EINVAL;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 356                                      int div_id, int div)
 357 {
 358         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 359         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 360
 361         if (div_id != OMAP_MCBSP_CLKGDV)
 362                 return -ENODEV;
 363
 364         regs->srgr1     |= CLKGDV(div - 1);
 365
 366         return 0;
 367 }
 368
 369 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 370                                        int clk_id)
 371 {
 372         int sel_bit;
 373         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 374
 375         if (cpu_class_is_omap1()) {
 376                 /* OMAP1's can use only external source clock */
 377                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 378                         return -EINVAL;
 379                 else
 380                         return 0;
 381         }
 382
 383         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 384                 return -EINVAL;
 385
 386         if (cpu_is_omap343x())
 387                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 388
 389         switch (mcbsp_data->bus_id) {
 390         case 0:
 391                 reg = OMAP2_CONTROL_DEVCONF0;
 392                 sel_bit = 2;
 393                 break;
 394         case 1:
 395                 reg = OMAP2_CONTROL_DEVCONF0;
 396                 sel_bit = 6;
 397                 break;
 398         case 2:
 399                 reg = reg_devconf1;
 400                 sel_bit = 0;
 401                 break;
 402         case 3:
 403                 reg = reg_devconf1;
 404                 sel_bit = 2;
 405                 break;
 406         case 4:
 407                 reg = reg_devconf1;
 408                 sel_bit = 4;
 409                 break;
 410         default:
 411                 return -EINVAL;
 412         }
 413
 414         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 415                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 416         else
 417                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 418
 419         return 0;
 420 }
 421
 422 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 423                                          int clk_id, unsigned int freq,
 424                                          int dir)
 425 {
 426         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 427         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 428         int err = 0;
 429
 430         switch (clk_id) {
 431         case OMAP_MCBSP_SYSCLK_CLK:
 432                 regs->srgr2     |= CLKSM;
 433                 break;
 434         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 435         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 436                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 437                 break;
 438
 439         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 440                 regs->srgr2     |= CLKSM;
 441         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 442                 regs->pcr0      |= SCLKME;
 443                 break;
 444         default:
 445                 err = -ENODEV;
 446         }
 447
 448         return err;
 449 }
 450
 451 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 452 {                                                               \
 453         .name = "omap-mcbsp-dai-"#link_id,                      \
 454         .id = (link_id),                                        \
 455         .type = SND_SOC_DAI_I2S,                                \
 456         .playback = {                                           \
 457                 .channels_min = 1,                              \
 458                 .channels_max = 2,                              \
 459                 .rates = OMAP_MCBSP_RATES,                      \
 460                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 461         },                                                      \
 462         .capture = {                                            \
 463                 .channels_min = 1,                              \
 464                 .channels_max = 2,                              \
 465                 .rates = OMAP_MCBSP_RATES,                      \
 466                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 467         },                                                      \
 468         .ops = {                                                \
 469                 .startup = omap_mcbsp_dai_startup,              \
 470                 .shutdown = omap_mcbsp_dai_shutdown,            \
 471                 .trigger = omap_mcbsp_dai_trigger,              \
 472                 .hw_params = omap_mcbsp_dai_hw_params,          \
 473         },                                                      \
 474         .dai_ops = {                                            \
 475                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,          \
 476                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,        \
 477                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,    \
 478         },                                                      \
 479         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 480 }
 481
 482 struct snd_soc_dai omap_mcbsp_dai[] = {
 483         OMAP_MCBSP_DAI_BUILDER(0),
 484         OMAP_MCBSP_DAI_BUILDER(1),
 485 #if NUM_LINKS >= 3
 486         OMAP_MCBSP_DAI_BUILDER(2),
 487 #endif
 488 #if NUM_LINKS == 5
 489         OMAP_MCBSP_DAI_BUILDER(3),
 490         OMAP_MCBSP_DAI_BUILDER(4),
 491 #endif
 492 };
 493
 494 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 495
 496 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
 497 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 498 MODULE_LICENSE("GPL");