2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
31 #include <asm/mach-types.h>
32 #include <mach/hardware.h>
37 static struct mxs_saif *mxs_saif[2];
39 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
40 int clk_id, unsigned int freq, int dir)
42 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
55 * Set SAIF clock and MCLK
57 static int mxs_saif_set_clk(struct mxs_saif *saif,
64 scr = __raw_readl(saif->base + SAIF_CTRL);
65 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
66 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
71 * The SAIF clock should be either 384*fs or 512*fs.
72 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
73 * For 32x mclk, set saif clk as 512*fs.
74 * For 48x mclk, set saif clk as 384*fs.
76 * If MCLK is not used, we just set saif clk to 512*fs.
78 if (saif->mclk_in_use) {
80 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
81 ret = clk_set_rate(saif->clk, 512 * rate);
82 } else if (mclk % 48 == 0) {
83 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
84 ret = clk_set_rate(saif->clk, 384 * rate);
86 /* SAIF MCLK should be either 32x or 48x */
90 ret = clk_set_rate(saif->clk, 512 * rate);
91 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
97 if (!saif->mclk_in_use) {
98 __raw_writel(scr, saif->base + SAIF_CTRL);
103 * Program the over-sample rate for MCLK output
105 * The available MCLK range is 32x, 48x... 512x. The rate
106 * could be from 8kHz to 192kH.
108 switch (mclk / rate) {
110 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
113 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
116 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
119 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
122 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
125 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
128 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
131 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
134 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
140 __raw_writel(scr, saif->base + SAIF_CTRL);
146 * Put and disable MCLK.
148 int mxs_saif_put_mclk(unsigned int saif_id)
150 struct mxs_saif *saif = mxs_saif[saif_id];
156 stat = __raw_readl(saif->base + SAIF_STAT);
157 if (stat & BM_SAIF_STAT_BUSY) {
158 dev_err(saif->dev, "error: busy\n");
162 clk_disable(saif->clk);
164 /* disable MCLK output */
165 __raw_writel(BM_SAIF_CTRL_CLKGATE,
166 saif->base + SAIF_CTRL + MXS_SET_ADDR);
167 __raw_writel(BM_SAIF_CTRL_RUN,
168 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
170 saif->mclk_in_use = 0;
175 * Get MCLK and set clock rate, then enable it
177 * This interface is used for codecs who are using MCLK provided
180 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
183 struct mxs_saif *saif = mxs_saif[saif_id];
191 __raw_writel(BM_SAIF_CTRL_SFTRST,
192 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
194 /* FIXME: need clear clk gate for register r/w */
195 __raw_writel(BM_SAIF_CTRL_CLKGATE,
196 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
198 stat = __raw_readl(saif->base + SAIF_STAT);
199 if (stat & BM_SAIF_STAT_BUSY) {
200 dev_err(saif->dev, "error: busy\n");
204 saif->mclk_in_use = 1;
205 ret = mxs_saif_set_clk(saif, mclk, rate);
209 ret = clk_enable(saif->clk);
213 /* enable MCLK output */
214 __raw_writel(BM_SAIF_CTRL_RUN,
215 saif->base + SAIF_CTRL + MXS_SET_ADDR);
221 * SAIF DAI format configuration.
222 * Should only be called when port is inactive.
224 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
228 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
230 stat = __raw_readl(saif->base + SAIF_STAT);
231 if (stat & BM_SAIF_STAT_BUSY) {
232 dev_err(cpu_dai->dev, "error: busy\n");
236 scr0 = __raw_readl(saif->base + SAIF_CTRL);
237 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
238 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
242 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
243 case SND_SOC_DAIFMT_I2S:
244 /* data frame low 1clk before data */
245 scr |= BM_SAIF_CTRL_DELAY;
246 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
248 case SND_SOC_DAIFMT_LEFT_J:
249 /* data frame high with data */
250 scr &= ~BM_SAIF_CTRL_DELAY;
251 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
252 scr &= ~BM_SAIF_CTRL_JUSTIFY;
258 /* DAI clock inversion */
259 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
260 case SND_SOC_DAIFMT_IB_IF:
261 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
262 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
264 case SND_SOC_DAIFMT_IB_NF:
265 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
266 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
268 case SND_SOC_DAIFMT_NB_IF:
269 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
270 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
272 case SND_SOC_DAIFMT_NB_NF:
273 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
274 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
279 * Note: We simply just support master mode since SAIF TX can only
282 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
283 case SND_SOC_DAIFMT_CBS_CFS:
284 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
285 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
294 static int mxs_saif_startup(struct snd_pcm_substream *substream,
295 struct snd_soc_dai *cpu_dai)
297 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
298 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
300 /* clear error status to 0 for each re-open */
301 saif->fifo_underrun = 0;
302 saif->fifo_overrun = 0;
304 /* Clear Reset for normal operations */
305 __raw_writel(BM_SAIF_CTRL_SFTRST,
306 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
308 /* clear clock gate */
309 __raw_writel(BM_SAIF_CTRL_CLKGATE,
310 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
316 * Should only be called when port is inactive.
317 * although can be called multiple times by upper layers.
319 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
320 struct snd_pcm_hw_params *params,
321 struct snd_soc_dai *cpu_dai)
323 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
327 /* mclk should already be set */
328 if (!saif->mclk && saif->mclk_in_use) {
329 dev_err(cpu_dai->dev, "set mclk first\n");
333 stat = __raw_readl(saif->base + SAIF_STAT);
334 if (stat & BM_SAIF_STAT_BUSY) {
335 dev_err(cpu_dai->dev, "error: busy\n");
340 * Set saif clk based on sample rate.
341 * If mclk is used, we also set mclk, if not, saif->mclk is
342 * default 0, means not used.
344 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
346 dev_err(cpu_dai->dev, "unable to get proper clk\n");
350 scr = __raw_readl(saif->base + SAIF_CTRL);
352 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
353 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
354 switch (params_format(params)) {
355 case SNDRV_PCM_FORMAT_S16_LE:
356 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
358 case SNDRV_PCM_FORMAT_S20_3LE:
359 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
360 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
362 case SNDRV_PCM_FORMAT_S24_LE:
363 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
364 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
371 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
373 scr &= ~BM_SAIF_CTRL_READ_MODE;
376 scr |= BM_SAIF_CTRL_READ_MODE;
379 __raw_writel(scr, saif->base + SAIF_CTRL);
383 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
384 struct snd_soc_dai *cpu_dai)
386 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
388 /* enable FIFO error irqs */
389 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
390 saif->base + SAIF_CTRL + MXS_SET_ADDR);
395 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
396 struct snd_soc_dai *cpu_dai)
398 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
401 case SNDRV_PCM_TRIGGER_START:
402 case SNDRV_PCM_TRIGGER_RESUME:
403 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
404 dev_dbg(cpu_dai->dev, "start\n");
406 clk_enable(saif->clk);
407 if (!saif->mclk_in_use)
408 __raw_writel(BM_SAIF_CTRL_RUN,
409 saif->base + SAIF_CTRL + MXS_SET_ADDR);
411 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
413 * write a data to saif data register to trigger
416 __raw_writel(0, saif->base + SAIF_DATA);
419 * read a data from saif data register to trigger
422 __raw_readl(saif->base + SAIF_DATA);
425 dev_dbg(cpu_dai->dev, "CTRL 0x%x STAT 0x%x\n",
426 __raw_readl(saif->base + SAIF_CTRL),
427 __raw_readl(saif->base + SAIF_STAT));
430 case SNDRV_PCM_TRIGGER_SUSPEND:
431 case SNDRV_PCM_TRIGGER_STOP:
432 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
433 dev_dbg(cpu_dai->dev, "stop\n");
435 clk_disable(saif->clk);
436 if (!saif->mclk_in_use)
437 __raw_writel(BM_SAIF_CTRL_RUN,
438 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
448 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
449 #define MXS_SAIF_FORMATS \
450 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
451 SNDRV_PCM_FMTBIT_S24_LE)
453 static struct snd_soc_dai_ops mxs_saif_dai_ops = {
454 .startup = mxs_saif_startup,
455 .trigger = mxs_saif_trigger,
456 .prepare = mxs_saif_prepare,
457 .hw_params = mxs_saif_hw_params,
458 .set_sysclk = mxs_saif_set_dai_sysclk,
459 .set_fmt = mxs_saif_set_dai_fmt,
462 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
464 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
466 snd_soc_dai_set_drvdata(dai, saif);
471 static struct snd_soc_dai_driver mxs_saif_dai = {
473 .probe = mxs_saif_dai_probe,
477 .rates = MXS_SAIF_RATES,
478 .formats = MXS_SAIF_FORMATS,
483 .rates = MXS_SAIF_RATES,
484 .formats = MXS_SAIF_FORMATS,
486 .ops = &mxs_saif_dai_ops,
489 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
491 struct mxs_saif *saif = dev_id;
494 stat = __raw_readl(saif->base + SAIF_STAT);
495 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
496 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
499 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
500 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
501 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
502 saif->base + SAIF_STAT + MXS_CLR_ADDR);
505 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
506 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
507 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
508 saif->base + SAIF_STAT + MXS_CLR_ADDR);
511 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
512 __raw_readl(saif->base + SAIF_CTRL),
513 __raw_readl(saif->base + SAIF_STAT));
518 static int mxs_saif_probe(struct platform_device *pdev)
520 struct resource *res;
521 struct mxs_saif *saif;
524 saif = kzalloc(sizeof(*saif), GFP_KERNEL);
528 if (pdev->id >= ARRAY_SIZE(mxs_saif))
530 mxs_saif[pdev->id] = saif;
532 saif->clk = clk_get(&pdev->dev, NULL);
533 if (IS_ERR(saif->clk)) {
534 ret = PTR_ERR(saif->clk);
535 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
540 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 dev_err(&pdev->dev, "failed to get io resource: %d\n",
545 goto failed_get_resource;
548 if (!request_mem_region(res->start, resource_size(res), "mxs-saif")) {
549 dev_err(&pdev->dev, "request_mem_region failed\n");
551 goto failed_get_resource;
554 saif->base = ioremap(res->start, resource_size(res));
556 dev_err(&pdev->dev, "ioremap failed\n");
561 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
564 dev_err(&pdev->dev, "failed to get dma resource: %d\n",
568 saif->dma_param.chan_num = res->start;
570 saif->irq = platform_get_irq(pdev, 0);
573 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
575 goto failed_get_irq1;
578 saif->dev = &pdev->dev;
579 ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
581 dev_err(&pdev->dev, "failed to request irq\n");
582 goto failed_get_irq1;
585 saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
586 if (saif->dma_param.chan_irq < 0) {
587 ret = saif->dma_param.chan_irq;
588 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
590 goto failed_get_irq2;
593 platform_set_drvdata(pdev, saif);
595 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
597 dev_err(&pdev->dev, "register DAI failed\n");
598 goto failed_register;
601 saif->soc_platform_pdev = platform_device_alloc(
602 "mxs-pcm-audio", pdev->id);
603 if (!saif->soc_platform_pdev) {
605 goto failed_pdev_alloc;
608 platform_set_drvdata(saif->soc_platform_pdev, saif);
609 ret = platform_device_add(saif->soc_platform_pdev);
611 dev_err(&pdev->dev, "failed to add soc platform device\n");
612 goto failed_pdev_add;
618 platform_device_put(saif->soc_platform_pdev);
620 snd_soc_unregister_dai(&pdev->dev);
623 free_irq(saif->irq, saif);
627 release_mem_region(res->start, resource_size(res));
636 static int __devexit mxs_saif_remove(struct platform_device *pdev)
638 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
639 struct mxs_saif *saif = platform_get_drvdata(pdev);
641 platform_device_unregister(saif->soc_platform_pdev);
643 snd_soc_unregister_dai(&pdev->dev);
646 release_mem_region(res->start, resource_size(res));
647 free_irq(saif->irq, saif);
655 static struct platform_driver mxs_saif_driver = {
656 .probe = mxs_saif_probe,
657 .remove = __devexit_p(mxs_saif_remove),
661 .owner = THIS_MODULE,
665 static int __init mxs_saif_init(void)
667 return platform_driver_register(&mxs_saif_driver);
670 static void __exit mxs_saif_exit(void)
672 platform_driver_unregister(&mxs_saif_driver);
675 module_init(mxs_saif_init);
676 module_exit(mxs_saif_exit);
677 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
678 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
679 MODULE_LICENSE("GPL");