2 * Intel SST Haswell/Broadwell IPC Support
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/device.h>
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/platform_device.h>
29 #include <linux/kthread.h>
30 #include <linux/firmware.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/debugfs.h>
33 #include <linux/pm_runtime.h>
34 #include <sound/asound.h>
36 #include "sst-haswell-ipc.h"
37 #include "../common/sst-dsp.h"
38 #include "../common/sst-dsp-priv.h"
39 #include "../common/sst-ipc.h"
41 /* Global Message - Generic */
42 #define IPC_GLB_TYPE_SHIFT 24
43 #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
44 #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
46 /* Global Message - Reply */
47 #define IPC_GLB_REPLY_SHIFT 0
48 #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
49 #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
51 /* Stream Message - Generic */
52 #define IPC_STR_TYPE_SHIFT 20
53 #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
54 #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
55 #define IPC_STR_ID_SHIFT 16
56 #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
57 #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
59 /* Stream Message - Reply */
60 #define IPC_STR_REPLY_SHIFT 0
61 #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
63 /* Stream Stage Message - Generic */
64 #define IPC_STG_TYPE_SHIFT 12
65 #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
66 #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
67 #define IPC_STG_ID_SHIFT 10
68 #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
69 #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
71 /* Stream Stage Message - Reply */
72 #define IPC_STG_REPLY_SHIFT 0
73 #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
75 /* Debug Log Message - Generic */
76 #define IPC_LOG_OP_SHIFT 20
77 #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
78 #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
79 #define IPC_LOG_ID_SHIFT 16
80 #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
81 #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
84 #define IPC_MODULE_OPERATION_SHIFT 20
85 #define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
86 #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
88 #define IPC_MODULE_ID_SHIFT 16
89 #define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
90 #define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
92 /* IPC message timeout (msecs) */
93 #define IPC_TIMEOUT_MSECS 300
94 #define IPC_BOOT_MSECS 200
95 #define IPC_MSG_WAIT 0
96 #define IPC_MSG_NOWAIT 1
98 /* Firmware Ready Message */
99 #define IPC_FW_READY (0x1 << 29)
100 #define IPC_STATUS_MASK (0x3 << 30)
102 #define IPC_EMPTY_LIST_SIZE 8
103 #define IPC_MAX_STREAMS 4
106 #define IPC_MAX_MAILBOX_BYTES 256
108 #define INVALID_STREAM_HW_ID 0xffffffff
110 /* Global Message - Types and Replies */
112 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
113 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
114 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
115 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
116 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
117 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
118 /* Request to store firmware context during D0->D3 transition */
119 IPC_GLB_REQUEST_DUMP = 7,
120 /* Request to restore firmware context during D3->D0 transition */
121 IPC_GLB_RESTORE_CONTEXT = 8,
122 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
123 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
124 IPC_GLB_SHORT_REPLY = 11,
125 IPC_GLB_ENTER_DX_STATE = 12,
126 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
127 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
128 IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
129 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
130 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
134 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
135 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
136 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
137 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
138 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
139 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
140 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
141 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
142 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
143 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
144 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
147 enum ipc_module_operation {
148 IPC_MODULE_NOTIFICATION = 0,
149 IPC_MODULE_ENABLE = 1,
150 IPC_MODULE_DISABLE = 2,
151 IPC_MODULE_GET_PARAMETER = 3,
152 IPC_MODULE_SET_PARAMETER = 4,
153 IPC_MODULE_GET_INFO = 5,
154 IPC_MODULE_MAX_MESSAGE
157 /* Stream Message - Types */
158 enum ipc_str_operation {
162 IPC_STR_STAGE_MESSAGE = 3,
163 IPC_STR_NOTIFICATION = 4,
167 /* Stream Stage Message Types */
168 enum ipc_stg_operation {
169 IPC_STG_GET_VOLUME = 0,
171 IPC_STG_SET_WRITE_POSITION,
172 IPC_STG_SET_FX_ENABLE,
173 IPC_STG_SET_FX_DISABLE,
174 IPC_STG_SET_FX_GET_PARAM,
175 IPC_STG_SET_FX_SET_PARAM,
176 IPC_STG_SET_FX_GET_INFO,
177 IPC_STG_MUTE_LOOPBACK,
181 /* Stream Stage Message Types For Notification*/
182 enum ipc_stg_operation_notify {
183 IPC_POSITION_CHANGED = 0,
188 enum ipc_glitch_type {
189 IPC_GLITCH_UNDERRUN = 1,
190 IPC_GLITCH_DECODER_ERROR,
191 IPC_GLITCH_DOUBLED_WRITE_POS,
196 enum ipc_debug_operation {
197 IPC_DEBUG_ENABLE_LOG = 0,
198 IPC_DEBUG_DISABLE_LOG = 1,
199 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
200 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
201 IPC_DEBUG_MAX_DEBUG_LOG
205 struct sst_hsw_ipc_fw_ready {
211 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
212 } __attribute__((packed));
214 struct sst_hsw_stream;
217 /* Stream infomation */
218 struct sst_hsw_stream {
220 struct sst_hsw_ipc_stream_alloc_req request;
221 struct sst_hsw_ipc_stream_alloc_reply reply;
222 struct sst_hsw_ipc_stream_free_req free_req;
225 u32 mute_volume[SST_HSW_NO_CHANNELS];
226 u32 mute[SST_HSW_NO_CHANNELS];
234 /* Notification work */
235 struct work_struct notify_work;
238 /* Position info from DSP */
239 struct sst_hsw_ipc_stream_set_position wpos;
240 struct sst_hsw_ipc_stream_get_position rpos;
241 struct sst_hsw_ipc_stream_glitch_position glitch;
244 struct sst_hsw_ipc_volume_req vol_req;
246 /* driver callback */
247 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
250 /* record the fw read position when playback */
251 snd_pcm_uframes_t old_position;
253 struct list_head node;
256 /* FW log ring information */
257 struct sst_hsw_log_stream {
259 unsigned char *dma_area;
260 unsigned char *ring_descr;
264 /* Notification work */
265 struct work_struct notify_work;
266 wait_queue_head_t readers_wait_q;
267 struct mutex rw_mutex;
274 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
279 /* SST Haswell IPC data */
283 struct platform_device *pdev_pcm;
286 struct sst_hsw_ipc_fw_ready fw_ready;
287 struct sst_hsw_ipc_fw_version version;
289 struct sst_fw *sst_fw;
292 struct list_head stream_list;
295 struct sst_hsw_ipc_stream_info_reply mixer_info;
296 enum sst_hsw_volume_curve curve_type;
298 u32 mute[SST_HSW_NO_CHANNELS];
299 u32 mute_volume[SST_HSW_NO_CHANNELS];
302 struct sst_hsw_ipc_dx_reply dx;
304 dma_addr_t dx_context_paddr;
305 enum sst_hsw_device_id dx_dev;
306 enum sst_hsw_device_mclk dx_mclk;
307 enum sst_hsw_device_mode dx_mode;
308 u32 dx_clock_divider;
311 wait_queue_head_t boot_wait;
316 struct sst_generic_ipc ipc;
319 struct sst_hsw_log_stream log_stream;
321 /* flags bit field to track module state when resume from RTD3,
322 * each bit represent state (enabled/disabled) of single module */
323 u32 enabled_modules_rtd3;
325 /* buffer to store parameter lines */
326 u32 param_idx_w; /* write index */
327 u32 param_idx_r; /* read index */
328 u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
331 #define CREATE_TRACE_POINTS
332 #include <trace/events/hswadsp.h>
334 static inline u32 msg_get_global_type(u32 msg)
336 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
339 static inline u32 msg_get_global_reply(u32 msg)
341 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
344 static inline u32 msg_get_stream_type(u32 msg)
346 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
349 static inline u32 msg_get_stage_type(u32 msg)
351 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
354 static inline u32 msg_get_stream_id(u32 msg)
356 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
359 static inline u32 msg_get_notify_reason(u32 msg)
361 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
364 static inline u32 msg_get_module_operation(u32 msg)
366 return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
369 static inline u32 msg_get_module_id(u32 msg)
371 return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
374 u32 create_channel_map(enum sst_hsw_channel_config config)
377 case SST_HSW_CHANNEL_CONFIG_MONO:
378 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
379 case SST_HSW_CHANNEL_CONFIG_STEREO:
380 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
381 | (SST_HSW_CHANNEL_RIGHT << 4));
382 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
383 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
384 | (SST_HSW_CHANNEL_RIGHT << 4)
385 | (SST_HSW_CHANNEL_LFE << 8 ));
386 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
387 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
388 | (SST_HSW_CHANNEL_CENTER << 4)
389 | (SST_HSW_CHANNEL_RIGHT << 8));
390 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
391 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
392 | (SST_HSW_CHANNEL_CENTER << 4)
393 | (SST_HSW_CHANNEL_RIGHT << 8)
394 | (SST_HSW_CHANNEL_LFE << 12));
395 case SST_HSW_CHANNEL_CONFIG_QUATRO:
396 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
397 | (SST_HSW_CHANNEL_RIGHT << 4)
398 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
399 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
400 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
401 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
402 | (SST_HSW_CHANNEL_CENTER << 4)
403 | (SST_HSW_CHANNEL_RIGHT << 8)
404 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
405 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
406 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
407 | (SST_HSW_CHANNEL_CENTER << 4)
408 | (SST_HSW_CHANNEL_RIGHT << 8)
409 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
410 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
411 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
412 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
413 | (SST_HSW_CHANNEL_LEFT << 4)
414 | (SST_HSW_CHANNEL_RIGHT << 8)
415 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
416 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
417 | (SST_HSW_CHANNEL_LFE << 20));
418 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
419 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
420 | (SST_HSW_CHANNEL_LEFT << 4));
426 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
429 struct sst_hsw_stream *stream;
431 list_for_each_entry(stream, &hsw->stream_list, node) {
432 if (stream->reply.stream_hw_id == stream_id)
439 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
441 struct sst_hsw_ipc_fw_ready fw_ready;
443 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
444 char *tmp[5], *pinfo;
447 offset = (header & 0x1FFFFFFF) << 3;
449 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
452 /* copy data from the DSP FW ready offset */
453 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
455 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
456 fw_ready.inbox_size, fw_ready.outbox_offset,
457 fw_ready.outbox_size);
459 hsw->boot_complete = true;
460 wake_up(&hsw->boot_wait);
462 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
463 fw_ready.inbox_offset, fw_ready.inbox_size);
464 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
465 fw_ready.outbox_offset, fw_ready.outbox_size);
466 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
467 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
468 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
470 /* log the FW version info got from the mailbox here. */
471 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
473 for (i = 0; i < ARRAY_SIZE(tmp); i++)
474 tmp[i] = strsep(&pinfo, " ");
475 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
476 "version: %s.%s, build %s, source commit id: %s\n",
477 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
481 static void hsw_notification_work(struct work_struct *work)
483 struct sst_hsw_stream *stream = container_of(work,
484 struct sst_hsw_stream, notify_work);
485 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
486 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
487 struct sst_hsw *hsw = stream->hsw;
490 reason = msg_get_notify_reason(stream->header);
494 trace_ipc_notification("DSP stream under/overrun",
495 stream->reply.stream_hw_id);
496 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
498 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
499 glitch->glitch_type, glitch->present_pos,
503 case IPC_POSITION_CHANGED:
504 trace_ipc_notification("DSP stream position changed for",
505 stream->reply.stream_hw_id);
506 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
508 if (stream->notify_position)
509 stream->notify_position(stream, stream->pdata);
513 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
518 /* tell DSP that notification has been handled */
519 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
520 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
522 /* unmask busy interrupt */
523 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
526 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
528 struct sst_hsw_stream *stream;
529 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
530 u32 stream_id = msg_get_stream_id(header);
531 u32 stream_msg = msg_get_stream_type(header);
533 stream = get_stream_by_id(hsw, stream_id);
537 switch (stream_msg) {
538 case IPC_STR_STAGE_MESSAGE:
539 case IPC_STR_NOTIFICATION:
542 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
545 stream->running = false;
546 trace_ipc_notification("stream paused",
547 stream->reply.stream_hw_id);
550 stream->running = true;
551 trace_ipc_notification("stream running",
552 stream->reply.stream_hw_id);
557 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
559 struct ipc_message *msg;
560 u32 reply = msg_get_global_reply(header);
562 trace_ipc_reply("processing -->", header);
564 msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
566 trace_ipc_error("error: can't find message header", header);
570 /* first process the header */
572 case IPC_GLB_REPLY_PENDING:
573 trace_ipc_pending_reply("received", header);
575 hsw->ipc.pending = true;
577 case IPC_GLB_REPLY_SUCCESS:
579 trace_ipc_pending_reply("completed", header);
580 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
582 hsw->ipc.pending = false;
584 /* copy data from the DSP */
585 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
589 /* these will be rare - but useful for debug */
590 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
591 trace_ipc_error("error: unknown message type", header);
592 msg->errno = -EBADMSG;
594 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
595 trace_ipc_error("error: out of resources", header);
596 msg->errno = -ENOMEM;
598 case IPC_GLB_REPLY_BUSY:
599 trace_ipc_error("error: reply busy", header);
602 case IPC_GLB_REPLY_FAILURE:
603 trace_ipc_error("error: reply failure", header);
604 msg->errno = -EINVAL;
606 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
607 trace_ipc_error("error: stage uninitialized", header);
608 msg->errno = -EINVAL;
610 case IPC_GLB_REPLY_NOT_FOUND:
611 trace_ipc_error("error: reply not found", header);
612 msg->errno = -EINVAL;
614 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
615 trace_ipc_error("error: source not started", header);
616 msg->errno = -EINVAL;
618 case IPC_GLB_REPLY_INVALID_REQUEST:
619 trace_ipc_error("error: invalid request", header);
620 msg->errno = -EINVAL;
622 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
623 trace_ipc_error("error: invalid parameter", header);
624 msg->errno = -EINVAL;
627 trace_ipc_error("error: unknown reply", header);
628 msg->errno = -EINVAL;
632 /* update any stream states */
633 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
634 hsw_stream_update(hsw, msg);
636 /* wake up and return the error if we have waiters on this message ? */
637 list_del(&msg->list);
638 sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
643 static int hsw_module_message(struct sst_hsw *hsw, u32 header)
645 u32 operation, module_id;
648 operation = msg_get_module_operation(header);
649 module_id = msg_get_module_id(header);
650 dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
652 dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
653 operation, module_id);
656 case IPC_MODULE_NOTIFICATION:
657 dev_dbg(hsw->dev, "module notification received");
661 handled = hsw_process_reply(hsw, header);
668 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
670 u32 stream_msg, stream_id, stage_type;
671 struct sst_hsw_stream *stream;
674 stream_msg = msg_get_stream_type(header);
675 stream_id = msg_get_stream_id(header);
676 stage_type = msg_get_stage_type(header);
678 stream = get_stream_by_id(hsw, stream_id);
682 stream->header = header;
684 switch (stream_msg) {
685 case IPC_STR_STAGE_MESSAGE:
686 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
689 case IPC_STR_NOTIFICATION:
690 schedule_work(&stream->notify_work);
693 /* handle pending message complete request */
694 handled = hsw_process_reply(hsw, header);
701 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
703 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
704 struct sst_hsw_log_stream *stream = &hsw->log_stream;
707 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
709 "error: log msg not implemented 0x%8.8x\n", header);
713 mutex_lock(&stream->rw_mutex);
714 stream->last_pos = stream->curr_pos;
716 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
717 mutex_unlock(&stream->rw_mutex);
719 schedule_work(&stream->notify_work);
724 static int hsw_process_notification(struct sst_hsw *hsw)
726 struct sst_dsp *sst = hsw->dsp;
730 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
731 type = msg_get_global_type(header);
733 trace_ipc_request("processing -->", header);
735 /* FW Ready is a special case */
736 if (!hsw->boot_complete && header & IPC_FW_READY) {
737 hsw_fw_ready(hsw, header);
742 case IPC_GLB_GET_FW_VERSION:
743 case IPC_GLB_ALLOCATE_STREAM:
744 case IPC_GLB_FREE_STREAM:
745 case IPC_GLB_GET_FW_CAPABILITIES:
746 case IPC_GLB_REQUEST_DUMP:
747 case IPC_GLB_GET_DEVICE_FORMATS:
748 case IPC_GLB_SET_DEVICE_FORMATS:
749 case IPC_GLB_ENTER_DX_STATE:
750 case IPC_GLB_GET_MIXER_STREAM_INFO:
751 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
752 case IPC_GLB_RESTORE_CONTEXT:
753 case IPC_GLB_SHORT_REPLY:
754 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
757 case IPC_GLB_STREAM_MESSAGE:
758 handled = hsw_stream_message(hsw, header);
760 case IPC_GLB_DEBUG_LOG_MESSAGE:
761 handled = hsw_log_message(hsw, header);
763 case IPC_GLB_MODULE_OPERATION:
764 handled = hsw_module_message(hsw, header);
767 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
775 static irqreturn_t hsw_irq_thread(int irq, void *context)
777 struct sst_dsp *sst = (struct sst_dsp *) context;
778 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
779 struct sst_generic_ipc *ipc = &hsw->ipc;
784 spin_lock_irqsave(&sst->spinlock, flags);
786 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
787 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
789 /* reply message from DSP */
790 if (ipcx & SST_IPCX_DONE) {
792 /* Handle Immediate reply from DSP Core */
793 handled = hsw_process_reply(hsw, ipcx);
796 /* clear DONE bit - tell DSP we have completed */
797 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
800 /* unmask Done interrupt */
801 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
806 /* new message from DSP */
807 if (ipcd & SST_IPCD_BUSY) {
809 /* Handle Notification and Delayed reply from DSP Core */
810 handled = hsw_process_notification(hsw);
812 /* clear BUSY bit and set DONE bit - accept new messages */
814 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
815 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
817 /* unmask busy interrupt */
818 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
823 spin_unlock_irqrestore(&sst->spinlock, flags);
825 /* continue to send any remaining messages... */
826 queue_kthread_work(&ipc->kworker, &ipc->kwork);
831 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
832 struct sst_hsw_ipc_fw_version *version)
836 ret = sst_ipc_tx_message_wait(&hsw->ipc,
837 IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
838 NULL, 0, version, sizeof(*version));
840 dev_err(hsw->dev, "error: get version failed\n");
846 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
847 u32 stage_id, u32 channel, u32 *volume)
852 sst_dsp_read(hsw->dsp, volume,
853 stream->reply.volume_register_address[channel],
860 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
861 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
863 struct sst_hsw_ipc_volume_req *req;
867 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
869 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
872 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
873 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
874 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
875 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
876 header |= (stage_id << IPC_STG_ID_SHIFT);
878 req = &stream->vol_req;
879 req->target_volume = volume;
881 /* set both at same time ? */
882 if (channel == SST_HSW_CHANNELS_ALL) {
883 if (hsw->mute[0] && hsw->mute[1]) {
884 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
886 } else if (hsw->mute[0])
888 else if (hsw->mute[1])
891 req->channel = SST_HSW_CHANNELS_ALL;
893 /* set only 1 channel */
894 if (hsw->mute[channel]) {
895 hsw->mute_volume[channel] = volume;
898 req->channel = channel;
901 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
902 sizeof(*req), NULL, 0);
904 dev_err(hsw->dev, "error: set stream volume failed\n");
911 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
917 sst_dsp_read(hsw->dsp, volume,
918 hsw->mixer_info.volume_register_address[channel],
924 /* global mixer volume */
925 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
928 struct sst_hsw_ipc_volume_req req;
932 trace_ipc_request("set mixer volume", volume);
934 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
937 /* set both at same time ? */
938 if (channel == SST_HSW_CHANNELS_ALL) {
939 if (hsw->mute[0] && hsw->mute[1]) {
940 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
942 } else if (hsw->mute[0])
944 else if (hsw->mute[1])
947 req.channel = SST_HSW_CHANNELS_ALL;
949 /* set only 1 channel */
950 if (hsw->mute[channel]) {
951 hsw->mute_volume[channel] = volume;
954 req.channel = channel;
957 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
958 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
959 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
960 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
961 header |= (stage_id << IPC_STG_ID_SHIFT);
963 req.curve_duration = hsw->curve_duration;
964 req.curve_type = hsw->curve_type;
965 req.target_volume = volume;
967 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
968 sizeof(req), NULL, 0);
970 dev_err(hsw->dev, "error: set mixer volume failed\n");
978 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
979 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
982 struct sst_hsw_stream *stream;
983 struct sst_dsp *sst = hsw->dsp;
986 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
990 spin_lock_irqsave(&sst->spinlock, flags);
991 stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
992 list_add(&stream->node, &hsw->stream_list);
993 stream->notify_position = notify_position;
994 stream->pdata = data;
996 stream->host_id = id;
998 /* work to process notification messages */
999 INIT_WORK(&stream->notify_work, hsw_notification_work);
1000 spin_unlock_irqrestore(&sst->spinlock, flags);
1005 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1009 struct sst_dsp *sst = hsw->dsp;
1010 unsigned long flags;
1013 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1017 /* dont free DSP streams that are not commited */
1018 if (!stream->commited)
1021 trace_ipc_request("stream free", stream->host_id);
1023 stream->free_req.stream_id = stream->reply.stream_hw_id;
1024 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1026 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
1027 sizeof(stream->free_req), NULL, 0);
1029 dev_err(hsw->dev, "error: free stream %d failed\n",
1030 stream->free_req.stream_id);
1034 trace_hsw_stream_free_req(stream, &stream->free_req);
1037 cancel_work_sync(&stream->notify_work);
1038 spin_lock_irqsave(&sst->spinlock, flags);
1039 list_del(&stream->node);
1041 spin_unlock_irqrestore(&sst->spinlock, flags);
1046 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1047 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1049 if (stream->commited) {
1050 dev_err(hsw->dev, "error: stream committed for set bits\n");
1054 stream->request.format.bitdepth = bits;
1058 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1059 struct sst_hsw_stream *stream, int channels)
1061 if (stream->commited) {
1062 dev_err(hsw->dev, "error: stream committed for set channels\n");
1066 stream->request.format.ch_num = channels;
1070 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1071 struct sst_hsw_stream *stream, int rate)
1073 if (stream->commited) {
1074 dev_err(hsw->dev, "error: stream committed for set rate\n");
1078 stream->request.format.frequency = rate;
1082 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1083 struct sst_hsw_stream *stream, u32 map,
1084 enum sst_hsw_channel_config config)
1086 if (stream->commited) {
1087 dev_err(hsw->dev, "error: stream committed for set map\n");
1091 stream->request.format.map = map;
1092 stream->request.format.config = config;
1096 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1097 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1099 if (stream->commited) {
1100 dev_err(hsw->dev, "error: stream committed for set style\n");
1104 stream->request.format.style = style;
1108 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1109 struct sst_hsw_stream *stream, u32 bits)
1111 if (stream->commited) {
1112 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1116 stream->request.format.valid_bit = bits;
1120 /* Stream Configuration */
1121 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1122 enum sst_hsw_stream_path_id path_id,
1123 enum sst_hsw_stream_type stream_type,
1124 enum sst_hsw_stream_format format_id)
1126 if (stream->commited) {
1127 dev_err(hsw->dev, "error: stream committed for set format\n");
1131 stream->request.path_id = path_id;
1132 stream->request.stream_type = stream_type;
1133 stream->request.format_id = format_id;
1135 trace_hsw_stream_alloc_request(stream, &stream->request);
1140 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1141 u32 ring_pt_address, u32 num_pages,
1142 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1144 if (stream->commited) {
1145 dev_err(hsw->dev, "error: stream committed for buffer\n");
1149 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1150 stream->request.ringinfo.num_pages = num_pages;
1151 stream->request.ringinfo.ring_size = ring_size;
1152 stream->request.ringinfo.ring_offset = ring_offset;
1153 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1155 trace_hsw_stream_buffer(stream);
1160 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1161 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1163 struct sst_hsw_module_map *map = &stream->request.map;
1164 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1165 struct sst_module *module = runtime->module;
1167 if (stream->commited) {
1168 dev_err(hsw->dev, "error: stream committed for set module\n");
1172 /* only support initial module atm */
1173 map->module_entries_count = 1;
1174 map->module_entries[0].module_id = module->id;
1175 map->module_entries[0].entry_point = module->entry;
1177 stream->request.persistent_mem.offset =
1178 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1179 stream->request.persistent_mem.size = module->persistent_size;
1181 stream->request.scratch_mem.offset =
1182 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1183 stream->request.scratch_mem.size = dsp->scratch_size;
1185 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1187 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1188 stream->request.persistent_mem.offset,
1189 stream->request.persistent_mem.size);
1190 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1191 stream->request.scratch_mem.offset,
1192 stream->request.scratch_mem.size);
1197 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1199 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1200 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1205 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1209 if (stream->commited) {
1210 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1214 trace_ipc_request("stream alloc", stream->host_id);
1216 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1218 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1219 sizeof(*str_req), reply, sizeof(*reply));
1221 dev_err(hsw->dev, "error: stream commit failed\n");
1225 stream->commited = 1;
1226 trace_hsw_stream_alloc_reply(stream);
1231 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1232 struct sst_hsw_stream *stream)
1234 return stream->old_position;
1237 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1238 struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1240 stream->old_position = val;
1243 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1244 struct sst_hsw_stream *stream)
1246 return stream->play_silence;
1249 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1250 struct sst_hsw_stream *stream, bool val)
1252 stream->play_silence = val;
1255 /* Stream Information - these calls could be inline but we want the IPC
1256 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1257 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1259 struct sst_hsw_ipc_stream_info_reply *reply;
1263 reply = &hsw->mixer_info;
1264 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1266 trace_ipc_request("get global mixer info", 0);
1268 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1269 reply, sizeof(*reply));
1271 dev_err(hsw->dev, "error: get stream info failed\n");
1275 trace_hsw_mixer_info_reply(reply);
1280 /* Send stream command */
1281 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1282 int stream_id, int wait)
1286 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1287 header |= (stream_id << IPC_STR_ID_SHIFT);
1290 return sst_ipc_tx_message_wait(&hsw->ipc, header,
1293 return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
1296 /* Stream ALSA trigger operations */
1297 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1303 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1307 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1309 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1310 stream->reply.stream_hw_id, wait);
1312 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1313 stream->reply.stream_hw_id);
1318 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1324 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1328 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1330 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1331 stream->reply.stream_hw_id, wait);
1333 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1334 stream->reply.stream_hw_id);
1339 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1341 int ret, tries = 10;
1344 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1348 /* dont reset streams that are not commited */
1349 if (!stream->commited)
1352 /* wait for pause to complete before we reset the stream */
1353 while (stream->running && tries--)
1356 dev_err(hsw->dev, "error: reset stream %d still running\n",
1357 stream->reply.stream_hw_id);
1361 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1363 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1364 stream->reply.stream_hw_id, 1);
1366 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1367 stream->reply.stream_hw_id);
1371 /* Stream pointer positions */
1372 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1373 struct sst_hsw_stream *stream)
1377 sst_dsp_read(hsw->dsp, &rpos,
1378 stream->reply.read_position_register_address, sizeof(rpos));
1383 /* Stream presentation (monotonic) positions */
1384 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1385 struct sst_hsw_stream *stream)
1389 sst_dsp_read(hsw->dsp, &ppos,
1390 stream->reply.presentation_position_register_address,
1396 /* physical BE config */
1397 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1398 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1399 enum sst_hsw_device_mode mode, u32 clock_divider)
1401 struct sst_hsw_ipc_device_config_req config;
1405 trace_ipc_request("set device config", dev);
1407 hsw->dx_dev = config.ssp_interface = dev;
1408 hsw->dx_mclk = config.clock_frequency = mclk;
1409 hsw->dx_mode = config.mode = mode;
1410 hsw->dx_clock_divider = config.clock_divider = clock_divider;
1411 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1412 config.channels = 4;
1414 config.channels = 2;
1416 trace_hsw_device_config_req(&config);
1418 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1420 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1421 sizeof(config), NULL, 0);
1423 dev_err(hsw->dev, "error: set device formats failed\n");
1427 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1430 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1431 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1436 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1439 trace_ipc_request("PM enter Dx state", state);
1441 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1442 sizeof(state_), dx, sizeof(*dx));
1444 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1448 for (item = 0; item < dx->entries_no; item++) {
1450 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1451 item, dx->mem_info[item].offset,
1452 dx->mem_info[item].size,
1453 dx->mem_info[item].source);
1455 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1456 dx->entries_no, state);
1461 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1462 int mod_id, int offset)
1464 struct sst_dsp *dsp = hsw->dsp;
1465 struct sst_module *module;
1466 struct sst_module_runtime *runtime;
1469 module = sst_module_get_from_id(dsp, mod_id);
1470 if (module == NULL) {
1471 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1476 runtime = sst_module_runtime_new(module, mod_id, NULL);
1477 if (runtime == NULL) {
1478 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1483 err = sst_module_runtime_alloc_blocks(runtime, offset);
1485 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1487 sst_module_runtime_free(runtime);
1491 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1496 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1498 sst_module_runtime_free_blocks(runtime);
1499 sst_module_runtime_free(runtime);
1503 static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1505 struct sst_dsp *sst = hsw->dsp;
1506 u32 item, offset, size;
1509 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1511 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1513 "error: number of FW context regions greater than %d\n",
1514 SST_HSW_MAX_DX_REGIONS);
1515 memset(&hsw->dx, 0, sizeof(hsw->dx));
1519 ret = sst_dsp_dma_get_channel(sst, 0);
1521 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1525 /* set on-demond mode on engine 0 channel 3 */
1526 sst_dsp_shim_update_bits(sst, SST_HMDC,
1527 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1528 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1530 for (item = 0; item < hsw->dx.entries_no; item++) {
1531 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1532 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1533 && hsw->dx.mem_info[item].offset <
1534 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1536 offset = hsw->dx.mem_info[item].offset
1537 - DSP_DRAM_ADDR_OFFSET;
1538 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1540 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1541 sst->addr.lpe_base + offset, size);
1544 "error: FW context dump failed\n");
1545 memset(&hsw->dx, 0, sizeof(hsw->dx));
1552 sst_dsp_dma_put_channel(sst);
1556 static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1558 struct sst_dsp *sst = hsw->dsp;
1559 u32 item, offset, size;
1562 for (item = 0; item < hsw->dx.entries_no; item++) {
1563 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1564 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1565 && hsw->dx.mem_info[item].offset <
1566 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1568 offset = hsw->dx.mem_info[item].offset
1569 - DSP_DRAM_ADDR_OFFSET;
1570 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1572 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1573 hsw->dx_context_paddr + offset, size);
1576 "error: FW context restore failed\n");
1585 int sst_hsw_dsp_load(struct sst_hsw *hsw)
1587 struct sst_dsp *dsp = hsw->dsp;
1588 struct sst_fw *sst_fw, *t;
1591 dev_dbg(hsw->dev, "loading audio DSP....");
1593 ret = sst_dsp_wake(dsp);
1595 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1599 ret = sst_dsp_dma_get_channel(dsp, 0);
1601 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1605 list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1606 ret = sst_fw_reload(sst_fw);
1608 dev_err(hsw->dev, "error: SST FW reload failed\n");
1609 sst_dsp_dma_put_channel(dsp);
1613 ret = sst_block_alloc_scratch(hsw->dsp);
1617 sst_dsp_dma_put_channel(dsp);
1621 static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1623 struct sst_dsp *dsp = hsw->dsp;
1626 dev_dbg(hsw->dev, "restoring audio DSP....");
1628 ret = sst_dsp_dma_get_channel(dsp, 0);
1630 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1634 ret = sst_hsw_dx_state_restore(hsw);
1636 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1637 sst_dsp_dma_put_channel(dsp);
1640 sst_dsp_dma_put_channel(dsp);
1642 /* wait for DSP boot completion */
1648 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1652 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1654 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1658 sst_dsp_stall(hsw->dsp);
1660 ret = sst_hsw_dx_state_dump(hsw);
1664 sst_ipc_drop_all(&hsw->ipc);
1669 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1671 struct sst_fw *sst_fw, *t;
1672 struct sst_dsp *dsp = hsw->dsp;
1674 list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1675 sst_fw_unload(sst_fw);
1677 sst_block_free_scratch(dsp);
1679 hsw->boot_complete = false;
1686 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1688 struct device *dev = hsw->dev;
1691 dev_dbg(dev, "audio dsp runtime resume\n");
1693 if (hsw->boot_complete)
1694 return 1; /* tell caller no action is required */
1696 ret = sst_hsw_dsp_restore(hsw);
1698 dev_err(dev, "error: audio DSP boot failure\n");
1700 sst_hsw_init_module_state(hsw);
1702 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1703 msecs_to_jiffies(IPC_BOOT_MSECS));
1705 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1706 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1707 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1711 /* Set ADSP SSP port settings - sadly the FW does not store SSP port
1712 settings as part of the PM context. */
1713 ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1714 hsw->dx_mode, hsw->dx_clock_divider);
1716 dev_err(dev, "error: SSP re-initialization failed\n");
1722 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1727 void sst_hsw_init_module_state(struct sst_hsw *hsw)
1729 struct sst_module *module;
1730 enum sst_hsw_module_id id;
1732 /* the base fw contains several modules */
1733 for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1734 module = sst_module_get_from_id(hsw->dsp, id);
1736 /* module waves is active only after being enabled */
1737 if (id == SST_HSW_MODULE_WAVES)
1738 module->state = SST_MODULE_STATE_INITIALIZED;
1740 module->state = SST_MODULE_STATE_ACTIVE;
1745 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1747 struct sst_module *module;
1749 module = sst_module_get_from_id(hsw->dsp, module_id);
1750 if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1756 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1758 struct sst_module *module;
1760 module = sst_module_get_from_id(hsw->dsp, module_id);
1761 if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1767 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1769 hsw->enabled_modules_rtd3 |= (1 << module_id);
1772 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1774 hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1777 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1779 return hsw->enabled_modules_rtd3 & (1 << module_id);
1782 void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1784 hsw->param_idx_w = 0;
1785 hsw->param_idx_r = 0;
1786 memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1789 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1791 /* save line to the first available position of param buffer */
1792 if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1793 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1796 memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1801 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1805 /* read the first matching line from param buffer */
1806 while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1807 id = hsw->param_buf[hsw->param_idx_r][0];
1810 memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1815 if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1816 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1817 hsw->param_idx_r = 0;
1823 int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1827 if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1828 dev_dbg(hsw->dev, "module waves is not active\n");
1832 /* put all param lines to DSP through ipc */
1833 for (idx = 0; idx < hsw->param_idx_w; idx++) {
1834 ret = sst_hsw_module_set_param(hsw,
1835 SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1836 WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1843 int sst_hsw_module_load(struct sst_hsw *hsw,
1844 u32 module_id, u32 instance_id, char *name)
1847 const struct firmware *fw = NULL;
1848 struct sst_fw *hsw_sst_fw;
1849 struct sst_module *module;
1850 struct device *dev = hsw->dev;
1851 struct sst_dsp *dsp = hsw->dsp;
1853 dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1855 module = sst_module_get_from_id(dsp, module_id);
1856 if (module == NULL) {
1857 /* loading for the first time */
1858 if (module_id == SST_HSW_MODULE_BASE_FW) {
1859 /* for base module: use fw requested in acpi probe */
1860 fw = dsp->pdata->fw;
1862 dev_err(dev, "request Base fw failed\n");
1866 /* try and load any other optional modules if they are
1867 * available. Use dev_info instead of dev_err in case
1868 * request firmware failed */
1869 ret = request_firmware(&fw, name, dev);
1871 dev_info(dev, "fw image %s not available(%d)\n",
1876 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1877 if (hsw_sst_fw == NULL) {
1878 dev_err(dev, "error: failed to load firmware\n");
1882 module = sst_module_get_from_id(dsp, module_id);
1883 if (module == NULL) {
1884 dev_err(dev, "error: no module %d in firmware %s\n",
1888 dev_info(dev, "module %d (%s) already loaded\n",
1891 /* release fw, but base fw should be released by acpi driver */
1892 if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1893 release_firmware(fw);
1898 int sst_hsw_module_enable(struct sst_hsw *hsw,
1899 u32 module_id, u32 instance_id)
1903 struct sst_hsw_ipc_module_config config;
1904 struct sst_module *module;
1905 struct sst_module_runtime *runtime;
1906 struct device *dev = hsw->dev;
1907 struct sst_dsp *dsp = hsw->dsp;
1909 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1910 dev_dbg(dev, "module %d not loaded\n", module_id);
1914 if (sst_hsw_is_module_active(hsw, module_id)) {
1915 dev_info(dev, "module %d already enabled\n", module_id);
1919 module = sst_module_get_from_id(dsp, module_id);
1920 if (module == NULL) {
1921 dev_err(dev, "module %d not valid\n", module_id);
1925 runtime = sst_module_runtime_get_from_id(module, module_id);
1926 if (runtime == NULL) {
1927 dev_err(dev, "runtime %d not valid", module_id);
1931 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1932 IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1933 IPC_MODULE_ID(module_id);
1934 dev_dbg(dev, "module enable header: %x\n", header);
1936 config.map.module_entries_count = 1;
1937 config.map.module_entries[0].module_id = module->id;
1938 config.map.module_entries[0].entry_point = module->entry;
1940 config.persistent_mem.offset =
1941 sst_dsp_get_offset(dsp,
1942 runtime->persistent_offset, SST_MEM_DRAM);
1943 config.persistent_mem.size = module->persistent_size;
1945 config.scratch_mem.offset =
1946 sst_dsp_get_offset(dsp,
1947 dsp->scratch_offset, SST_MEM_DRAM);
1948 config.scratch_mem.size = module->scratch_size;
1949 dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1950 config.map.module_entries[0].module_id,
1951 config.persistent_mem.size,
1952 config.persistent_mem.offset,
1953 config.scratch_mem.size, config.scratch_mem.offset,
1954 config.map.module_entries[0].entry_point);
1956 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
1957 &config, sizeof(config), NULL, 0);
1959 dev_err(dev, "ipc: module enable failed - %d\n", ret);
1961 module->state = SST_MODULE_STATE_ACTIVE;
1966 int sst_hsw_module_disable(struct sst_hsw *hsw,
1967 u32 module_id, u32 instance_id)
1971 struct sst_module *module;
1972 struct device *dev = hsw->dev;
1973 struct sst_dsp *dsp = hsw->dsp;
1975 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1976 dev_dbg(dev, "module %d not loaded\n", module_id);
1980 if (!sst_hsw_is_module_active(hsw, module_id)) {
1981 dev_info(dev, "module %d already disabled\n", module_id);
1985 module = sst_module_get_from_id(dsp, module_id);
1986 if (module == NULL) {
1987 dev_err(dev, "module %d not valid\n", module_id);
1991 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1992 IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1993 IPC_MODULE_ID(module_id);
1995 ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0, NULL, 0);
1997 dev_err(dev, "module disable failed - %d\n", ret);
1999 module->state = SST_MODULE_STATE_INITIALIZED;
2004 int sst_hsw_module_set_param(struct sst_hsw *hsw,
2005 u32 module_id, u32 instance_id, u32 parameter_id,
2006 u32 param_size, char *param)
2009 unsigned char *data = NULL;
2011 u32 payload_size = 0, transfer_parameter_size = 0;
2012 dma_addr_t dma_addr = 0;
2013 struct sst_hsw_transfer_parameter *parameter;
2014 struct device *dev = hsw->dev;
2016 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2017 IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2018 IPC_MODULE_ID(module_id);
2019 dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2021 payload_size = param_size +
2022 sizeof(struct sst_hsw_transfer_parameter) -
2023 sizeof(struct sst_hsw_transfer_list);
2024 dev_dbg(dev, "parameter size : %d\n", param_size);
2025 dev_dbg(dev, "payload size : %d\n", payload_size);
2027 if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2028 /* short parameter, mailbox can contain data */
2029 dev_dbg(dev, "transfer parameter size : %d\n",
2030 transfer_parameter_size);
2032 transfer_parameter_size = ALIGN(payload_size, 4);
2033 dev_dbg(dev, "transfer parameter aligned size : %d\n",
2034 transfer_parameter_size);
2036 parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2037 if (parameter == NULL)
2040 memcpy(parameter->data, param, param_size);
2042 dev_warn(dev, "transfer parameter size too large!");
2046 parameter->parameter_id = parameter_id;
2047 parameter->data_size = param_size;
2049 ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
2050 parameter, transfer_parameter_size , NULL, 0);
2052 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2057 dma_free_coherent(hsw->dsp->dma_dev,
2058 param_size, (void *)data, dma_addr);
2063 static struct sst_dsp_device hsw_dev = {
2064 .thread = hsw_irq_thread,
2065 .ops = &haswell_ops,
2068 static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2070 /* send the message */
2071 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2072 sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2075 static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2077 struct sst_dsp *sst = ipc->dsp;
2078 u32 isr, ipcd, imrx, ipcx;
2080 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2081 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2082 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2083 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2086 "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2087 text, ipcx, isr, ipcd, imrx);
2090 static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2093 memcpy(msg->tx_data, tx_data, tx_size);
2096 static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2098 /* clear reply bits & status bits */
2099 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2105 static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2109 ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2110 return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2113 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2115 struct sst_hsw_ipc_fw_version version;
2116 struct sst_hsw *hsw;
2117 struct sst_generic_ipc *ipc;
2120 dev_dbg(dev, "initialising Audio DSP IPC\n");
2122 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2130 ipc->ops.tx_msg = hsw_tx_msg;
2131 ipc->ops.shim_dbg = hsw_shim_dbg;
2132 ipc->ops.tx_data_copy = hsw_tx_data_copy;
2133 ipc->ops.reply_msg_match = hsw_reply_msg_match;
2134 ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
2136 ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2137 ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2139 ret = sst_ipc_init(ipc);
2143 INIT_LIST_HEAD(&hsw->stream_list);
2144 init_waitqueue_head(&hsw->boot_wait);
2145 hsw_dev.thread_context = hsw;
2148 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2149 if (hsw->dsp == NULL) {
2154 ipc->dsp = hsw->dsp;
2156 /* allocate DMA buffer for context storage */
2157 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2158 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2159 if (hsw->dx_context == NULL) {
2164 /* keep the DSP in reset state for base FW loading */
2165 sst_dsp_reset(hsw->dsp);
2167 /* load base module and other modules in base firmware image */
2168 ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2172 /* try to load module waves */
2173 sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2175 /* allocate scratch mem regions */
2176 ret = sst_block_alloc_scratch(hsw->dsp);
2180 /* init param buffer */
2181 sst_hsw_reset_param_buf(hsw);
2183 /* wait for DSP boot completion */
2184 sst_dsp_boot(hsw->dsp);
2185 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2186 msecs_to_jiffies(IPC_BOOT_MSECS));
2189 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2190 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2191 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2195 /* init module state after boot */
2196 sst_hsw_init_module_state(hsw);
2198 /* get the FW version */
2199 sst_hsw_fw_get_version(hsw, &version);
2201 /* get the globalmixer */
2202 ret = sst_hsw_mixer_get_info(hsw);
2204 dev_err(hsw->dev, "error: failed to get stream info\n");
2212 sst_dsp_reset(hsw->dsp);
2213 sst_fw_free_all(hsw->dsp);
2215 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2216 hsw->dx_context, hsw->dx_context_paddr);
2218 sst_dsp_free(hsw->dsp);
2224 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2226 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2228 struct sst_hsw *hsw = pdata->dsp;
2230 sst_dsp_reset(hsw->dsp);
2231 sst_fw_free_all(hsw->dsp);
2232 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2233 hsw->dx_context, hsw->dx_context_paddr);
2234 sst_dsp_free(hsw->dsp);
2235 sst_ipc_fini(&hsw->ipc);
2237 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);