2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/of_address.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_platform.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/initval.h>
49 #include <sound/soc.h>
50 #include <sound/dmaengine_pcm.h>
56 #define read_ssi(addr) in_be32(addr)
57 #define write_ssi(val, addr) out_be32(addr, val)
58 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
60 #define read_ssi(addr) readl(addr)
61 #define write_ssi(val, addr) writel(val, addr)
63 * FIXME: Proper locking should be added at write_ssi_mask caller level
64 * to ensure this register read/modify/write sequence is race free.
66 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
75 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * This driver currently only supports the SSI running in I2S slave mode,
78 * which means the codec determines the sample rate. Therefore, we tell
79 * ALSA that we support all rates and let the codec driver decide what rates
80 * are really supported.
82 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 /* SIER bitflag of interrupts to enable */
110 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
117 * fsl_ssi_private: per-SSI private data
119 * @ssi: pointer to the SSI's registers
120 * @ssi_phys: physical address of the SSI registers
121 * @irq: IRQ of this SSI
122 * @first_stream: pointer to the stream that was opened first
123 * @second_stream: pointer to second stream
124 * @playback: the number of playback streams opened
125 * @capture: the number of capture streams opened
126 * @cpu_dai: the CPU DAI for this device
127 * @dev_attr: the sysfs device attribute structure
128 * @stats: SSI statistics
129 * @name: name for this device
131 struct fsl_ssi_private {
132 struct ccsr_ssi __iomem *ssi;
135 struct snd_pcm_substream *first_stream;
136 struct snd_pcm_substream *second_stream;
137 unsigned int fifo_depth;
138 struct snd_soc_dai_driver cpu_dai_drv;
139 struct device_attribute dev_attr;
140 struct platform_device *pdev;
148 struct snd_dmaengine_dai_dma_data dma_params_tx;
149 struct snd_dmaengine_dai_dma_data dma_params_rx;
150 struct imx_dma_data filter_data_tx;
151 struct imx_dma_data filter_data_rx;
152 struct imx_pcm_fiq_params fiq_params;
182 * fsl_ssi_isr: SSI interrupt handler
184 * Although it's possible to use the interrupt handler to send and receive
185 * data to/from the SSI, we use the DMA instead. Programming is more
186 * complicated, but the performance is much better.
188 * This interrupt handler is used only to gather statistics.
190 * @irq: IRQ of the SSI device
191 * @dev_id: pointer to the ssi_private structure for this SSI device
193 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
195 struct fsl_ssi_private *ssi_private = dev_id;
196 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
197 irqreturn_t ret = IRQ_NONE;
201 /* We got an interrupt, so read the status register to see what we
202 were interrupted for. We mask it with the Interrupt Enable register
203 so that we only check for events that we're interested in.
205 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
207 if (sisr & CCSR_SSI_SISR_RFRC) {
208 ssi_private->stats.rfrc++;
209 sisr2 |= CCSR_SSI_SISR_RFRC;
213 if (sisr & CCSR_SSI_SISR_TFRC) {
214 ssi_private->stats.tfrc++;
215 sisr2 |= CCSR_SSI_SISR_TFRC;
219 if (sisr & CCSR_SSI_SISR_CMDAU) {
220 ssi_private->stats.cmdau++;
224 if (sisr & CCSR_SSI_SISR_CMDDU) {
225 ssi_private->stats.cmddu++;
229 if (sisr & CCSR_SSI_SISR_RXT) {
230 ssi_private->stats.rxt++;
234 if (sisr & CCSR_SSI_SISR_RDR1) {
235 ssi_private->stats.rdr1++;
239 if (sisr & CCSR_SSI_SISR_RDR0) {
240 ssi_private->stats.rdr0++;
244 if (sisr & CCSR_SSI_SISR_TDE1) {
245 ssi_private->stats.tde1++;
249 if (sisr & CCSR_SSI_SISR_TDE0) {
250 ssi_private->stats.tde0++;
254 if (sisr & CCSR_SSI_SISR_ROE1) {
255 ssi_private->stats.roe1++;
256 sisr2 |= CCSR_SSI_SISR_ROE1;
260 if (sisr & CCSR_SSI_SISR_ROE0) {
261 ssi_private->stats.roe0++;
262 sisr2 |= CCSR_SSI_SISR_ROE0;
266 if (sisr & CCSR_SSI_SISR_TUE1) {
267 ssi_private->stats.tue1++;
268 sisr2 |= CCSR_SSI_SISR_TUE1;
272 if (sisr & CCSR_SSI_SISR_TUE0) {
273 ssi_private->stats.tue0++;
274 sisr2 |= CCSR_SSI_SISR_TUE0;
278 if (sisr & CCSR_SSI_SISR_TFS) {
279 ssi_private->stats.tfs++;
283 if (sisr & CCSR_SSI_SISR_RFS) {
284 ssi_private->stats.rfs++;
288 if (sisr & CCSR_SSI_SISR_TLS) {
289 ssi_private->stats.tls++;
293 if (sisr & CCSR_SSI_SISR_RLS) {
294 ssi_private->stats.rls++;
298 if (sisr & CCSR_SSI_SISR_RFF1) {
299 ssi_private->stats.rff1++;
303 if (sisr & CCSR_SSI_SISR_RFF0) {
304 ssi_private->stats.rff0++;
308 if (sisr & CCSR_SSI_SISR_TFE1) {
309 ssi_private->stats.tfe1++;
313 if (sisr & CCSR_SSI_SISR_TFE0) {
314 ssi_private->stats.tfe0++;
318 /* Clear the bits that we set */
320 write_ssi(sisr2, &ssi->sisr);
325 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
327 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
330 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
332 if (ssi_private->imx_ac97)
333 i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
335 i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
338 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
339 * to be disabled before updating the registers we set here.
341 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
344 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
345 * enable the transmit and receive FIFO.
347 * FIXME: Little-endian samples require a different shift dir
349 write_ssi_mask(&ssi->scr,
350 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
351 CCSR_SSI_SCR_TFR_CLK_DIS |
353 (synchronous ? CCSR_SSI_SCR_SYN : 0));
355 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
356 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
357 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
359 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
360 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
361 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
363 * The DC and PM bits are only used if the SSI is the clock master.
367 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
368 * use FIFO 1. We program the transmit water to signal a DMA transfer
369 * if there are only two (or fewer) elements left in the FIFO. Two
370 * elements equals one frame (left channel, right channel). This value,
371 * however, depends on the depth of the transmit buffer.
373 * We set the watermark on the same level as the DMA burstsize. For
374 * fiq it is probably better to use the biggest possible watermark
377 if (ssi_private->use_dma)
378 wm = ssi_private->fifo_depth - 2;
380 wm = ssi_private->fifo_depth;
382 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
383 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
387 * For ac97 interrupts are enabled with the startup of the substream
388 * because it is also running without an active substream. Normally SSI
389 * is only enabled when there is a substream.
391 if (ssi_private->imx_ac97) {
393 * Setup the clock control register
395 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
397 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
401 * Enable AC97 mode and startup the SSI
403 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
405 write_ssi(0xff, &ssi->saccdis);
406 write_ssi(0x300, &ssi->saccen);
409 * Enable SSI, Transmit and Receive
411 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
412 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
414 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
417 if (ssi_private->use_dual_fifo) {
418 write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
419 write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
420 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
428 * fsl_ssi_startup: create a new substream
430 * This is the first function called when a stream is opened.
432 * If this is the first stream open, then grab the IRQ and program most of
435 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
436 struct snd_soc_dai *dai)
438 struct snd_soc_pcm_runtime *rtd = substream->private_data;
439 struct fsl_ssi_private *ssi_private =
440 snd_soc_dai_get_drvdata(rtd->cpu_dai);
441 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
444 * If this is the first stream opened, then request the IRQ
445 * and initialize the SSI registers.
447 if (!ssi_private->first_stream) {
448 ssi_private->first_stream = substream;
451 * fsl_ssi_setup was already called by ac97_init earlier if
452 * the driver is in ac97 mode.
454 if (!ssi_private->imx_ac97)
455 fsl_ssi_setup(ssi_private);
458 struct snd_pcm_runtime *first_runtime =
459 ssi_private->first_stream->runtime;
461 * This is the second stream open, and we're in
462 * synchronous mode, so we need to impose sample
463 * sample size constraints. This is because STCCR is
464 * used for playback and capture in synchronous mode,
465 * so there's no way to specify different word
468 * Note that this can cause a race condition if the
469 * second stream is opened before the first stream is
470 * fully initialized. We provide some protection by
471 * checking to make sure the first stream is
472 * initialized, but it's not perfect. ALSA sometimes
473 * re-initializes the driver with a different sample
474 * rate or size. If the second stream is opened
475 * before the first stream has received its final
476 * parameters, then the second stream may be
477 * constrained to the wrong sample rate or size.
479 if (first_runtime->sample_bits) {
480 snd_pcm_hw_constraint_minmax(substream->runtime,
481 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
482 first_runtime->sample_bits,
483 first_runtime->sample_bits);
487 ssi_private->second_stream = substream;
490 /* When using dual fifo mode, it is safer to ensure an even period
491 * size. If appearing to an odd number while DMA always starts its
492 * task from fifo0, fifo1 would be neglected at the end of each
493 * period. But SSI would still access fifo1 with an invalid data.
495 if (ssi_private->use_dual_fifo)
496 snd_pcm_hw_constraint_step(substream->runtime, 0,
497 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
503 * fsl_ssi_hw_params - program the sample size
505 * Most of the SSI registers have been programmed in the startup function,
506 * but the word length must be programmed here. Unfortunately, programming
507 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
508 * cause a problem with supporting simultaneous playback and capture. If
509 * the SSI is already playing a stream, then that stream may be temporarily
510 * stopped when you start capture.
512 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
515 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
516 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
518 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
519 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
520 unsigned int sample_size =
521 snd_pcm_format_width(params_format(hw_params));
522 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
523 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
526 * If we're in synchronous mode, and the SSI is already enabled,
527 * then STCCR is already set properly.
529 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
533 * FIXME: The documentation says that SxCCR[WL] should not be
534 * modified while the SSI is enabled. The only time this can
535 * happen is if we're trying to do simultaneous playback and
536 * capture in asynchronous mode. Unfortunately, I have been enable
537 * to get that to work at all on the P1022DS. Therefore, we don't
538 * bother to disable/enable the SSI when setting SxCCR[WL], because
539 * the SSI will stop anyway. Maybe one day, this will get fixed.
542 /* In synchronous mode, the SSI uses STCCR for capture */
543 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
544 ssi_private->cpu_dai_drv.symmetric_rates)
545 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
547 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
553 * fsl_ssi_trigger: start and stop the DMA transfer.
555 * This function is called by ALSA to start, stop, pause, and resume the DMA
558 * The DMA channel is in external master start and pause mode, which
559 * means the SSI completely controls the flow of data.
561 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
562 struct snd_soc_dai *dai)
564 struct snd_soc_pcm_runtime *rtd = substream->private_data;
565 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
566 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
567 unsigned int sier_bits;
570 * Enable only the interrupts and DMA requests
571 * that are needed for the channel. As the fiq
572 * is polling for this bits, we have to ensure
573 * that this are aligned with the preallocated
577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
578 if (ssi_private->use_dma)
579 sier_bits = SIER_FLAGS;
581 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
583 if (ssi_private->use_dma)
584 sier_bits = SIER_FLAGS;
586 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
590 case SNDRV_PCM_TRIGGER_START:
591 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
592 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
593 write_ssi_mask(&ssi->scr, 0,
594 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
596 write_ssi_mask(&ssi->scr, 0,
597 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
600 case SNDRV_PCM_TRIGGER_STOP:
601 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
602 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
603 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
605 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
607 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
608 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
609 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
616 write_ssi(sier_bits, &ssi->sier);
622 * fsl_ssi_shutdown: shutdown the SSI
624 * Shutdown the SSI if there are no other substreams open.
626 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
627 struct snd_soc_dai *dai)
629 struct snd_soc_pcm_runtime *rtd = substream->private_data;
630 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
632 if (ssi_private->first_stream == substream)
633 ssi_private->first_stream = ssi_private->second_stream;
635 ssi_private->second_stream = NULL;
638 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
640 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
642 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
643 dai->playback_dma_data = &ssi_private->dma_params_tx;
644 dai->capture_dma_data = &ssi_private->dma_params_rx;
650 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
651 .startup = fsl_ssi_startup,
652 .hw_params = fsl_ssi_hw_params,
653 .shutdown = fsl_ssi_shutdown,
654 .trigger = fsl_ssi_trigger,
657 /* Template for the CPU dai driver structure */
658 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
659 .probe = fsl_ssi_dai_probe,
661 /* The SSI does not support monaural audio. */
664 .rates = FSLSSI_I2S_RATES,
665 .formats = FSLSSI_I2S_FORMATS,
670 .rates = FSLSSI_I2S_RATES,
671 .formats = FSLSSI_I2S_FORMATS,
673 .ops = &fsl_ssi_dai_ops,
676 static const struct snd_soc_component_driver fsl_ssi_component = {
681 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
683 * This function is called by ALSA to start, stop, pause, and resume the
686 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
687 struct snd_soc_dai *dai)
689 struct snd_soc_pcm_runtime *rtd = substream->private_data;
690 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
692 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
695 case SNDRV_PCM_TRIGGER_START:
696 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
697 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
698 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
699 CCSR_SSI_SIER_TFE0_EN);
701 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
702 CCSR_SSI_SIER_RFF0_EN);
705 case SNDRV_PCM_TRIGGER_STOP:
706 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
707 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
708 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
709 CCSR_SSI_SIER_TFE0_EN, 0);
711 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
712 CCSR_SSI_SIER_RFF0_EN, 0);
719 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
720 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
722 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
727 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
728 .startup = fsl_ssi_startup,
729 .shutdown = fsl_ssi_shutdown,
730 .trigger = fsl_ssi_ac97_trigger,
733 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
736 .stream_name = "AC97 Playback",
739 .rates = SNDRV_PCM_RATE_8000_48000,
740 .formats = SNDRV_PCM_FMTBIT_S16_LE,
743 .stream_name = "AC97 Capture",
746 .rates = SNDRV_PCM_RATE_48000,
747 .formats = SNDRV_PCM_FMTBIT_S16_LE,
749 .ops = &fsl_ssi_ac97_dai_ops,
753 static struct fsl_ssi_private *fsl_ac97_data;
755 static void fsl_ssi_ac97_init(void)
757 fsl_ssi_setup(fsl_ac97_data);
760 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
763 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
772 write_ssi(lreg, &ssi->sacadd);
775 write_ssi(lval , &ssi->sacdat);
777 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
782 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
785 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
787 unsigned short val = -1;
790 lreg = (reg & 0x7f) << 12;
791 write_ssi(lreg, &ssi->sacadd);
792 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
797 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
802 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
803 .read = fsl_ssi_ac97_read,
804 .write = fsl_ssi_ac97_write,
807 /* Show the statistics of a flag only if its interrupt is enabled. The
808 * compiler will optimze this code to a no-op if the interrupt is not
811 #define SIER_SHOW(flag, name) \
813 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
814 length += sprintf(buf + length, #name "=%u\n", \
815 ssi_private->stats.name); \
820 * fsl_sysfs_ssi_show: display SSI statistics
822 * Display the statistics for the current SSI device. To avoid confusion,
823 * we only show those counts that are enabled.
825 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
826 struct device_attribute *attr, char *buf)
828 struct fsl_ssi_private *ssi_private =
829 container_of(attr, struct fsl_ssi_private, dev_attr);
832 SIER_SHOW(RFRC_EN, rfrc);
833 SIER_SHOW(TFRC_EN, tfrc);
834 SIER_SHOW(CMDAU_EN, cmdau);
835 SIER_SHOW(CMDDU_EN, cmddu);
836 SIER_SHOW(RXT_EN, rxt);
837 SIER_SHOW(RDR1_EN, rdr1);
838 SIER_SHOW(RDR0_EN, rdr0);
839 SIER_SHOW(TDE1_EN, tde1);
840 SIER_SHOW(TDE0_EN, tde0);
841 SIER_SHOW(ROE1_EN, roe1);
842 SIER_SHOW(ROE0_EN, roe0);
843 SIER_SHOW(TUE1_EN, tue1);
844 SIER_SHOW(TUE0_EN, tue0);
845 SIER_SHOW(TFS_EN, tfs);
846 SIER_SHOW(RFS_EN, rfs);
847 SIER_SHOW(TLS_EN, tls);
848 SIER_SHOW(RLS_EN, rls);
849 SIER_SHOW(RFF1_EN, rff1);
850 SIER_SHOW(RFF0_EN, rff0);
851 SIER_SHOW(TFE1_EN, tfe1);
852 SIER_SHOW(TFE0_EN, tfe0);
858 * Make every character in a string lower-case
860 static void make_lowercase(char *s)
866 if ((c >= 'A') && (c <= 'Z'))
867 *p = c + ('a' - 'A');
872 static int fsl_ssi_probe(struct platform_device *pdev)
874 struct fsl_ssi_private *ssi_private;
876 struct device_attribute *dev_attr = NULL;
877 struct device_node *np = pdev->dev.of_node;
878 const char *p, *sprop;
879 const uint32_t *iprop;
885 /* SSIs that are not connected on the board should have a
886 * status = "disabled"
887 * property in their device tree nodes.
889 if (!of_device_is_available(np))
892 /* We only support the SSI in "I2S Slave" mode */
893 sprop = of_get_property(np, "fsl,mode", NULL);
895 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
898 if (!strcmp(sprop, "ac97-slave")) {
900 } else if (strcmp(sprop, "i2s-slave")) {
901 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
905 /* The DAI name is the last part of the full name of the node. */
906 p = strrchr(np->full_name, '/') + 1;
907 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
910 dev_err(&pdev->dev, "could not allocate DAI object\n");
914 strcpy(ssi_private->name, p);
916 ssi_private->use_dma = !of_property_read_bool(np,
917 "fsl,fiq-stream-filter");
920 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
921 sizeof(fsl_ssi_ac97_dai));
923 fsl_ac97_data = ssi_private;
924 ssi_private->imx_ac97 = true;
926 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
928 /* Initialize this copy of the CPU DAI driver structure */
929 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
930 sizeof(fsl_ssi_dai_template));
932 ssi_private->cpu_dai_drv.name = ssi_private->name;
934 /* Get the addresses and IRQ */
935 ret = of_address_to_resource(np, 0, &res);
937 dev_err(&pdev->dev, "could not determine device resources\n");
940 ssi_private->ssi = of_iomap(np, 0);
941 if (!ssi_private->ssi) {
942 dev_err(&pdev->dev, "could not map device resources\n");
945 ssi_private->ssi_phys = res.start;
947 ssi_private->irq = irq_of_parse_and_map(np, 0);
948 if (!ssi_private->irq) {
949 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
953 /* Are the RX and the TX clocks locked? */
954 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
955 ssi_private->cpu_dai_drv.symmetric_rates = 1;
957 /* Determine the FIFO depth. */
958 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
960 ssi_private->fifo_depth = be32_to_cpup(iprop);
962 /* Older 8610 DTs didn't have the fifo-depth property */
963 ssi_private->fifo_depth = 8;
965 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
966 u32 dma_events[2], dmas[4];
967 ssi_private->ssi_on_imx = true;
969 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
970 if (IS_ERR(ssi_private->clk)) {
971 ret = PTR_ERR(ssi_private->clk);
972 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
975 ret = clk_prepare_enable(ssi_private->clk);
977 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
983 * We have burstsize be "fifo_depth - 2" to match the SSI
984 * watermark setting in fsl_ssi_startup().
986 ssi_private->dma_params_tx.maxburst =
987 ssi_private->fifo_depth - 2;
988 ssi_private->dma_params_rx.maxburst =
989 ssi_private->fifo_depth - 2;
990 ssi_private->dma_params_tx.addr =
991 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
992 ssi_private->dma_params_rx.addr =
993 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
994 ssi_private->dma_params_tx.filter_data =
995 &ssi_private->filter_data_tx;
996 ssi_private->dma_params_rx.filter_data =
997 &ssi_private->filter_data_rx;
998 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
999 ssi_private->use_dma) {
1001 * FIXME: This is a temporary solution until all
1002 * necessary dma drivers support the generic dma
1005 ret = of_property_read_u32_array(pdev->dev.of_node,
1006 "fsl,ssi-dma-events", dma_events, 2);
1007 if (ret && ssi_private->use_dma) {
1008 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1013 shared = of_device_is_compatible(of_get_parent(np),
1016 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1017 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1018 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1019 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1020 if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
1021 && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1022 ssi_private->use_dual_fifo = true;
1023 /* When using dual fifo mode, we need to keep watermark
1024 * as even numbers due to dma script limitation.
1026 ssi_private->dma_params_tx.maxburst &= ~0x1;
1027 ssi_private->dma_params_rx.maxburst &= ~0x1;
1029 } else if (ssi_private->use_dma) {
1030 /* The 'name' should not have any slashes in it. */
1031 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1032 fsl_ssi_isr, 0, ssi_private->name,
1035 dev_err(&pdev->dev, "could not claim irq %u\n",
1041 /* Initialize the the device_attribute structure */
1042 dev_attr = &ssi_private->dev_attr;
1043 sysfs_attr_init(&dev_attr->attr);
1044 dev_attr->attr.name = "statistics";
1045 dev_attr->attr.mode = S_IRUGO;
1046 dev_attr->show = fsl_sysfs_ssi_show;
1048 ret = device_create_file(&pdev->dev, dev_attr);
1050 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1051 ssi_private->dev_attr.attr.name);
1055 /* Register with ASoC */
1056 dev_set_drvdata(&pdev->dev, ssi_private);
1058 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1059 &ssi_private->cpu_dai_drv, 1);
1061 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1065 if (ssi_private->ssi_on_imx) {
1066 if (!ssi_private->use_dma) {
1069 * Some boards use an incompatible codec. To get it
1070 * working, we are using imx-fiq-pcm-audio, that
1071 * can handle those codecs. DMA is not possible in this
1075 ssi_private->fiq_params.irq = ssi_private->irq;
1076 ssi_private->fiq_params.base = ssi_private->ssi;
1077 ssi_private->fiq_params.dma_params_rx =
1078 &ssi_private->dma_params_rx;
1079 ssi_private->fiq_params.dma_params_tx =
1080 &ssi_private->dma_params_tx;
1082 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1086 ret = imx_pcm_dma_init(pdev);
1093 * If codec-handle property is missing from SSI node, we assume
1094 * that the machine driver uses new binding which does not require
1095 * SSI driver to trigger machine driver's probe.
1097 if (!of_get_property(np, "codec-handle", NULL)) {
1098 ssi_private->new_binding = true;
1102 /* Trigger the machine driver's probe function. The platform driver
1103 * name of the machine driver is taken from /compatible property of the
1104 * device tree. We also pass the address of the CPU DAI driver
1107 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1108 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1109 p = strrchr(sprop, ',');
1112 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1113 make_lowercase(name);
1116 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1117 if (IS_ERR(ssi_private->pdev)) {
1118 ret = PTR_ERR(ssi_private->pdev);
1119 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1124 if (ssi_private->imx_ac97)
1125 fsl_ssi_ac97_init();
1130 if (ssi_private->ssi_on_imx)
1131 imx_pcm_dma_exit(pdev);
1132 snd_soc_unregister_component(&pdev->dev);
1135 device_remove_file(&pdev->dev, dev_attr);
1138 if (ssi_private->ssi_on_imx)
1139 clk_disable_unprepare(ssi_private->clk);
1142 irq_dispose_mapping(ssi_private->irq);
1147 static int fsl_ssi_remove(struct platform_device *pdev)
1149 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1151 if (!ssi_private->new_binding)
1152 platform_device_unregister(ssi_private->pdev);
1153 if (ssi_private->ssi_on_imx)
1154 imx_pcm_dma_exit(pdev);
1155 snd_soc_unregister_component(&pdev->dev);
1156 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1157 if (ssi_private->ssi_on_imx)
1158 clk_disable_unprepare(ssi_private->clk);
1159 irq_dispose_mapping(ssi_private->irq);
1164 static const struct of_device_id fsl_ssi_ids[] = {
1165 { .compatible = "fsl,mpc8610-ssi", },
1166 { .compatible = "fsl,imx21-ssi", },
1169 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1171 static struct platform_driver fsl_ssi_driver = {
1173 .name = "fsl-ssi-dai",
1174 .owner = THIS_MODULE,
1175 .of_match_table = fsl_ssi_ids,
1177 .probe = fsl_ssi_probe,
1178 .remove = fsl_ssi_remove,
1181 module_platform_driver(fsl_ssi_driver);
1183 MODULE_ALIAS("platform:fsl-ssi-dai");
1184 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1185 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1186 MODULE_LICENSE("GPL v2");