2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
69 u32 val = readl(addr);
70 val = (val & ~clear) | set;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
110 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
111 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
112 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
113 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
114 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
123 struct fsl_ssi_reg_val {
130 struct fsl_ssi_rxtx_reg_val {
131 struct fsl_ssi_reg_val rx;
132 struct fsl_ssi_reg_val tx;
135 struct fsl_ssi_soc_data {
142 * fsl_ssi_private: per-SSI private data
144 * @ssi: pointer to the SSI's registers
145 * @ssi_phys: physical address of the SSI registers
146 * @irq: IRQ of this SSI
147 * @playback: the number of playback streams opened
148 * @capture: the number of capture streams opened
149 * @cpu_dai: the CPU DAI for this device
150 * @dev_attr: the sysfs device attribute structure
151 * @stats: SSI statistics
153 struct fsl_ssi_private {
154 struct ccsr_ssi __iomem *ssi;
157 unsigned int fifo_depth;
158 struct snd_soc_dai_driver cpu_dai_drv;
159 struct platform_device *pdev;
160 unsigned int dai_fmt;
168 unsigned int bitclk_freq;
169 struct snd_dmaengine_dai_dma_data dma_params_tx;
170 struct snd_dmaengine_dai_dma_data dma_params_rx;
171 struct imx_pcm_fiq_params fiq_params;
172 /* Register values for rx/tx configuration */
173 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
175 struct fsl_ssi_dbg dbg_stats;
177 const struct fsl_ssi_soc_data *soc;
181 * imx51 and later SoCs have a slightly different IP that allows the
182 * SSI configuration while the SSI unit is running.
184 * More important, it is necessary on those SoCs to configure the
185 * sperate TX/RX DMA bits just before starting the stream
186 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
187 * sends any DMA requests to the SDMA unit, otherwise it is not defined
188 * how the SDMA unit handles the DMA request.
190 * SDMA units are present on devices starting at imx35 but the imx35
191 * reference manual states that the DMA bits should not be changed
192 * while the SSI unit is running (SSIEN). So we support the necessary
193 * online configuration of fsl-ssi starting at imx51.
196 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
198 .offline_config = true,
199 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
200 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
201 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
204 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
206 .offline_config = true,
207 .sisr_write_mask = 0,
210 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
212 .offline_config = true,
213 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
214 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
215 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
218 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
220 .offline_config = false,
221 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
222 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
225 static const struct of_device_id fsl_ssi_ids[] = {
226 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
227 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
228 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
229 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
232 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
234 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
236 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
239 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
241 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
242 SND_SOC_DAIFMT_CBS_CFS;
246 * fsl_ssi_isr: SSI interrupt handler
248 * Although it's possible to use the interrupt handler to send and receive
249 * data to/from the SSI, we use the DMA instead. Programming is more
250 * complicated, but the performance is much better.
252 * This interrupt handler is used only to gather statistics.
254 * @irq: IRQ of the SSI device
255 * @dev_id: pointer to the ssi_private structure for this SSI device
257 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
259 struct fsl_ssi_private *ssi_private = dev_id;
260 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
264 /* We got an interrupt, so read the status register to see what we
265 were interrupted for. We mask it with the Interrupt Enable register
266 so that we only check for events that we're interested in.
268 sisr = read_ssi(&ssi->sisr);
270 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
271 /* Clear the bits that we set */
273 write_ssi(sisr2, &ssi->sisr);
275 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
281 * Enable/Disable all rx/tx config flags at once.
283 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
286 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
287 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
290 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
291 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
292 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
294 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
295 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
296 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
301 * Calculate the bits that have to be disabled for the current stream that is
302 * getting disabled. This keeps the bits enabled that are necessary for the
303 * second stream to work if 'stream_active' is true.
305 * Detailed calculation:
306 * These are the values that need to be active after disabling. For non-active
307 * second stream, this is 0:
308 * vals_stream * !!stream_active
310 * The following computes the overall differences between the setup for the
311 * to-disable stream and the active stream, a simple XOR:
312 * vals_disable ^ (vals_stream * !!(stream_active))
314 * The full expression adds a mask on all values we care about
316 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
318 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
321 * Enable/Disable a ssi configuration. You have to pass either
322 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
324 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
325 struct fsl_ssi_reg_val *vals)
327 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
328 struct fsl_ssi_reg_val *avals;
329 u32 scr_val = read_ssi(&ssi->scr);
330 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
331 !!(scr_val & CCSR_SSI_SCR_RE);
334 if (nr_active_streams - 1 > 0)
339 /* Find the other direction values rx or tx which we do not want to
341 if (&ssi_private->rxtx_reg_val.rx == vals)
342 avals = &ssi_private->rxtx_reg_val.tx;
344 avals = &ssi_private->rxtx_reg_val.rx;
346 /* If vals should be disabled, start with disabling the unit */
348 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
350 write_ssi_mask(&ssi->scr, scr, 0);
354 * We are running on a SoC which does not support online SSI
355 * reconfiguration, so we have to enable all necessary flags at once
356 * even if we do not use them later (capture and playback configuration)
358 if (ssi_private->soc->offline_config) {
359 if ((enable && !nr_active_streams) ||
360 (!enable && !keep_active))
361 fsl_ssi_rxtx_config(ssi_private, enable);
367 * Configure single direction units while the SSI unit is running
368 * (online configuration)
371 write_ssi_mask(&ssi->sier, 0, vals->sier);
372 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
373 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
380 * Disabling the necessary flags for one of rx/tx while the
381 * other stream is active is a little bit more difficult. We
382 * have to disable only those flags that differ between both
383 * streams (rx XOR tx) and that are set in the stream that is
384 * disabled now. Otherwise we could alter flags of the other
388 /* These assignments are simply vals without bits set in avals*/
389 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
391 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
393 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
396 write_ssi_mask(&ssi->srcr, srcr, 0);
397 write_ssi_mask(&ssi->stcr, stcr, 0);
398 write_ssi_mask(&ssi->sier, sier, 0);
402 /* Enabling of subunits is done after configuration */
404 write_ssi_mask(&ssi->scr, 0, vals->scr);
408 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
410 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
413 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
415 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
419 * Setup rx/tx register values used to enable/disable the streams. These will
420 * be used later in fsl_ssi_config to setup the streams without the need to
421 * check for all different SSI modes.
423 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
425 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
427 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
428 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
430 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
431 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
434 if (!fsl_ssi_is_ac97(ssi_private)) {
435 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
436 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
437 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
438 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
441 if (ssi_private->use_dma) {
442 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
443 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
445 reg->rx.sier |= CCSR_SSI_SIER_RIE;
446 reg->tx.sier |= CCSR_SSI_SIER_TIE;
449 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
450 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
453 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
455 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
458 * Setup the clock control register
460 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
462 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
466 * Enable AC97 mode and startup the SSI
468 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
470 write_ssi(0xff, &ssi->saccdis);
471 write_ssi(0x300, &ssi->saccen);
474 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
475 * codec before a stream is started.
477 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
478 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
480 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
484 * fsl_ssi_startup: create a new substream
486 * This is the first function called when a stream is opened.
488 * If this is the first stream open, then grab the IRQ and program most of
491 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
492 struct snd_soc_dai *dai)
494 struct snd_soc_pcm_runtime *rtd = substream->private_data;
495 struct fsl_ssi_private *ssi_private =
496 snd_soc_dai_get_drvdata(rtd->cpu_dai);
498 if (!dai->active && !fsl_ssi_is_ac97(ssi_private))
499 ssi_private->baudclk_locked = false;
501 /* When using dual fifo mode, it is safer to ensure an even period
502 * size. If appearing to an odd number while DMA always starts its
503 * task from fifo0, fifo1 would be neglected at the end of each
504 * period. But SSI would still access fifo1 with an invalid data.
506 if (ssi_private->use_dual_fifo)
507 snd_pcm_hw_constraint_step(substream->runtime, 0,
508 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
514 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
516 * Note: This function can be only called when using SSI as DAI master
518 * Quick instruction for parameters:
519 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
520 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
522 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *cpu_dai,
524 struct snd_pcm_hw_params *hw_params)
526 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
527 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
528 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
529 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
530 unsigned long clkrate, baudrate, tmprate;
531 u64 sub, savesub = 100000;
534 /* Prefer the explicitly set bitclock frequency */
535 if (ssi_private->bitclk_freq)
536 freq = ssi_private->bitclk_freq;
538 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
540 /* Don't apply it to any non-baudclk circumstance */
541 if (IS_ERR(ssi_private->baudclk))
544 /* It should be already enough to divide clock by setting pm alone */
548 factor = (div2 + 1) * (7 * psr + 1) * 2;
550 for (i = 0; i < 255; i++) {
551 /* The bclk rate must be smaller than 1/5 sysclk rate */
552 if (factor * (i + 1) < 5)
555 tmprate = freq * factor * (i + 2);
556 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
558 do_div(clkrate, factor);
559 afreq = (u32)clkrate / (i + 1);
563 else if (freq / afreq == 1)
565 else if (afreq / freq == 1)
570 /* Calculate the fraction */
585 /* No proper pm found if it is still remaining the initial value */
587 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
591 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
592 (psr ? CCSR_SSI_SxCCR_PSR : 0);
593 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
597 write_ssi_mask(&ssi->stccr, mask, stccr);
599 write_ssi_mask(&ssi->srccr, mask, stccr);
601 if (!ssi_private->baudclk_locked) {
602 ret = clk_set_rate(ssi_private->baudclk, baudrate);
604 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
607 ssi_private->baudclk_locked = true;
613 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
614 int clk_id, unsigned int freq, int dir)
616 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
618 ssi_private->bitclk_freq = freq;
624 * fsl_ssi_hw_params - program the sample size
626 * Most of the SSI registers have been programmed in the startup function,
627 * but the word length must be programmed here. Unfortunately, programming
628 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
629 * cause a problem with supporting simultaneous playback and capture. If
630 * the SSI is already playing a stream, then that stream may be temporarily
631 * stopped when you start capture.
633 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
636 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
637 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
639 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
640 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
641 unsigned int channels = params_channels(hw_params);
642 unsigned int sample_size =
643 snd_pcm_format_width(params_format(hw_params));
644 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
645 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
649 * If we're in synchronous mode, and the SSI is already enabled,
650 * then STCCR is already set properly.
652 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
655 if (fsl_ssi_is_i2s_master(ssi_private)) {
656 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
662 * FIXME: The documentation says that SxCCR[WL] should not be
663 * modified while the SSI is enabled. The only time this can
664 * happen is if we're trying to do simultaneous playback and
665 * capture in asynchronous mode. Unfortunately, I have been enable
666 * to get that to work at all on the P1022DS. Therefore, we don't
667 * bother to disable/enable the SSI when setting SxCCR[WL], because
668 * the SSI will stop anyway. Maybe one day, this will get fixed.
671 /* In synchronous mode, the SSI uses STCCR for capture */
672 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
673 ssi_private->cpu_dai_drv.symmetric_rates)
674 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
676 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
678 if (!fsl_ssi_is_ac97(ssi_private))
679 write_ssi_mask(&ssi->scr,
680 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
681 channels == 1 ? 0 : ssi_private->i2s_mode);
686 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
689 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
690 u32 strcr = 0, stcr, srcr, scr, mask;
693 ssi_private->dai_fmt = fmt;
695 fsl_ssi_setup_reg_vals(ssi_private);
697 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
698 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
700 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
701 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
703 stcr = read_ssi(&ssi->stcr) & ~mask;
704 srcr = read_ssi(&ssi->srcr) & ~mask;
706 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
707 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
708 case SND_SOC_DAIFMT_I2S:
709 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
710 case SND_SOC_DAIFMT_CBS_CFS:
711 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
713 case SND_SOC_DAIFMT_CBM_CFM:
714 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
720 /* Data on rising edge of bclk, frame low, 1clk before data */
721 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
722 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
724 case SND_SOC_DAIFMT_LEFT_J:
725 /* Data on rising edge of bclk, frame high */
726 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
728 case SND_SOC_DAIFMT_DSP_A:
729 /* Data on rising edge of bclk, frame high, 1clk before data */
730 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
731 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
733 case SND_SOC_DAIFMT_DSP_B:
734 /* Data on rising edge of bclk, frame high */
735 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
736 CCSR_SSI_STCR_TXBIT0;
738 case SND_SOC_DAIFMT_AC97:
739 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
744 scr |= ssi_private->i2s_mode;
746 /* DAI clock inversion */
747 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
748 case SND_SOC_DAIFMT_NB_NF:
749 /* Nothing to do for both normal cases */
751 case SND_SOC_DAIFMT_IB_NF:
752 /* Invert bit clock */
753 strcr ^= CCSR_SSI_STCR_TSCKP;
755 case SND_SOC_DAIFMT_NB_IF:
756 /* Invert frame clock */
757 strcr ^= CCSR_SSI_STCR_TFSI;
759 case SND_SOC_DAIFMT_IB_IF:
760 /* Invert both clocks */
761 strcr ^= CCSR_SSI_STCR_TSCKP;
762 strcr ^= CCSR_SSI_STCR_TFSI;
768 /* DAI clock master masks */
769 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
770 case SND_SOC_DAIFMT_CBS_CFS:
771 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
772 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
774 case SND_SOC_DAIFMT_CBM_CFM:
775 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
784 if (ssi_private->cpu_dai_drv.symmetric_rates) {
785 /* Need to clear RXDIR when using SYNC mode */
786 srcr &= ~CCSR_SSI_SRCR_RXDIR;
787 scr |= CCSR_SSI_SCR_SYN;
790 write_ssi(stcr, &ssi->stcr);
791 write_ssi(srcr, &ssi->srcr);
792 write_ssi(scr, &ssi->scr);
795 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
796 * use FIFO 1. We program the transmit water to signal a DMA transfer
797 * if there are only two (or fewer) elements left in the FIFO. Two
798 * elements equals one frame (left channel, right channel). This value,
799 * however, depends on the depth of the transmit buffer.
801 * We set the watermark on the same level as the DMA burstsize. For
802 * fiq it is probably better to use the biggest possible watermark
805 if (ssi_private->use_dma)
806 wm = ssi_private->fifo_depth - 2;
808 wm = ssi_private->fifo_depth;
810 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
811 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
814 if (ssi_private->use_dual_fifo) {
815 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
816 CCSR_SSI_SRCR_RFEN1);
817 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
818 CCSR_SSI_STCR_TFEN1);
819 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
820 CCSR_SSI_SCR_TCH_EN);
823 if (fmt & SND_SOC_DAIFMT_AC97)
824 fsl_ssi_setup_ac97(ssi_private);
831 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
833 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
835 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
837 return _fsl_ssi_set_dai_fmt(ssi_private, fmt);
841 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
843 * Note: This function can be only called when using SSI as DAI master
845 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
846 u32 rx_mask, int slots, int slot_width)
848 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
849 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
852 /* The slot number should be >= 2 if using Network mode or I2S mode */
853 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
854 if (val && slots < 2) {
855 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
859 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
860 CCSR_SSI_SxCCR_DC(slots));
861 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
862 CCSR_SSI_SxCCR_DC(slots));
864 /* The register SxMSKs needs SSI to provide essential clock due to
865 * hardware design. So we here temporarily enable SSI to set them.
867 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
868 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
870 write_ssi(tx_mask, &ssi->stmsk);
871 write_ssi(rx_mask, &ssi->srmsk);
873 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
879 * fsl_ssi_trigger: start and stop the DMA transfer.
881 * This function is called by ALSA to start, stop, pause, and resume the DMA
884 * The DMA channel is in external master start and pause mode, which
885 * means the SSI completely controls the flow of data.
887 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
888 struct snd_soc_dai *dai)
890 struct snd_soc_pcm_runtime *rtd = substream->private_data;
891 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
892 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
895 case SNDRV_PCM_TRIGGER_START:
896 case SNDRV_PCM_TRIGGER_RESUME:
897 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
898 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
899 fsl_ssi_tx_config(ssi_private, true);
901 fsl_ssi_rx_config(ssi_private, true);
904 case SNDRV_PCM_TRIGGER_STOP:
905 case SNDRV_PCM_TRIGGER_SUSPEND:
906 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
907 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
908 fsl_ssi_tx_config(ssi_private, false);
910 fsl_ssi_rx_config(ssi_private, false);
912 if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) &
913 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
914 ssi_private->baudclk_locked = false;
922 if (fsl_ssi_is_ac97(ssi_private)) {
923 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
924 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
926 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
932 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
934 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
936 if (ssi_private->soc->imx && ssi_private->use_dma) {
937 dai->playback_dma_data = &ssi_private->dma_params_tx;
938 dai->capture_dma_data = &ssi_private->dma_params_rx;
944 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
945 .startup = fsl_ssi_startup,
946 .hw_params = fsl_ssi_hw_params,
947 .set_fmt = fsl_ssi_set_dai_fmt,
948 .set_sysclk = fsl_ssi_set_dai_sysclk,
949 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
950 .trigger = fsl_ssi_trigger,
953 /* Template for the CPU dai driver structure */
954 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
955 .probe = fsl_ssi_dai_probe,
959 .rates = FSLSSI_I2S_RATES,
960 .formats = FSLSSI_I2S_FORMATS,
965 .rates = FSLSSI_I2S_RATES,
966 .formats = FSLSSI_I2S_FORMATS,
968 .ops = &fsl_ssi_dai_ops,
971 static const struct snd_soc_component_driver fsl_ssi_component = {
975 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
978 .stream_name = "AC97 Playback",
981 .rates = SNDRV_PCM_RATE_8000_48000,
982 .formats = SNDRV_PCM_FMTBIT_S16_LE,
985 .stream_name = "AC97 Capture",
988 .rates = SNDRV_PCM_RATE_48000,
989 .formats = SNDRV_PCM_FMTBIT_S16_LE,
991 .ops = &fsl_ssi_dai_ops,
995 static struct fsl_ssi_private *fsl_ac97_data;
997 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1000 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1009 write_ssi(lreg, &ssi->sacadd);
1012 write_ssi(lval , &ssi->sacdat);
1014 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1019 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1022 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1024 unsigned short val = -1;
1027 lreg = (reg & 0x7f) << 12;
1028 write_ssi(lreg, &ssi->sacadd);
1029 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1034 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1039 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1040 .read = fsl_ssi_ac97_read,
1041 .write = fsl_ssi_ac97_write,
1045 * Make every character in a string lower-case
1047 static void make_lowercase(char *s)
1053 if ((c >= 'A') && (c <= 'Z'))
1054 *p = c + ('a' - 'A');
1059 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1060 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1062 struct device_node *np = pdev->dev.of_node;
1066 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1067 if (IS_ERR(ssi_private->clk)) {
1068 ret = PTR_ERR(ssi_private->clk);
1069 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1073 ret = clk_prepare_enable(ssi_private->clk);
1075 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1079 /* For those SLAVE implementations, we ingore non-baudclk cases
1080 * and, instead, abandon MASTER mode that needs baud clock.
1082 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1083 if (IS_ERR(ssi_private->baudclk))
1084 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1085 PTR_ERR(ssi_private->baudclk));
1087 clk_prepare_enable(ssi_private->baudclk);
1090 * We have burstsize be "fifo_depth - 2" to match the SSI
1091 * watermark setting in fsl_ssi_startup().
1093 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1094 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1095 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys +
1096 offsetof(struct ccsr_ssi, stx0);
1097 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys +
1098 offsetof(struct ccsr_ssi, srx0);
1100 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1101 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1102 ssi_private->use_dual_fifo = true;
1103 /* When using dual fifo mode, we need to keep watermark
1104 * as even numbers due to dma script limitation.
1106 ssi_private->dma_params_tx.maxburst &= ~0x1;
1107 ssi_private->dma_params_rx.maxburst &= ~0x1;
1110 if (!ssi_private->use_dma) {
1113 * Some boards use an incompatible codec. To get it
1114 * working, we are using imx-fiq-pcm-audio, that
1115 * can handle those codecs. DMA is not possible in this
1119 ssi_private->fiq_params.irq = ssi_private->irq;
1120 ssi_private->fiq_params.base = iomem;
1121 ssi_private->fiq_params.dma_params_rx =
1122 &ssi_private->dma_params_rx;
1123 ssi_private->fiq_params.dma_params_tx =
1124 &ssi_private->dma_params_tx;
1126 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1130 ret = imx_pcm_dma_init(pdev);
1138 if (!IS_ERR(ssi_private->baudclk))
1139 clk_disable_unprepare(ssi_private->baudclk);
1141 clk_disable_unprepare(ssi_private->clk);
1146 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1147 struct fsl_ssi_private *ssi_private)
1149 if (!ssi_private->use_dma)
1150 imx_pcm_fiq_exit(pdev);
1151 if (!IS_ERR(ssi_private->baudclk))
1152 clk_disable_unprepare(ssi_private->baudclk);
1153 clk_disable_unprepare(ssi_private->clk);
1156 static int fsl_ssi_probe(struct platform_device *pdev)
1158 struct fsl_ssi_private *ssi_private;
1160 struct device_node *np = pdev->dev.of_node;
1161 const struct of_device_id *of_id;
1162 const char *p, *sprop;
1163 const uint32_t *iprop;
1164 struct resource res;
1167 /* SSIs that are not connected on the board should have a
1168 * status = "disabled"
1169 * property in their device tree nodes.
1171 if (!of_device_is_available(np))
1174 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1175 if (!of_id || !of_id->data)
1178 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1181 dev_err(&pdev->dev, "could not allocate DAI object\n");
1185 ssi_private->soc = of_id->data;
1187 sprop = of_get_property(np, "fsl,mode", NULL);
1189 if (!strcmp(sprop, "ac97-slave"))
1190 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1191 else if (!strcmp(sprop, "i2s-slave"))
1192 ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S |
1193 SND_SOC_DAIFMT_CBM_CFM;
1196 ssi_private->use_dma = !of_property_read_bool(np,
1197 "fsl,fiq-stream-filter");
1199 if (fsl_ssi_is_ac97(ssi_private)) {
1200 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1201 sizeof(fsl_ssi_ac97_dai));
1203 fsl_ac97_data = ssi_private;
1205 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1207 /* Initialize this copy of the CPU DAI driver structure */
1208 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1209 sizeof(fsl_ssi_dai_template));
1211 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1213 /* Get the addresses and IRQ */
1214 ret = of_address_to_resource(np, 0, &res);
1216 dev_err(&pdev->dev, "could not determine device resources\n");
1219 ssi_private->ssi = of_iomap(np, 0);
1220 if (!ssi_private->ssi) {
1221 dev_err(&pdev->dev, "could not map device resources\n");
1224 ssi_private->ssi_phys = res.start;
1226 ssi_private->irq = irq_of_parse_and_map(np, 0);
1227 if (!ssi_private->irq) {
1228 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1232 /* Are the RX and the TX clocks locked? */
1233 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1234 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1235 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1236 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1239 /* Determine the FIFO depth. */
1240 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1242 ssi_private->fifo_depth = be32_to_cpup(iprop);
1244 /* Older 8610 DTs didn't have the fifo-depth property */
1245 ssi_private->fifo_depth = 8;
1247 ssi_private->baudclk_locked = false;
1249 dev_set_drvdata(&pdev->dev, ssi_private);
1251 if (ssi_private->soc->imx) {
1252 ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi);
1257 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1258 &ssi_private->cpu_dai_drv, 1);
1260 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1261 goto error_asoc_register;
1264 if (ssi_private->use_dma) {
1265 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1266 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1269 dev_err(&pdev->dev, "could not claim irq %u\n",
1275 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1277 goto error_asoc_register;
1280 * If codec-handle property is missing from SSI node, we assume
1281 * that the machine driver uses new binding which does not require
1282 * SSI driver to trigger machine driver's probe.
1284 if (!of_get_property(np, "codec-handle", NULL))
1287 /* Trigger the machine driver's probe function. The platform driver
1288 * name of the machine driver is taken from /compatible property of the
1289 * device tree. We also pass the address of the CPU DAI driver
1292 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1293 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1294 p = strrchr(sprop, ',');
1297 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1298 make_lowercase(name);
1301 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1302 if (IS_ERR(ssi_private->pdev)) {
1303 ret = PTR_ERR(ssi_private->pdev);
1304 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1305 goto error_sound_card;
1309 if (ssi_private->dai_fmt)
1310 _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt);
1315 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1318 snd_soc_unregister_component(&pdev->dev);
1320 error_asoc_register:
1321 if (ssi_private->soc->imx)
1322 fsl_ssi_imx_clean(pdev, ssi_private);
1325 if (ssi_private->use_dma)
1326 irq_dispose_mapping(ssi_private->irq);
1331 static int fsl_ssi_remove(struct platform_device *pdev)
1333 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1335 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1337 if (ssi_private->pdev)
1338 platform_device_unregister(ssi_private->pdev);
1339 snd_soc_unregister_component(&pdev->dev);
1341 if (ssi_private->soc->imx)
1342 fsl_ssi_imx_clean(pdev, ssi_private);
1344 if (ssi_private->use_dma)
1345 irq_dispose_mapping(ssi_private->irq);
1350 static struct platform_driver fsl_ssi_driver = {
1352 .name = "fsl-ssi-dai",
1353 .owner = THIS_MODULE,
1354 .of_match_table = fsl_ssi_ids,
1356 .probe = fsl_ssi_probe,
1357 .remove = fsl_ssi_remove,
1360 module_platform_driver(fsl_ssi_driver);
1362 MODULE_ALIAS("platform:fsl-ssi-dai");
1363 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1364 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1365 MODULE_LICENSE("GPL v2");