2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
22 #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
23 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
24 SNDRV_PCM_FMTBIT_S16_LE | \
25 SNDRV_PCM_FMTBIT_S20_3LE | \
26 SNDRV_PCM_FMTBIT_S24_LE)
29 * fsl_esai: ESAI private data
31 * @dma_params_rx: DMA parameters for receive channel
32 * @dma_params_tx: DMA parameters for transmit channel
33 * @pdev: platform device pointer
34 * @regmap: regmap handler
35 * @coreclk: clock source to access register
36 * @extalclk: esai clock source to derive HCK, SCK and FS
37 * @fsysclk: system clock source to derive HCK, SCK and FS
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @hck_rate: clock rate of desired HCKx clock
41 * @sck_rate: clock rate of desired SCKx clock
42 * @hck_dir: the direction of HCKx pads
43 * @sck_div: if using PSR/PM dividers for SCKx clock
44 * @slave_mode: if fully using DAI slave mode
45 * @synchronous: if using tx/rx synchronous mode
49 struct snd_dmaengine_dai_dma_data dma_params_rx;
50 struct snd_dmaengine_dai_dma_data dma_params_tx;
51 struct platform_device *pdev;
52 struct regmap *regmap;
67 static irqreturn_t esai_isr(int irq, void *devid)
69 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
70 struct platform_device *pdev = esai_priv->pdev;
73 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
75 if (esr & ESAI_ESR_TINIT_MASK)
76 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
78 if (esr & ESAI_ESR_RFF_MASK)
79 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
81 if (esr & ESAI_ESR_TFE_MASK)
82 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
84 if (esr & ESAI_ESR_TLS_MASK)
85 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
87 if (esr & ESAI_ESR_TDE_MASK)
88 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
90 if (esr & ESAI_ESR_TED_MASK)
91 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
93 if (esr & ESAI_ESR_TD_MASK)
94 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
96 if (esr & ESAI_ESR_RLS_MASK)
97 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
99 if (esr & ESAI_ESR_RDE_MASK)
100 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
102 if (esr & ESAI_ESR_RED_MASK)
103 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
105 if (esr & ESAI_ESR_RD_MASK)
106 dev_dbg(&pdev->dev, "isr: Receiving data\n");
112 * This function is used to calculate the divisors of psr, pm, fp and it is
113 * supposed to be called in set_dai_sysclk() and set_bclk().
115 * @ratio: desired overall ratio for the paticipating dividers
116 * @usefp: for HCK setting, there is no need to set fp divider
117 * @fp: bypass other dividers by setting fp directly if fp != 0
118 * @tx: current setting is for playback or capture
120 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
123 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
124 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
126 maxfp = usefp ? 16 : 1;
131 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
132 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
133 2 * 8 * 256 * maxfp);
135 } else if (ratio % 2) {
136 dev_err(dai->dev, "the raio must be even if using upper divider\n");
142 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
144 /* Set the max fluctuation -- 0.1% of the max devisor */
145 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
147 /* Find the best value for PM */
148 for (i = 1; i <= 256; i++) {
149 for (j = 1; j <= maxfp; j++) {
150 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
151 prod = (psr ? 1 : 8) * i * j;
155 else if (prod / ratio == 1)
157 else if (ratio / prod == 1)
162 /* Calculate the fraction */
163 sub = sub * 1000 / ratio;
177 dev_err(dai->dev, "failed to calculate proper divisors\n");
182 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
183 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
184 psr | ESAI_xCCR_xPM(pm));
187 /* Bypass fp if not being required */
191 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
192 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
198 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
201 * clk_id: The clock source of HCKT/HCKR
202 * (Input from outside; output from inside, FSYS or EXTAL)
203 * freq: The required clock rate of HCKT/HCKR
204 * dir: The clock direction of HCKT/HCKR
206 * Note: If the direction is input, we do not care about clk_id.
208 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
209 unsigned int freq, int dir)
211 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
212 struct clk *clksrc = esai_priv->extalclk;
213 bool tx = clk_id <= ESAI_HCKT_EXTAL;
214 bool in = dir == SND_SOC_CLOCK_IN;
216 unsigned long clk_rate;
219 /* Bypass divider settings if the requirement doesn't change */
220 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
223 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
224 esai_priv->sck_div[tx] = true;
226 /* Set the direction of HCKT/HCKR pins */
227 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
228 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
236 clksrc = esai_priv->fsysclk;
238 case ESAI_HCKT_EXTAL:
240 case ESAI_HCKR_EXTAL:
247 if (IS_ERR(clksrc)) {
248 dev_err(dai->dev, "no assigned %s clock\n",
249 clk_id % 2 ? "extal" : "fsys");
250 return PTR_ERR(clksrc);
252 clk_rate = clk_get_rate(clksrc);
254 ratio = clk_rate / freq;
255 if (ratio * freq > clk_rate)
256 ret = ratio * freq - clk_rate;
257 else if (ratio * freq < clk_rate)
258 ret = clk_rate - ratio * freq;
262 /* Block if clock source can not be divided into the required rate */
263 if (ret != 0 && clk_rate / ret < 1000) {
264 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
269 /* Only EXTAL source can be output directly without using PSR and PM */
270 if (ratio == 1 && clksrc == esai_priv->extalclk) {
271 /* Bypass all the dividers if not being needed */
272 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
274 } else if (ratio < 2) {
275 /* The ratio should be no less than 2 if using other sources */
276 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
281 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
285 esai_priv->sck_div[tx] = false;
288 esai_priv->hck_dir[tx] = dir;
289 esai_priv->hck_rate[tx] = freq;
291 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
292 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
293 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
299 * This function configures the related dividers according to the bclk rate
301 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
303 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
304 u32 hck_rate = esai_priv->hck_rate[tx];
305 u32 sub, ratio = hck_rate / freq;
308 /* Don't apply for fully slave mode or unchanged bclk */
309 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
312 if (ratio * freq > hck_rate)
313 sub = ratio * freq - hck_rate;
314 else if (ratio * freq < hck_rate)
315 sub = hck_rate - ratio * freq;
319 /* Block if clock source can not be divided into the required rate */
320 if (sub != 0 && hck_rate / sub < 1000) {
321 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
326 /* The ratio should be contented by FP alone if bypassing PM and PSR */
327 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
328 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
332 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
333 esai_priv->sck_div[tx] ? 0 : ratio);
337 /* Save current bclk rate */
338 esai_priv->sck_rate[tx] = freq;
343 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
344 u32 rx_mask, int slots, int slot_width)
346 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
348 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
349 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
351 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
352 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
353 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
354 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
356 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
357 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
359 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
360 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
361 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
362 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
364 esai_priv->slot_width = slot_width;
369 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
371 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
372 u32 xcr = 0, xccr = 0, mask;
375 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
376 case SND_SOC_DAIFMT_I2S:
377 /* Data on rising edge of bclk, frame low, 1clk before data */
378 xcr |= ESAI_xCR_xFSR;
379 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
381 case SND_SOC_DAIFMT_LEFT_J:
382 /* Data on rising edge of bclk, frame high */
383 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
385 case SND_SOC_DAIFMT_RIGHT_J:
386 /* Data on rising edge of bclk, frame high, right aligned */
387 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
389 case SND_SOC_DAIFMT_DSP_A:
390 /* Data on rising edge of bclk, frame high, 1clk before data */
391 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
392 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
394 case SND_SOC_DAIFMT_DSP_B:
395 /* Data on rising edge of bclk, frame high */
396 xcr |= ESAI_xCR_xFSL;
397 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
403 /* DAI clock inversion */
404 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
405 case SND_SOC_DAIFMT_NB_NF:
406 /* Nothing to do for both normal cases */
408 case SND_SOC_DAIFMT_IB_NF:
409 /* Invert bit clock */
410 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
412 case SND_SOC_DAIFMT_NB_IF:
413 /* Invert frame clock */
414 xccr ^= ESAI_xCCR_xFSP;
416 case SND_SOC_DAIFMT_IB_IF:
417 /* Invert both clocks */
418 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
424 esai_priv->slave_mode = false;
426 /* DAI clock master masks */
427 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
428 case SND_SOC_DAIFMT_CBM_CFM:
429 esai_priv->slave_mode = true;
431 case SND_SOC_DAIFMT_CBS_CFM:
432 xccr |= ESAI_xCCR_xCKD;
434 case SND_SOC_DAIFMT_CBM_CFS:
435 xccr |= ESAI_xCCR_xFSD;
437 case SND_SOC_DAIFMT_CBS_CFS:
438 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
444 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
445 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
446 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
448 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
449 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
450 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
451 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
456 static int fsl_esai_startup(struct snd_pcm_substream *substream,
457 struct snd_soc_dai *dai)
459 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
463 * Some platforms might use the same bit to gate all three or two of
464 * clocks, so keep all clocks open/close at the same time for safety
466 ret = clk_prepare_enable(esai_priv->coreclk);
469 if (!IS_ERR(esai_priv->extalclk)) {
470 ret = clk_prepare_enable(esai_priv->extalclk);
474 if (!IS_ERR(esai_priv->fsysclk)) {
475 ret = clk_prepare_enable(esai_priv->fsysclk);
481 /* Set synchronous mode */
482 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
483 ESAI_SAICR_SYNC, esai_priv->synchronous ?
484 ESAI_SAICR_SYNC : 0);
486 /* Set a default slot number -- 2 */
487 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
488 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
489 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
490 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
496 if (!IS_ERR(esai_priv->extalclk))
497 clk_disable_unprepare(esai_priv->extalclk);
499 clk_disable_unprepare(esai_priv->coreclk);
504 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
505 struct snd_pcm_hw_params *params,
506 struct snd_soc_dai *dai)
508 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
509 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
510 u32 width = snd_pcm_format_width(params_format(params));
511 u32 channels = params_channels(params);
515 bclk = params_rate(params) * esai_priv->slot_width * 2;
517 ret = fsl_esai_set_bclk(dai, tx, bclk);
521 /* Use Normal mode to support monaural audio */
522 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
523 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
524 ESAI_xCR_xMOD_NETWORK : 0);
526 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
527 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
529 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
530 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
531 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
532 (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels));
534 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
536 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
537 val = ESAI_xCR_xSWS(esai_priv->slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
539 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
541 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
542 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
543 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
544 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
545 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
549 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
550 struct snd_soc_dai *dai)
552 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
554 if (!IS_ERR(esai_priv->fsysclk))
555 clk_disable_unprepare(esai_priv->fsysclk);
556 if (!IS_ERR(esai_priv->extalclk))
557 clk_disable_unprepare(esai_priv->extalclk);
558 clk_disable_unprepare(esai_priv->coreclk);
561 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
562 struct snd_soc_dai *dai)
564 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
565 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
566 u8 i, channels = substream->runtime->channels;
569 case SNDRV_PCM_TRIGGER_START:
570 case SNDRV_PCM_TRIGGER_RESUME:
571 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
572 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
573 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
575 /* Write initial words reqiured by ESAI as normal procedure */
576 for (i = 0; tx && i < channels; i++)
577 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
579 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
580 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
581 tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels));
583 case SNDRV_PCM_TRIGGER_SUSPEND:
584 case SNDRV_PCM_TRIGGER_STOP:
585 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
586 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
587 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
589 /* Disable and reset FIFO */
590 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
591 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
592 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
602 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
603 .startup = fsl_esai_startup,
604 .shutdown = fsl_esai_shutdown,
605 .trigger = fsl_esai_trigger,
606 .hw_params = fsl_esai_hw_params,
607 .set_sysclk = fsl_esai_set_dai_sysclk,
608 .set_fmt = fsl_esai_set_dai_fmt,
609 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
612 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
614 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
616 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
617 &esai_priv->dma_params_rx);
622 static struct snd_soc_dai_driver fsl_esai_dai = {
623 .probe = fsl_esai_dai_probe,
625 .stream_name = "CPU-Playback",
628 .rates = FSL_ESAI_RATES,
629 .formats = FSL_ESAI_FORMATS,
632 .stream_name = "CPU-Capture",
635 .rates = FSL_ESAI_RATES,
636 .formats = FSL_ESAI_FORMATS,
638 .ops = &fsl_esai_dai_ops,
641 static const struct snd_soc_component_driver fsl_esai_component = {
645 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
677 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
708 static struct regmap_config fsl_esai_regmap_config = {
713 .max_register = REG_ESAI_PCRC,
714 .readable_reg = fsl_esai_readable_reg,
715 .writeable_reg = fsl_esai_writeable_reg,
718 static int fsl_esai_probe(struct platform_device *pdev)
720 struct device_node *np = pdev->dev.of_node;
721 struct fsl_esai *esai_priv;
722 struct resource *res;
723 const uint32_t *iprop;
727 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
731 esai_priv->pdev = pdev;
732 strcpy(esai_priv->name, np->name);
734 if (of_property_read_bool(np, "big-endian"))
735 fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
737 /* Get the addresses and IRQ */
738 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 regs = devm_ioremap_resource(&pdev->dev, res);
741 return PTR_ERR(regs);
743 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
744 "core", regs, &fsl_esai_regmap_config);
745 if (IS_ERR(esai_priv->regmap)) {
746 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
747 PTR_ERR(esai_priv->regmap));
748 return PTR_ERR(esai_priv->regmap);
751 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
752 if (IS_ERR(esai_priv->coreclk)) {
753 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
754 PTR_ERR(esai_priv->coreclk));
755 return PTR_ERR(esai_priv->coreclk);
758 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
759 if (IS_ERR(esai_priv->extalclk))
760 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
761 PTR_ERR(esai_priv->extalclk));
763 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
764 if (IS_ERR(esai_priv->fsysclk))
765 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
766 PTR_ERR(esai_priv->fsysclk));
768 irq = platform_get_irq(pdev, 0);
770 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
774 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
775 esai_priv->name, esai_priv);
777 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
781 /* Set a default slot size */
782 esai_priv->slot_width = 32;
784 /* Set a default master/slave state */
785 esai_priv->slave_mode = true;
787 /* Determine the FIFO depth */
788 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
790 esai_priv->fifo_depth = be32_to_cpup(iprop);
792 esai_priv->fifo_depth = 64;
794 esai_priv->dma_params_tx.maxburst = 16;
795 esai_priv->dma_params_rx.maxburst = 16;
796 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
797 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
799 esai_priv->synchronous =
800 of_property_read_bool(np, "fsl,esai-synchronous");
802 /* Implement full symmetry for synchronous mode */
803 if (esai_priv->synchronous) {
804 fsl_esai_dai.symmetric_rates = 1;
805 fsl_esai_dai.symmetric_channels = 1;
806 fsl_esai_dai.symmetric_samplebits = 1;
809 dev_set_drvdata(&pdev->dev, esai_priv);
811 /* Reset ESAI unit */
812 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
814 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
819 * We need to enable ESAI so as to access some of its registers.
820 * Otherwise, we would fail to dump regmap from user space.
822 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
824 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
828 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
831 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
835 ret = imx_pcm_dma_init(pdev);
837 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
842 static const struct of_device_id fsl_esai_dt_ids[] = {
843 { .compatible = "fsl,imx35-esai", },
844 { .compatible = "fsl,vf610-esai", },
847 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
849 static struct platform_driver fsl_esai_driver = {
850 .probe = fsl_esai_probe,
852 .name = "fsl-esai-dai",
853 .owner = THIS_MODULE,
854 .of_match_table = fsl_esai_dt_ids,
858 module_platform_driver(fsl_esai_driver);
860 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
861 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
862 MODULE_LICENSE("GPL v2");
863 MODULE_ALIAS("platform:fsl-esai-dai");