2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
30 #include <sound/wm9081.h>
33 static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
101 } clk_sys_rates[] = {
132 int div; /* *10 due to .5s */
159 enum snd_soc_control_type control_type;
169 struct wm9081_pdata pdata;
172 static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
175 case WM9081_SOFTWARE_RESET:
182 static int wm9081_reset(struct snd_soc_codec *codec)
184 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
187 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
188 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
189 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
190 static unsigned int drc_max_tlv[] = {
191 TLV_DB_RANGE_HEAD(4),
192 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
193 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
194 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
195 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
197 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
198 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
200 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
202 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
203 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
204 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
206 static const char *drc_high_text[] = {
215 static const struct soc_enum drc_high =
216 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
218 static const char *drc_low_text[] = {
226 static const struct soc_enum drc_low =
227 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
229 static const char *drc_atk_text[] = {
244 static const struct soc_enum drc_atk =
245 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
247 static const char *drc_dcy_text[] = {
259 static const struct soc_enum drc_dcy =
260 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
262 static const char *drc_qr_dcy_text[] = {
268 static const struct soc_enum drc_qr_dcy =
269 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
271 static const char *dac_deemph_text[] = {
278 static const struct soc_enum dac_deemph =
279 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
281 static const char *speaker_mode_text[] = {
286 static const struct soc_enum speaker_mode =
287 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
289 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
292 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
295 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
296 if (reg & WM9081_SPK_MODE)
297 ucontrol->value.integer.value[0] = 1;
299 ucontrol->value.integer.value[0] = 0;
305 * Stop any attempts to change speaker mode while the speaker is enabled.
307 * We also have some special anti-pop controls dependent on speaker
308 * mode which must be changed along with the mode.
310 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
311 struct snd_ctl_elem_value *ucontrol)
313 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
314 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
315 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
317 /* Are we changing anything? */
318 if (ucontrol->value.integer.value[0] ==
319 ((reg2 & WM9081_SPK_MODE) != 0))
322 /* Don't try to change modes while enabled */
323 if (reg_pwr & WM9081_SPK_ENA)
326 if (ucontrol->value.integer.value[0]) {
328 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
329 reg2 |= WM9081_SPK_MODE;
332 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
333 reg2 &= ~WM9081_SPK_MODE;
336 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
341 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
342 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
343 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
345 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
347 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
348 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
349 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
351 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
352 SOC_ENUM("DRC High Slope", drc_high),
353 SOC_ENUM("DRC Low Slope", drc_low),
354 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
355 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
356 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
357 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
358 SOC_ENUM("DRC Attack", drc_atk),
359 SOC_ENUM("DRC Decay", drc_dcy),
360 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
361 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
362 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
363 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
365 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
367 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
368 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
369 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
370 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
371 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
373 SOC_ENUM("DAC Deemphasis", dac_deemph),
374 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
377 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
378 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
379 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
380 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
381 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
382 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
385 static const struct snd_kcontrol_new mixer[] = {
386 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
387 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
388 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
399 /* The size in bits of the FLL divide multiplied by 10
400 * to allow rounding later */
401 #define FIXED_FLL_SIZE ((1 << 16) * 10)
410 { 64000, 128000, 3, 8 },
411 { 128000, 256000, 2, 4 },
412 { 256000, 1000000, 1, 2 },
413 { 1000000, 13500000, 0, 1 },
416 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
420 unsigned int K, Ndiv, Nmod, target;
424 /* Fref must be <=13.5MHz */
426 while ((Fref / div) > 13500000) {
430 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
435 fll_div->fll_clk_ref_div = div / 2;
437 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
439 /* Apply the division for our remaining calculations */
442 /* Fvco should be 90-100MHz; don't check the upper bound */
445 while (target < 90000000) {
449 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
454 fll_div->fll_outdiv = div;
456 pr_debug("Fvco=%dHz\n", target);
458 /* Find an appropriate FLL_FRATIO and factor it out of the target */
459 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
460 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
461 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
462 target /= fll_fratios[i].ratio;
466 if (i == ARRAY_SIZE(fll_fratios)) {
467 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
471 /* Now, calculate N.K */
472 Ndiv = target / Fref;
475 Nmod = target % Fref;
476 pr_debug("Nmod=%d\n", Nmod);
478 /* Calculate fractional part - scale up so we can round. */
479 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
483 K = Kpart & 0xFFFFFFFF;
488 /* Move down to proper range now rounding is done */
491 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
492 fll_div->n, fll_div->k,
493 fll_div->fll_fratio, fll_div->fll_outdiv,
494 fll_div->fll_clk_ref_div);
499 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
500 unsigned int Fref, unsigned int Fout)
502 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
503 u16 reg1, reg4, reg5;
504 struct _fll_div fll_div;
509 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
512 /* Disable the FLL */
514 dev_dbg(codec->dev, "FLL disabled\n");
515 wm9081->fll_fref = 0;
516 wm9081->fll_fout = 0;
521 ret = fll_factors(&fll_div, Fref, Fout);
525 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
526 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
529 case WM9081_SYSCLK_FLL_MCLK:
534 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
538 /* Disable CLK_SYS while we reconfigure */
539 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
540 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
541 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
542 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
544 /* Any FLL configuration change requires that the FLL be
546 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
547 reg1 &= ~WM9081_FLL_ENA;
548 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
550 /* Apply the configuration */
552 reg1 |= WM9081_FLL_FRAC_MASK;
554 reg1 &= ~WM9081_FLL_FRAC_MASK;
555 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
557 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
558 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
559 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
560 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
562 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
563 reg4 &= ~WM9081_FLL_N_MASK;
564 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
565 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
567 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
568 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
569 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
571 /* Set gain to the recommended value */
572 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
573 WM9081_FLL_GAIN_MASK, 0);
576 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
578 /* Then bring CLK_SYS up again if it was disabled */
579 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
580 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
582 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
584 wm9081->fll_fref = Fref;
585 wm9081->fll_fout = Fout;
590 static int configure_clock(struct snd_soc_codec *codec)
592 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
593 int new_sysclk, i, target;
599 switch (wm9081->sysclk_source) {
600 case WM9081_SYSCLK_MCLK:
601 if (wm9081->mclk_rate > 12225000) {
603 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
605 wm9081->sysclk_rate = wm9081->mclk_rate;
607 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
610 case WM9081_SYSCLK_FLL_MCLK:
611 /* If we have a sample rate calculate a CLK_SYS that
612 * gives us a suitable DAC configuration, plus BCLK.
613 * Ideally we would check to see if we can clock
614 * directly from MCLK and only use the FLL if this is
615 * not the case, though care must be taken with free
618 if (wm9081->master && wm9081->bclk) {
619 /* Make sure we can generate CLK_SYS and BCLK
620 * and that we've got 3MHz for optimal
622 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
623 target = wm9081->fs * clk_sys_rates[i].ratio;
625 if (target >= wm9081->bclk &&
630 if (i == ARRAY_SIZE(clk_sys_rates))
633 } else if (wm9081->fs) {
634 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
635 new_sysclk = clk_sys_rates[i].ratio
637 if (new_sysclk > 3000000)
641 if (i == ARRAY_SIZE(clk_sys_rates))
645 new_sysclk = 12288000;
648 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
649 wm9081->mclk_rate, new_sysclk);
651 wm9081->sysclk_rate = new_sysclk;
653 /* Switch SYSCLK over to FLL */
656 wm9081->sysclk_rate = wm9081->mclk_rate;
664 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
666 reg |= WM9081_MCLKDIV2;
668 reg &= ~WM9081_MCLKDIV2;
669 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
671 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
673 reg |= WM9081_CLK_SRC_SEL;
675 reg &= ~WM9081_CLK_SRC_SEL;
676 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
678 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
683 static int clk_sys_event(struct snd_soc_dapm_widget *w,
684 struct snd_kcontrol *kcontrol, int event)
686 struct snd_soc_codec *codec = w->codec;
687 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
689 /* This should be done on init() for bypass paths */
690 switch (wm9081->sysclk_source) {
691 case WM9081_SYSCLK_MCLK:
692 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
694 case WM9081_SYSCLK_FLL_MCLK:
695 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
699 dev_err(codec->dev, "System clock not configured\n");
704 case SND_SOC_DAPM_PRE_PMU:
705 configure_clock(codec);
708 case SND_SOC_DAPM_POST_PMD:
709 /* Disable the FLL if it's running */
710 wm9081_set_fll(codec, 0, 0, 0);
717 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
718 SND_SOC_DAPM_INPUT("IN1"),
719 SND_SOC_DAPM_INPUT("IN2"),
721 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
723 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
724 mixer, ARRAY_SIZE(mixer)),
726 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
728 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
729 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
731 SND_SOC_DAPM_OUTPUT("LINEOUT"),
732 SND_SOC_DAPM_OUTPUT("SPKN"),
733 SND_SOC_DAPM_OUTPUT("SPKP"),
735 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
737 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
738 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
742 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
743 { "DAC", NULL, "CLK_SYS" },
744 { "DAC", NULL, "CLK_DSP" },
746 { "Mixer", "IN1 Switch", "IN1" },
747 { "Mixer", "IN2 Switch", "IN2" },
748 { "Mixer", "Playback Switch", "DAC" },
750 { "LINEOUT PGA", NULL, "Mixer" },
751 { "LINEOUT PGA", NULL, "TOCLK" },
752 { "LINEOUT PGA", NULL, "CLK_SYS" },
754 { "LINEOUT", NULL, "LINEOUT PGA" },
756 { "Speaker PGA", NULL, "Mixer" },
757 { "Speaker PGA", NULL, "TOCLK" },
758 { "Speaker PGA", NULL, "CLK_SYS" },
760 { "Speaker", NULL, "Speaker PGA" },
762 { "SPKN", NULL, "Speaker" },
763 { "SPKP", NULL, "Speaker" },
766 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
767 enum snd_soc_bias_level level)
772 case SND_SOC_BIAS_ON:
775 case SND_SOC_BIAS_PREPARE:
777 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
778 reg &= ~WM9081_VMID_SEL_MASK;
780 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
782 /* Normal bias current */
783 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
784 reg &= ~WM9081_STBY_BIAS_ENA;
785 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
788 case SND_SOC_BIAS_STANDBY:
789 /* Initial cold start */
790 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
791 /* Disable LINEOUT discharge */
792 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
793 reg &= ~WM9081_LINEOUT_DISCH;
794 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
796 /* Select startup bias source */
797 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
798 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
799 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
801 /* VMID 2*4k; Soft VMID ramp enable */
802 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
803 reg |= WM9081_VMID_RAMP | 0x6;
804 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
808 /* Normal bias enable & soft start off */
809 reg |= WM9081_BIAS_ENA;
810 reg &= ~WM9081_VMID_RAMP;
811 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
813 /* Standard bias source */
814 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
815 reg &= ~WM9081_BIAS_SRC;
816 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
820 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
821 reg &= ~WM9081_VMID_SEL_MASK;
823 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
825 /* Standby bias current on */
826 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
827 reg |= WM9081_STBY_BIAS_ENA;
828 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
831 case SND_SOC_BIAS_OFF:
832 /* Startup bias source */
833 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
834 reg |= WM9081_BIAS_SRC;
835 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
837 /* Disable VMID and biases with soft ramping */
838 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
839 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
840 reg |= WM9081_VMID_RAMP;
841 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
843 /* Actively discharge LINEOUT */
844 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
845 reg |= WM9081_LINEOUT_DISCH;
846 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
850 codec->dapm.bias_level = level;
855 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
858 struct snd_soc_codec *codec = dai->codec;
859 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
860 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
862 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
863 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
865 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
866 case SND_SOC_DAIFMT_CBS_CFS:
869 case SND_SOC_DAIFMT_CBS_CFM:
870 aif2 |= WM9081_LRCLK_DIR;
873 case SND_SOC_DAIFMT_CBM_CFS:
874 aif2 |= WM9081_BCLK_DIR;
877 case SND_SOC_DAIFMT_CBM_CFM:
878 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
886 case SND_SOC_DAIFMT_DSP_B:
887 aif2 |= WM9081_AIF_LRCLK_INV;
888 case SND_SOC_DAIFMT_DSP_A:
891 case SND_SOC_DAIFMT_I2S:
894 case SND_SOC_DAIFMT_RIGHT_J:
896 case SND_SOC_DAIFMT_LEFT_J:
903 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
904 case SND_SOC_DAIFMT_DSP_A:
905 case SND_SOC_DAIFMT_DSP_B:
906 /* frame inversion not valid for DSP modes */
907 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
908 case SND_SOC_DAIFMT_NB_NF:
910 case SND_SOC_DAIFMT_IB_NF:
911 aif2 |= WM9081_AIF_BCLK_INV;
918 case SND_SOC_DAIFMT_I2S:
919 case SND_SOC_DAIFMT_RIGHT_J:
920 case SND_SOC_DAIFMT_LEFT_J:
921 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
922 case SND_SOC_DAIFMT_NB_NF:
924 case SND_SOC_DAIFMT_IB_IF:
925 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
927 case SND_SOC_DAIFMT_IB_NF:
928 aif2 |= WM9081_AIF_BCLK_INV;
930 case SND_SOC_DAIFMT_NB_IF:
931 aif2 |= WM9081_AIF_LRCLK_INV;
941 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
946 static int wm9081_hw_params(struct snd_pcm_substream *substream,
947 struct snd_pcm_hw_params *params,
948 struct snd_soc_dai *dai)
950 struct snd_soc_codec *codec = dai->codec;
951 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
952 int ret, i, best, best_val, cur_val;
953 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
955 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
956 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
958 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
960 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
961 aif2 &= ~WM9081_AIF_WL_MASK;
963 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
964 aif3 &= ~WM9081_BCLK_DIV_MASK;
966 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
967 aif4 &= ~WM9081_LRCLK_RATE_MASK;
969 wm9081->fs = params_rate(params);
971 if (wm9081->tdm_width) {
972 /* If TDM is set up then that fixes our BCLK. */
973 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
974 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
976 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
978 /* Otherwise work out a BCLK from the sample size */
979 wm9081->bclk = 2 * wm9081->fs;
981 switch (params_format(params)) {
982 case SNDRV_PCM_FORMAT_S16_LE:
985 case SNDRV_PCM_FORMAT_S20_3LE:
989 case SNDRV_PCM_FORMAT_S24_LE:
993 case SNDRV_PCM_FORMAT_S32_LE:
1002 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1004 ret = configure_clock(codec);
1008 /* Select nearest CLK_SYS_RATE */
1010 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1012 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1013 cur_val = abs((wm9081->sysclk_rate /
1014 clk_sys_rates[i].ratio) - wm9081->fs);
1015 if (cur_val < best_val) {
1020 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1021 clk_sys_rates[best].ratio);
1022 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1023 << WM9081_CLK_SYS_RATE_SHIFT);
1027 best_val = abs(wm9081->fs - sample_rates[0].rate);
1028 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1030 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1031 if (cur_val < best_val) {
1036 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1037 sample_rates[best].rate);
1038 clk_ctrl2 |= (sample_rates[best].sample_rate
1039 << WM9081_SAMPLE_RATE_SHIFT);
1044 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1045 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1047 if (cur_val < 0) /* Table is sorted */
1049 if (cur_val < best_val) {
1054 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1055 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1056 bclk_divs[best].div, wm9081->bclk);
1057 aif3 |= bclk_divs[best].bclk_div;
1059 /* LRCLK is a simple fraction of BCLK */
1060 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1061 aif4 |= wm9081->bclk / wm9081->fs;
1063 /* Apply a ReTune Mobile configuration if it's in use */
1064 if (wm9081->pdata.num_retune_configs) {
1065 struct wm9081_pdata *pdata = &wm9081->pdata;
1066 struct wm9081_retune_mobile_setting *s;
1070 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1071 for (i = 0; i < pdata->num_retune_configs; i++) {
1072 cur_val = abs(pdata->retune_configs[i].rate -
1074 if (cur_val < best_val) {
1079 s = &pdata->retune_configs[best];
1081 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1084 /* If the EQ is enabled then disable it while we write out */
1085 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1086 if (eq1 & WM9081_EQ_ENA)
1087 snd_soc_write(codec, WM9081_EQ_1, 0);
1089 /* Write out the other values */
1090 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1091 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1093 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1094 snd_soc_write(codec, WM9081_EQ_1, eq1);
1097 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1098 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1099 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1100 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1105 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1107 struct snd_soc_codec *codec = codec_dai->codec;
1110 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1113 reg |= WM9081_DAC_MUTE;
1115 reg &= ~WM9081_DAC_MUTE;
1117 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1122 static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1123 int source, unsigned int freq, int dir)
1125 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1128 case WM9081_SYSCLK_MCLK:
1129 case WM9081_SYSCLK_FLL_MCLK:
1130 wm9081->sysclk_source = clk_id;
1131 wm9081->mclk_rate = freq;
1141 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1142 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1144 struct snd_soc_codec *codec = dai->codec;
1145 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1146 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1148 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1150 if (slots < 0 || slots > 4)
1153 wm9081->tdm_width = slot_width;
1158 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1176 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1181 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1183 #define WM9081_FORMATS \
1184 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1185 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1187 static struct snd_soc_dai_ops wm9081_dai_ops = {
1188 .hw_params = wm9081_hw_params,
1189 .set_fmt = wm9081_set_dai_fmt,
1190 .digital_mute = wm9081_digital_mute,
1191 .set_tdm_slot = wm9081_set_tdm_slot,
1194 /* We report two channels because the CODEC processes a stereo signal, even
1195 * though it is only capable of handling a mono output.
1197 static struct snd_soc_dai_driver wm9081_dai = {
1198 .name = "wm9081-hifi",
1200 .stream_name = "HiFi Playback",
1203 .rates = WM9081_RATES,
1204 .formats = WM9081_FORMATS,
1206 .ops = &wm9081_dai_ops,
1209 static int wm9081_probe(struct snd_soc_codec *codec)
1211 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1215 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1217 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1221 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1222 if (reg != 0x9081) {
1223 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1228 ret = wm9081_reset(codec);
1230 dev_err(codec->dev, "Failed to issue reset\n");
1235 if (wm9081->pdata.irq_high)
1236 reg |= WM9081_IRQ_POL;
1237 if (!wm9081->pdata.irq_cmos)
1238 reg |= WM9081_IRQ_OP_CTRL;
1239 snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
1240 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1242 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1244 /* Enable zero cross by default */
1245 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1246 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1247 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1248 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1249 reg | WM9081_SPKPGAZC);
1251 snd_soc_add_controls(codec, wm9081_snd_controls,
1252 ARRAY_SIZE(wm9081_snd_controls));
1253 if (!wm9081->pdata.num_retune_configs) {
1255 "No ReTune Mobile data, using normal EQ\n");
1256 snd_soc_add_controls(codec, wm9081_eq_controls,
1257 ARRAY_SIZE(wm9081_eq_controls));
1263 static int wm9081_remove(struct snd_soc_codec *codec)
1265 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1270 static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
1272 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1277 static int wm9081_resume(struct snd_soc_codec *codec)
1279 u16 *reg_cache = codec->reg_cache;
1282 for (i = 0; i < codec->driver->reg_cache_size; i++) {
1283 if (i == WM9081_SOFTWARE_RESET)
1286 snd_soc_write(codec, i, reg_cache[i]);
1289 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1294 #define wm9081_suspend NULL
1295 #define wm9081_resume NULL
1298 static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
1299 .probe = wm9081_probe,
1300 .remove = wm9081_remove,
1301 .suspend = wm9081_suspend,
1302 .resume = wm9081_resume,
1304 .set_sysclk = wm9081_set_sysclk,
1305 .set_bias_level = wm9081_set_bias_level,
1307 .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
1308 .reg_word_size = sizeof(u16),
1309 .reg_cache_default = wm9081_reg_defaults,
1310 .volatile_register = wm9081_volatile_register,
1312 .dapm_widgets = wm9081_dapm_widgets,
1313 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1314 .dapm_routes = wm9081_audio_paths,
1315 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
1318 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1319 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1320 const struct i2c_device_id *id)
1322 struct wm9081_priv *wm9081;
1325 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1329 i2c_set_clientdata(i2c, wm9081);
1330 wm9081->control_type = SND_SOC_I2C;
1332 if (dev_get_platdata(&i2c->dev))
1333 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1334 sizeof(wm9081->pdata));
1336 ret = snd_soc_register_codec(&i2c->dev,
1337 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1343 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1345 snd_soc_unregister_codec(&client->dev);
1346 kfree(i2c_get_clientdata(client));
1350 static const struct i2c_device_id wm9081_i2c_id[] = {
1354 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1356 static struct i2c_driver wm9081_i2c_driver = {
1359 .owner = THIS_MODULE,
1361 .probe = wm9081_i2c_probe,
1362 .remove = __devexit_p(wm9081_i2c_remove),
1363 .id_table = wm9081_i2c_id,
1367 static int __init wm9081_modinit(void)
1370 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1371 ret = i2c_add_driver(&wm9081_i2c_driver);
1373 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1379 module_init(wm9081_modinit);
1381 static void __exit wm9081_exit(void)
1383 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1384 i2c_del_driver(&wm9081_i2c_driver);
1387 module_exit(wm9081_exit);
1390 MODULE_DESCRIPTION("ASoC WM9081 driver");
1391 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1392 MODULE_LICENSE("GPL");