sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = wm8994->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110         case WM8994_DC_SERVO_4E:
 111                 return 1;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 118         unsigned int value)
 119 {
 120         int ret;
 121
 122         BUG_ON(reg > WM8994_MAX_REGISTER);
 123
 124         if (!wm8994_volatile(codec, reg)) {
 125                 ret = snd_soc_cache_write(codec, reg, value);
 126                 if (ret != 0)
 127                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 128                                 reg, ret);
 129         }
 130
 131         return wm8994_reg_write(codec->control_data, reg, value);
 132 }
 133
 134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 135                                 unsigned int reg)
 136 {
 137         unsigned int val;
 138         int ret;
 139
 140         BUG_ON(reg > WM8994_MAX_REGISTER);
 141
 142         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 143             reg < codec->driver->reg_cache_size) {
 144                 ret = snd_soc_cache_read(codec, reg, &val);
 145                 if (ret >= 0)
 146                         return val;
 147                 else
 148                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 149                                 reg, ret);
 150         }
 151
 152         return wm8994_reg_read(codec->control_data, reg);
 153 }
 154
 155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 156 {
 157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 158         int rate;
 159         int reg1 = 0;
 160         int offset;
 161
 162         if (aif)
 163                 offset = 4;
 164         else
 165                 offset = 0;
 166
 167         switch (wm8994->sysclk[aif]) {
 168         case WM8994_SYSCLK_MCLK1:
 169                 rate = wm8994->mclk[0];
 170                 break;
 171
 172         case WM8994_SYSCLK_MCLK2:
 173                 reg1 |= 0x8;
 174                 rate = wm8994->mclk[1];
 175                 break;
 176
 177         case WM8994_SYSCLK_FLL1:
 178                 reg1 |= 0x10;
 179                 rate = wm8994->fll[0].out;
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL2:
 183                 reg1 |= 0x18;
 184                 rate = wm8994->fll[1].out;
 185                 break;
 186
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         if (rate >= 13500000) {
 192                 rate /= 2;
 193                 reg1 |= WM8994_AIF1CLK_DIV;
 194
 195                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 196                         aif + 1, rate);
 197         }
 198
 199         wm8994->aifclk[aif] = rate;
 200
 201         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 202                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 203                             reg1);
 204
 205         return 0;
 206 }
 207
 208 static int configure_clock(struct snd_soc_codec *codec)
 209 {
 210         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 211         int old, new;
 212
 213         /* Bring up the AIF clocks first */
 214         configure_aif_clock(codec, 0);
 215         configure_aif_clock(codec, 1);
 216
 217         /* Then switch CLK_SYS over to the higher of them; a change
 218          * can only happen as a result of a clocking change which can
 219          * only be made outside of DAPM so we can safely redo the
 220          * clocking.
 221          */
 222
 223         /* If they're equal it doesn't matter which is used */
 224         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 225                 return 0;
 226
 227         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 228                 new = WM8994_SYSCLK_SRC;
 229         else
 230                 new = 0;
 231
 232         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 233
 234         /* If there's no change then we're done. */
 235         if (old == new)
 236                 return 0;
 237
 238         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 239
 240         snd_soc_dapm_sync(&codec->dapm);
 241
 242         return 0;
 243 }
 244
 245 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 246                          struct snd_soc_dapm_widget *sink)
 247 {
 248         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 249         const char *clk;
 250
 251         /* Check what we're currently using for CLK_SYS */
 252         if (reg & WM8994_SYSCLK_SRC)
 253                 clk = "AIF2CLK";
 254         else
 255                 clk = "AIF1CLK";
 256
 257         return strcmp(source->name, clk) == 0;
 258 }
 259
 260 static const char *sidetone_hpf_text[] = {
 261         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 262 };
 263
 264 static const struct soc_enum sidetone_hpf =
 265         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 266
 267 static const char *adc_hpf_text[] = {
 268         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 269 };
 270
 271 static const struct soc_enum aif1adc1_hpf =
 272         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 273
 274 static const struct soc_enum aif1adc2_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif2adc_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 281 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 282 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 283 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 284 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 285 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 286 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 287
 288 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 289 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 290         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 291         .put = wm8994_put_drc_sw, \
 292         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 293
 294 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 295                              struct snd_ctl_elem_value *ucontrol)
 296 {
 297         struct soc_mixer_control *mc =
 298                 (struct soc_mixer_control *)kcontrol->private_value;
 299         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 300         int mask, ret;
 301
 302         /* Can't enable both ADC and DAC paths simultaneously */
 303         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 304                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 305                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 306         else
 307                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 308
 309         ret = snd_soc_read(codec, mc->reg);
 310         if (ret < 0)
 311                 return ret;
 312         if (ret & mask)
 313                 return -EINVAL;
 314
 315         return snd_soc_put_volsw(kcontrol, ucontrol);
 316 }
 317
 318 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 319 {
 320         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 321         struct wm8994_pdata *pdata = wm8994->pdata;
 322         int base = wm8994_drc_base[drc];
 323         int cfg = wm8994->drc_cfg[drc];
 324         int save, i;
 325
 326         /* Save any enables; the configuration should clear them. */
 327         save = snd_soc_read(codec, base);
 328         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 329                 WM8994_AIF1ADC1R_DRC_ENA;
 330
 331         for (i = 0; i < WM8994_DRC_REGS; i++)
 332                 snd_soc_update_bits(codec, base + i, 0xffff,
 333                                     pdata->drc_cfgs[cfg].regs[i]);
 334
 335         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 336                              WM8994_AIF1ADC1L_DRC_ENA |
 337                              WM8994_AIF1ADC1R_DRC_ENA, save);
 338 }
 339
 340 /* Icky as hell but saves code duplication */
 341 static int wm8994_get_drc(const char *name)
 342 {
 343         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 344                 return 0;
 345         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 346                 return 1;
 347         if (strcmp(name, "AIF2DRC Mode") == 0)
 348                 return 2;
 349         return -EINVAL;
 350 }
 351
 352 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 353                                struct snd_ctl_elem_value *ucontrol)
 354 {
 355         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 356         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 357         struct wm8994_pdata *pdata = wm8994->pdata;
 358         int drc = wm8994_get_drc(kcontrol->id.name);
 359         int value = ucontrol->value.integer.value[0];
 360
 361         if (drc < 0)
 362                 return drc;
 363
 364         if (value >= pdata->num_drc_cfgs)
 365                 return -EINVAL;
 366
 367         wm8994->drc_cfg[drc] = value;
 368
 369         wm8994_set_drc(codec, drc);
 370
 371         return 0;
 372 }
 373
 374 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 375                                struct snd_ctl_elem_value *ucontrol)
 376 {
 377         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 378         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 379         int drc = wm8994_get_drc(kcontrol->id.name);
 380
 381         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 382
 383         return 0;
 384 }
 385
 386 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 387 {
 388         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 389         struct wm8994_pdata *pdata = wm8994->pdata;
 390         int base = wm8994_retune_mobile_base[block];
 391         int iface, best, best_val, save, i, cfg;
 392
 393         if (!pdata || !wm8994->num_retune_mobile_texts)
 394                 return;
 395
 396         switch (block) {
 397         case 0:
 398         case 1:
 399                 iface = 0;
 400                 break;
 401         case 2:
 402                 iface = 1;
 403                 break;
 404         default:
 405                 return;
 406         }
 407
 408         /* Find the version of the currently selected configuration
 409          * with the nearest sample rate. */
 410         cfg = wm8994->retune_mobile_cfg[block];
 411         best = 0;
 412         best_val = INT_MAX;
 413         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 414                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 415                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 416                     abs(pdata->retune_mobile_cfgs[i].rate
 417                         - wm8994->dac_rates[iface]) < best_val) {
 418                         best = i;
 419                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 420                                        - wm8994->dac_rates[iface]);
 421                 }
 422         }
 423
 424         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 425                 block,
 426                 pdata->retune_mobile_cfgs[best].name,
 427                 pdata->retune_mobile_cfgs[best].rate,
 428                 wm8994->dac_rates[iface]);
 429
 430         /* The EQ will be disabled while reconfiguring it, remember the
 431          * current configuration.
 432          */
 433         save = snd_soc_read(codec, base);
 434         save &= WM8994_AIF1DAC1_EQ_ENA;
 435
 436         for (i = 0; i < WM8994_EQ_REGS; i++)
 437                 snd_soc_update_bits(codec, base + i, 0xffff,
 438                                 pdata->retune_mobile_cfgs[best].regs[i]);
 439
 440         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 441 }
 442
 443 /* Icky as hell but saves code duplication */
 444 static int wm8994_get_retune_mobile_block(const char *name)
 445 {
 446         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 447                 return 0;
 448         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 449                 return 1;
 450         if (strcmp(name, "AIF2 EQ Mode") == 0)
 451                 return 2;
 452         return -EINVAL;
 453 }
 454
 455 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 456                                          struct snd_ctl_elem_value *ucontrol)
 457 {
 458         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 459         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 460         struct wm8994_pdata *pdata = wm8994->pdata;
 461         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 462         int value = ucontrol->value.integer.value[0];
 463
 464         if (block < 0)
 465                 return block;
 466
 467         if (value >= pdata->num_retune_mobile_cfgs)
 468                 return -EINVAL;
 469
 470         wm8994->retune_mobile_cfg[block] = value;
 471
 472         wm8994_set_retune_mobile(codec, block);
 473
 474         return 0;
 475 }
 476
 477 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 478                                          struct snd_ctl_elem_value *ucontrol)
 479 {
 480         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 481         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 482         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 483
 484         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 485
 486         return 0;
 487 }
 488
 489 static const char *aif_chan_src_text[] = {
 490         "Left", "Right"
 491 };
 492
 493 static const struct soc_enum aif1adcl_src =
 494         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 495
 496 static const struct soc_enum aif1adcr_src =
 497         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 498
 499 static const struct soc_enum aif2adcl_src =
 500         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 501
 502 static const struct soc_enum aif2adcr_src =
 503         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 504
 505 static const struct soc_enum aif1dacl_src =
 506         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 507
 508 static const struct soc_enum aif1dacr_src =
 509         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 510
 511 static const struct soc_enum aif2dacl_src =
 512         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 513
 514 static const struct soc_enum aif2dacr_src =
 515         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 516
 517 static const char *osr_text[] = {
 518         "Low Power", "High Performance",
 519 };
 520
 521 static const struct soc_enum dac_osr =
 522         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 523
 524 static const struct soc_enum adc_osr =
 525         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 526
 527 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 528 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 529                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 530                  1, 119, 0, digital_tlv),
 531 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 532                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 533                  1, 119, 0, digital_tlv),
 534 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 535                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 536                  1, 119, 0, digital_tlv),
 537
 538 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 539 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 540 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 541 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 542
 543 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 544 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 545 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 546 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 547
 548 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 549                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 550 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 551                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 552 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 553                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 554
 555 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 556 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 557
 558 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 559 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 560 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 561
 562 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 563 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 564 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 565
 566 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 567 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 568 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 569
 570 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 571 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 572 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 573
 574 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 575                5, 12, 0, st_tlv),
 576 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 577                0, 12, 0, st_tlv),
 578 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 579                5, 12, 0, st_tlv),
 580 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 581                0, 12, 0, st_tlv),
 582 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 583 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 584
 585 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 586 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 587
 588 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 589 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 590
 591 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 592 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 593
 594 SOC_ENUM("ADC OSR", adc_osr),
 595 SOC_ENUM("DAC OSR", dac_osr),
 596
 597 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 598                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 599 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 600              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 601
 602 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 603                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 604 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 605              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 606
 607 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 608                6, 1, 1, wm_hubs_spkmix_tlv),
 609 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 610                2, 1, 1, wm_hubs_spkmix_tlv),
 611
 612 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 613                6, 1, 1, wm_hubs_spkmix_tlv),
 614 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 615                2, 1, 1, wm_hubs_spkmix_tlv),
 616
 617 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 618                10, 15, 0, wm8994_3d_tlv),
 619 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 620            8, 1, 0),
 621 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 622                10, 15, 0, wm8994_3d_tlv),
 623 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 624            8, 1, 0),
 625 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 626                10, 15, 0, wm8994_3d_tlv),
 627 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 628            8, 1, 0),
 629 };
 630
 631 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 632 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 633                eq_tlv),
 634 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 635                eq_tlv),
 636 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 637                eq_tlv),
 638 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 639                eq_tlv),
 640 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 641                eq_tlv),
 642
 643 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 644                eq_tlv),
 645 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 646                eq_tlv),
 647 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 650                eq_tlv),
 651 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 652                eq_tlv),
 653
 654 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 655                eq_tlv),
 656 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 657                eq_tlv),
 658 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 659                eq_tlv),
 660 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 661                eq_tlv),
 662 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 663                eq_tlv),
 664 };
 665
 666 static const char *wm8958_ng_text[] = {
 667         "30ms", "125ms", "250ms", "500ms",
 668 };
 669
 670 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 671         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 672                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 673
 674 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 675         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 676                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 677
 678 static const struct soc_enum wm8958_aif2dac_ng_hold =
 679         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 680                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 681
 682 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 683 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 684
 685 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 686            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 687 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 688 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 689                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 690                7, 1, ng_tlv),
 691
 692 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 693            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 694 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 695 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 696                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 697                7, 1, ng_tlv),
 698
 699 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 700            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 701 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 702 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 703                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 704                7, 1, ng_tlv),
 705 };
 706
 707 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 708 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 709                mixin_boost_tlv),
 710 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 711                mixin_boost_tlv),
 712 };
 713
 714 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 715                          struct snd_kcontrol *kcontrol, int event)
 716 {
 717         struct snd_soc_codec *codec = w->codec;
 718
 719         switch (event) {
 720         case SND_SOC_DAPM_PRE_PMU:
 721                 return configure_clock(codec);
 722
 723         case SND_SOC_DAPM_POST_PMD:
 724                 configure_clock(codec);
 725                 break;
 726         }
 727
 728         return 0;
 729 }
 730
 731 static void vmid_reference(struct snd_soc_codec *codec)
 732 {
 733         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 734
 735         wm8994->vmid_refcount++;
 736
 737         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 738                 wm8994->vmid_refcount);
 739
 740         if (wm8994->vmid_refcount == 1) {
 741                 /* Startup bias, VMID ramp & buffer */
 742                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 743                                     WM8994_STARTUP_BIAS_ENA |
 744                                     WM8994_VMID_BUF_ENA |
 745                                     WM8994_VMID_RAMP_MASK,
 746                                     WM8994_STARTUP_BIAS_ENA |
 747                                     WM8994_VMID_BUF_ENA |
 748                                     (0x11 << WM8994_VMID_RAMP_SHIFT));
 749
 750                 /* Main bias enable, VMID=2x40k */
 751                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 752                                     WM8994_BIAS_ENA |
 753                                     WM8994_VMID_SEL_MASK,
 754                                     WM8994_BIAS_ENA | 0x2);
 755
 756                 msleep(20);
 757         }
 758 }
 759
 760 static void vmid_dereference(struct snd_soc_codec *codec)
 761 {
 762         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 763
 764         wm8994->vmid_refcount--;
 765
 766         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 767                 wm8994->vmid_refcount);
 768
 769         if (wm8994->vmid_refcount == 0) {
 770                 /* Switch over to startup biases */
 771                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 772                                     WM8994_BIAS_SRC |
 773                                     WM8994_STARTUP_BIAS_ENA |
 774                                     WM8994_VMID_BUF_ENA |
 775                                     WM8994_VMID_RAMP_MASK,
 776                                     WM8994_BIAS_SRC |
 777                                     WM8994_STARTUP_BIAS_ENA |
 778                                     WM8994_VMID_BUF_ENA |
 779                                     (1 << WM8994_VMID_RAMP_SHIFT));
 780
 781                 /* Disable main biases */
 782                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 783                                     WM8994_BIAS_ENA |
 784                                     WM8994_VMID_SEL_MASK, 0);
 785
 786                 /* Discharge line */
 787                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 788                                     WM8994_LINEOUT1_DISCH |
 789                                     WM8994_LINEOUT2_DISCH,
 790                                     WM8994_LINEOUT1_DISCH |
 791                                     WM8994_LINEOUT2_DISCH);
 792
 793                 msleep(5);
 794
 795                 /* Switch off startup biases */
 796                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 797                                     WM8994_BIAS_SRC |
 798                                     WM8994_STARTUP_BIAS_ENA |
 799                                     WM8994_VMID_BUF_ENA |
 800                                     WM8994_VMID_RAMP_MASK, 0);
 801         }
 802 }
 803
 804 static int vmid_event(struct snd_soc_dapm_widget *w,
 805                       struct snd_kcontrol *kcontrol, int event)
 806 {
 807         struct snd_soc_codec *codec = w->codec;
 808
 809         switch (event) {
 810         case SND_SOC_DAPM_PRE_PMU:
 811                 vmid_reference(codec);
 812                 break;
 813
 814         case SND_SOC_DAPM_POST_PMD:
 815                 vmid_dereference(codec);
 816                 break;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 823 {
 824         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 825         int enable = 1;
 826         int source = 0;  /* GCC flow analysis can't track enable */
 827         int reg, reg_r;
 828
 829         /* Only support direct DAC->headphone paths */
 830         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 831         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 832                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 833                 enable = 0;
 834         }
 835
 836         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 837         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 838                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 839                 enable = 0;
 840         }
 841
 842         /* We also need the same setting for L/R and only one path */
 843         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 844         switch (reg) {
 845         case WM8994_AIF2DACL_TO_DAC1L:
 846                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 847                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 848                 break;
 849         case WM8994_AIF1DAC2L_TO_DAC1L:
 850                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 851                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 852                 break;
 853         case WM8994_AIF1DAC1L_TO_DAC1L:
 854                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 855                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 856                 break;
 857         default:
 858                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 859                 enable = 0;
 860                 break;
 861         }
 862
 863         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 864         if (reg_r != reg) {
 865                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 866                 enable = 0;
 867         }
 868
 869         if (enable) {
 870                 dev_dbg(codec->dev, "Class W enabled\n");
 871                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 872                                     WM8994_CP_DYN_PWR |
 873                                     WM8994_CP_DYN_SRC_SEL_MASK,
 874                                     source | WM8994_CP_DYN_PWR);
 875                 wm8994->hubs.class_w = true;
 876
 877         } else {
 878                 dev_dbg(codec->dev, "Class W disabled\n");
 879                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 880                                     WM8994_CP_DYN_PWR, 0);
 881                 wm8994->hubs.class_w = false;
 882         }
 883 }
 884
 885 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 886                           struct snd_kcontrol *kcontrol, int event)
 887 {
 888         struct snd_soc_codec *codec = w->codec;
 889         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 890
 891         switch (event) {
 892         case SND_SOC_DAPM_PRE_PMU:
 893                 if (wm8994->aif1clk_enable) {
 894                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 895                                             WM8994_AIF1CLK_ENA_MASK,
 896                                             WM8994_AIF1CLK_ENA);
 897                         wm8994->aif1clk_enable = 0;
 898                 }
 899                 if (wm8994->aif2clk_enable) {
 900                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 901                                             WM8994_AIF2CLK_ENA_MASK,
 902                                             WM8994_AIF2CLK_ENA);
 903                         wm8994->aif2clk_enable = 0;
 904                 }
 905                 break;
 906         }
 907
 908         /* We may also have postponed startup of DSP, handle that. */
 909         wm8958_aif_ev(w, kcontrol, event);
 910
 911         return 0;
 912 }
 913
 914 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 915                            struct snd_kcontrol *kcontrol, int event)
 916 {
 917         struct snd_soc_codec *codec = w->codec;
 918         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 919
 920         switch (event) {
 921         case SND_SOC_DAPM_POST_PMD:
 922                 if (wm8994->aif1clk_disable) {
 923                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 924                                             WM8994_AIF1CLK_ENA_MASK, 0);
 925                         wm8994->aif1clk_disable = 0;
 926                 }
 927                 if (wm8994->aif2clk_disable) {
 928                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 929                                             WM8994_AIF2CLK_ENA_MASK, 0);
 930                         wm8994->aif2clk_disable = 0;
 931                 }
 932                 break;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 939                       struct snd_kcontrol *kcontrol, int event)
 940 {
 941         struct snd_soc_codec *codec = w->codec;
 942         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 943
 944         switch (event) {
 945         case SND_SOC_DAPM_PRE_PMU:
 946                 wm8994->aif1clk_enable = 1;
 947                 break;
 948         case SND_SOC_DAPM_POST_PMD:
 949                 wm8994->aif1clk_disable = 1;
 950                 break;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 957                       struct snd_kcontrol *kcontrol, int event)
 958 {
 959         struct snd_soc_codec *codec = w->codec;
 960         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 961
 962         switch (event) {
 963         case SND_SOC_DAPM_PRE_PMU:
 964                 wm8994->aif2clk_enable = 1;
 965                 break;
 966         case SND_SOC_DAPM_POST_PMD:
 967                 wm8994->aif2clk_disable = 1;
 968                 break;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 975                       struct snd_kcontrol *kcontrol, int event)
 976 {
 977         late_enable_ev(w, kcontrol, event);
 978         return 0;
 979 }
 980
 981 static int micbias_ev(struct snd_soc_dapm_widget *w,
 982                       struct snd_kcontrol *kcontrol, int event)
 983 {
 984         late_enable_ev(w, kcontrol, event);
 985         return 0;
 986 }
 987
 988 static int dac_ev(struct snd_soc_dapm_widget *w,
 989                   struct snd_kcontrol *kcontrol, int event)
 990 {
 991         struct snd_soc_codec *codec = w->codec;
 992         unsigned int mask = 1 << w->shift;
 993
 994         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 995                             mask, mask);
 996         return 0;
 997 }
 998
 999 static const char *hp_mux_text[] = {
1000         "Mixer",
1001         "DAC",
1002 };
1003
1004 #define WM8994_HP_ENUM(xname, xenum) \
1005 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1006         .info = snd_soc_info_enum_double, \
1007         .get = snd_soc_dapm_get_enum_double, \
1008         .put = wm8994_put_hp_enum, \
1009         .private_value = (unsigned long)&xenum }
1010
1011 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1012                               struct snd_ctl_elem_value *ucontrol)
1013 {
1014         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1015         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1016         struct snd_soc_codec *codec = w->codec;
1017         int ret;
1018
1019         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1020
1021         wm8994_update_class_w(codec);
1022
1023         return ret;
1024 }
1025
1026 static const struct soc_enum hpl_enum =
1027         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1028
1029 static const struct snd_kcontrol_new hpl_mux =
1030         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1031
1032 static const struct soc_enum hpr_enum =
1033         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1034
1035 static const struct snd_kcontrol_new hpr_mux =
1036         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1037
1038 static const char *adc_mux_text[] = {
1039         "ADC",
1040         "DMIC",
1041 };
1042
1043 static const struct soc_enum adc_enum =
1044         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1045
1046 static const struct snd_kcontrol_new adcl_mux =
1047         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1048
1049 static const struct snd_kcontrol_new adcr_mux =
1050         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1051
1052 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1053 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1054 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1055 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1056 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1057 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1058 };
1059
1060 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1061 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1062 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1063 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1064 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1065 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1066 };
1067
1068 /* Debugging; dump chip status after DAPM transitions */
1069 static int post_ev(struct snd_soc_dapm_widget *w,
1070             struct snd_kcontrol *kcontrol, int event)
1071 {
1072         struct snd_soc_codec *codec = w->codec;
1073         dev_dbg(codec->dev, "SRC status: %x\n",
1074                 snd_soc_read(codec,
1075                              WM8994_RATE_STATUS));
1076         return 0;
1077 }
1078
1079 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1080 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1081                 1, 1, 0),
1082 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1083                 0, 1, 0),
1084 };
1085
1086 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1087 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1088                 1, 1, 0),
1089 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1090                 0, 1, 0),
1091 };
1092
1093 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1094 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1095                 1, 1, 0),
1096 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1097                 0, 1, 0),
1098 };
1099
1100 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1101 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1102                 1, 1, 0),
1103 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1104                 0, 1, 0),
1105 };
1106
1107 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1108 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1109                 5, 1, 0),
1110 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1111                 4, 1, 0),
1112 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1113                 2, 1, 0),
1114 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1115                 1, 1, 0),
1116 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1117                 0, 1, 0),
1118 };
1119
1120 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1121 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1122                 5, 1, 0),
1123 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1124                 4, 1, 0),
1125 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1126                 2, 1, 0),
1127 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1128                 1, 1, 0),
1129 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1130                 0, 1, 0),
1131 };
1132
1133 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1134 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1135         .info = snd_soc_info_volsw, \
1136         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1137         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1138
1139 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1140                               struct snd_ctl_elem_value *ucontrol)
1141 {
1142         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1143         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1144         struct snd_soc_codec *codec = w->codec;
1145         int ret;
1146
1147         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1148
1149         wm8994_update_class_w(codec);
1150
1151         return ret;
1152 }
1153
1154 static const struct snd_kcontrol_new dac1l_mix[] = {
1155 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1156                       5, 1, 0),
1157 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1158                       4, 1, 0),
1159 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1160                       2, 1, 0),
1161 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1162                       1, 1, 0),
1163 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1164                       0, 1, 0),
1165 };
1166
1167 static const struct snd_kcontrol_new dac1r_mix[] = {
1168 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1169                       5, 1, 0),
1170 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1171                       4, 1, 0),
1172 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1173                       2, 1, 0),
1174 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1175                       1, 1, 0),
1176 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1177                       0, 1, 0),
1178 };
1179
1180 static const char *sidetone_text[] = {
1181         "ADC/DMIC1", "DMIC2",
1182 };
1183
1184 static const struct soc_enum sidetone1_enum =
1185         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1186
1187 static const struct snd_kcontrol_new sidetone1_mux =
1188         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1189
1190 static const struct soc_enum sidetone2_enum =
1191         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1192
1193 static const struct snd_kcontrol_new sidetone2_mux =
1194         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1195
1196 static const char *aif1dac_text[] = {
1197         "AIF1DACDAT", "AIF3DACDAT",
1198 };
1199
1200 static const struct soc_enum aif1dac_enum =
1201         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1202
1203 static const struct snd_kcontrol_new aif1dac_mux =
1204         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1205
1206 static const char *aif2dac_text[] = {
1207         "AIF2DACDAT", "AIF3DACDAT",
1208 };
1209
1210 static const struct soc_enum aif2dac_enum =
1211         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1212
1213 static const struct snd_kcontrol_new aif2dac_mux =
1214         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1215
1216 static const char *aif2adc_text[] = {
1217         "AIF2ADCDAT", "AIF3DACDAT",
1218 };
1219
1220 static const struct soc_enum aif2adc_enum =
1221         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1222
1223 static const struct snd_kcontrol_new aif2adc_mux =
1224         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1225
1226 static const char *aif3adc_text[] = {
1227         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1228 };
1229
1230 static const struct soc_enum wm8994_aif3adc_enum =
1231         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1232
1233 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1234         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1235
1236 static const struct soc_enum wm8958_aif3adc_enum =
1237         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1238
1239 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1240         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1241
1242 static const char *mono_pcm_out_text[] = {
1243         "None", "AIF2ADCL", "AIF2ADCR",
1244 };
1245
1246 static const struct soc_enum mono_pcm_out_enum =
1247         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1248
1249 static const struct snd_kcontrol_new mono_pcm_out_mux =
1250         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1251
1252 static const char *aif2dac_src_text[] = {
1253         "AIF2", "AIF3",
1254 };
1255
1256 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1257 static const struct soc_enum aif2dacl_src_enum =
1258         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1259
1260 static const struct snd_kcontrol_new aif2dacl_src_mux =
1261         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1262
1263 static const struct soc_enum aif2dacr_src_enum =
1264         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1265
1266 static const struct snd_kcontrol_new aif2dacr_src_mux =
1267         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1268
1269 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1270 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1271         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1272 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1273         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1274
1275 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1276         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1277 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1278         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1279 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1280         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1281 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1282         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1283 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1284         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1285
1286 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1287                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1288                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1289 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1290                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1291                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1292 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1293                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1294 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1295                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1296
1297 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1298 };
1299
1300 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1301 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1302 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1303 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1305                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1306 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1307                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1308 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1309 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1310 };
1311
1312 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1313 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1314         dac_ev, SND_SOC_DAPM_PRE_PMU),
1315 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1316         dac_ev, SND_SOC_DAPM_PRE_PMU),
1317 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1318         dac_ev, SND_SOC_DAPM_PRE_PMU),
1319 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1320         dac_ev, SND_SOC_DAPM_PRE_PMU),
1321 };
1322
1323 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1324 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1325 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1326 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1327 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1328 };
1329
1330 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1331 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1332                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1333 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1334                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1335 };
1336
1337 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1338 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1339 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1340 };
1341
1342 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1343 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1344 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1345 SND_SOC_DAPM_INPUT("Clock"),
1346
1347 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1348                       SND_SOC_DAPM_PRE_PMU),
1349 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1350                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1351
1352 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1353                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1354
1355 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1356 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1357 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1358
1359 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1360                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1361 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1362                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1363 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1364                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1365                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1366 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1367                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1368                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1369
1370 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1371                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1372 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1373                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1374 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1375                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1376                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1377 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1378                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1379                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1380
1381 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1382                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1383 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1384                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1385
1386 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1387                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1388 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1389                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1390
1391 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1392                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1393 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1394                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1395
1396 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1397 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1398
1399 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1400                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1401 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1402                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1403
1404 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1405                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1406 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1407                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1408 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1409                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1410                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1411 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1412                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1413                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1414
1415 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1416 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1417 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1418 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1419
1420 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1421 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1422 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1423
1424 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1425 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1426
1427 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1428
1429 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1430 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1431 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1432 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1433
1434 /* Power is done with the muxes since the ADC power also controls the
1435  * downsampling chain, the chip will automatically manage the analogue
1436  * specific portions.
1437  */
1438 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1439 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1440
1441 SND_SOC_DAPM_POST("Debug log", post_ev),
1442 };
1443
1444 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1445 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1446 };
1447
1448 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1449 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1450 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1451 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1452 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1453 };
1454
1455 static const struct snd_soc_dapm_route intercon[] = {
1456         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1457         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1458
1459         { "DSP1CLK", NULL, "CLK_SYS" },
1460         { "DSP2CLK", NULL, "CLK_SYS" },
1461         { "DSPINTCLK", NULL, "CLK_SYS" },
1462
1463         { "AIF1ADC1L", NULL, "AIF1CLK" },
1464         { "AIF1ADC1L", NULL, "DSP1CLK" },
1465         { "AIF1ADC1R", NULL, "AIF1CLK" },
1466         { "AIF1ADC1R", NULL, "DSP1CLK" },
1467         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1468
1469         { "AIF1DAC1L", NULL, "AIF1CLK" },
1470         { "AIF1DAC1L", NULL, "DSP1CLK" },
1471         { "AIF1DAC1R", NULL, "AIF1CLK" },
1472         { "AIF1DAC1R", NULL, "DSP1CLK" },
1473         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1474
1475         { "AIF1ADC2L", NULL, "AIF1CLK" },
1476         { "AIF1ADC2L", NULL, "DSP1CLK" },
1477         { "AIF1ADC2R", NULL, "AIF1CLK" },
1478         { "AIF1ADC2R", NULL, "DSP1CLK" },
1479         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1480
1481         { "AIF1DAC2L", NULL, "AIF1CLK" },
1482         { "AIF1DAC2L", NULL, "DSP1CLK" },
1483         { "AIF1DAC2R", NULL, "AIF1CLK" },
1484         { "AIF1DAC2R", NULL, "DSP1CLK" },
1485         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1486
1487         { "AIF2ADCL", NULL, "AIF2CLK" },
1488         { "AIF2ADCL", NULL, "DSP2CLK" },
1489         { "AIF2ADCR", NULL, "AIF2CLK" },
1490         { "AIF2ADCR", NULL, "DSP2CLK" },
1491         { "AIF2ADCR", NULL, "DSPINTCLK" },
1492
1493         { "AIF2DACL", NULL, "AIF2CLK" },
1494         { "AIF2DACL", NULL, "DSP2CLK" },
1495         { "AIF2DACR", NULL, "AIF2CLK" },
1496         { "AIF2DACR", NULL, "DSP2CLK" },
1497         { "AIF2DACR", NULL, "DSPINTCLK" },
1498
1499         { "DMIC1L", NULL, "DMIC1DAT" },
1500         { "DMIC1L", NULL, "CLK_SYS" },
1501         { "DMIC1R", NULL, "DMIC1DAT" },
1502         { "DMIC1R", NULL, "CLK_SYS" },
1503         { "DMIC2L", NULL, "DMIC2DAT" },
1504         { "DMIC2L", NULL, "CLK_SYS" },
1505         { "DMIC2R", NULL, "DMIC2DAT" },
1506         { "DMIC2R", NULL, "CLK_SYS" },
1507
1508         { "ADCL", NULL, "AIF1CLK" },
1509         { "ADCL", NULL, "DSP1CLK" },
1510         { "ADCL", NULL, "DSPINTCLK" },
1511
1512         { "ADCR", NULL, "AIF1CLK" },
1513         { "ADCR", NULL, "DSP1CLK" },
1514         { "ADCR", NULL, "DSPINTCLK" },
1515
1516         { "ADCL Mux", "ADC", "ADCL" },
1517         { "ADCL Mux", "DMIC", "DMIC1L" },
1518         { "ADCR Mux", "ADC", "ADCR" },
1519         { "ADCR Mux", "DMIC", "DMIC1R" },
1520
1521         { "DAC1L", NULL, "AIF1CLK" },
1522         { "DAC1L", NULL, "DSP1CLK" },
1523         { "DAC1L", NULL, "DSPINTCLK" },
1524
1525         { "DAC1R", NULL, "AIF1CLK" },
1526         { "DAC1R", NULL, "DSP1CLK" },
1527         { "DAC1R", NULL, "DSPINTCLK" },
1528
1529         { "DAC2L", NULL, "AIF2CLK" },
1530         { "DAC2L", NULL, "DSP2CLK" },
1531         { "DAC2L", NULL, "DSPINTCLK" },
1532
1533         { "DAC2R", NULL, "AIF2DACR" },
1534         { "DAC2R", NULL, "AIF2CLK" },
1535         { "DAC2R", NULL, "DSP2CLK" },
1536         { "DAC2R", NULL, "DSPINTCLK" },
1537
1538         { "TOCLK", NULL, "CLK_SYS" },
1539
1540         /* AIF1 outputs */
1541         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1542         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1543         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1544
1545         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1546         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1547         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1548
1549         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1550         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1551         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1552
1553         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1554         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1555         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1556
1557         /* Pin level routing for AIF3 */
1558         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1559         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1560         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1561         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1562
1563         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1564         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1565         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1566         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1567         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1568         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1569         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1570
1571         /* DAC1 inputs */
1572         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1573         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1574         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1575         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1576         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1577
1578         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1579         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1580         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1581         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1582         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1583
1584         /* DAC2/AIF2 outputs  */
1585         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1586         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1587         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1588         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1589         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1590         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1591
1592         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1593         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1594         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1595         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1596         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1597         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1598
1599         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1600         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1601         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1602         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1603
1604         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1605
1606         /* AIF3 output */
1607         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1608         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1609         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1610         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1611         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1612         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1613         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1614         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1615
1616         /* Sidetone */
1617         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1618         { "Left Sidetone", "DMIC2", "DMIC2L" },
1619         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1620         { "Right Sidetone", "DMIC2", "DMIC2R" },
1621
1622         /* Output stages */
1623         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1624         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1625
1626         { "SPKL", "DAC1 Switch", "DAC1L" },
1627         { "SPKL", "DAC2 Switch", "DAC2L" },
1628
1629         { "SPKR", "DAC1 Switch", "DAC1R" },
1630         { "SPKR", "DAC2 Switch", "DAC2R" },
1631
1632         { "Left Headphone Mux", "DAC", "DAC1L" },
1633         { "Right Headphone Mux", "DAC", "DAC1R" },
1634 };
1635
1636 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1637         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1638         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1639         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1640         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1641         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1642         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1643         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1644         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1645 };
1646
1647 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1648         { "DAC1L", NULL, "DAC1L Mixer" },
1649         { "DAC1R", NULL, "DAC1R Mixer" },
1650         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1651         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1652 };
1653
1654 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1655         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1656         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1657         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1658         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1659         { "MICBIAS1", NULL, "CLK_SYS" },
1660         { "MICBIAS1", NULL, "MICBIAS Supply" },
1661         { "MICBIAS2", NULL, "CLK_SYS" },
1662         { "MICBIAS2", NULL, "MICBIAS Supply" },
1663 };
1664
1665 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1666         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1667         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1668         { "MICBIAS1", NULL, "VMID" },
1669         { "MICBIAS2", NULL, "VMID" },
1670 };
1671
1672 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1673         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1674         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1675
1676         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1677         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1678         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1679         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1680
1681         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1682         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1683
1684         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1685 };
1686
1687 /* The size in bits of the FLL divide multiplied by 10
1688  * to allow rounding later */
1689 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1690
1691 struct fll_div {
1692         u16 outdiv;
1693         u16 n;
1694         u16 k;
1695         u16 clk_ref_div;
1696         u16 fll_fratio;
1697 };
1698
1699 static int wm8994_get_fll_config(struct fll_div *fll,
1700                                  int freq_in, int freq_out)
1701 {
1702         u64 Kpart;
1703         unsigned int K, Ndiv, Nmod;
1704
1705         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1706
1707         /* Scale the input frequency down to <= 13.5MHz */
1708         fll->clk_ref_div = 0;
1709         while (freq_in > 13500000) {
1710                 fll->clk_ref_div++;
1711                 freq_in /= 2;
1712
1713                 if (fll->clk_ref_div > 3)
1714                         return -EINVAL;
1715         }
1716         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1717
1718         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1719         fll->outdiv = 3;
1720         while (freq_out * (fll->outdiv + 1) < 90000000) {
1721                 fll->outdiv++;
1722                 if (fll->outdiv > 63)
1723                         return -EINVAL;
1724         }
1725         freq_out *= fll->outdiv + 1;
1726         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1727
1728         if (freq_in > 1000000) {
1729                 fll->fll_fratio = 0;
1730         } else if (freq_in > 256000) {
1731                 fll->fll_fratio = 1;
1732                 freq_in *= 2;
1733         } else if (freq_in > 128000) {
1734                 fll->fll_fratio = 2;
1735                 freq_in *= 4;
1736         } else if (freq_in > 64000) {
1737                 fll->fll_fratio = 3;
1738                 freq_in *= 8;
1739         } else {
1740                 fll->fll_fratio = 4;
1741                 freq_in *= 16;
1742         }
1743         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1744
1745         /* Now, calculate N.K */
1746         Ndiv = freq_out / freq_in;
1747
1748         fll->n = Ndiv;
1749         Nmod = freq_out % freq_in;
1750         pr_debug("Nmod=%d\n", Nmod);
1751
1752         /* Calculate fractional part - scale up so we can round. */
1753         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1754
1755         do_div(Kpart, freq_in);
1756
1757         K = Kpart & 0xFFFFFFFF;
1758
1759         if ((K % 10) >= 5)
1760                 K += 5;
1761
1762         /* Move down to proper range now rounding is done */
1763         fll->k = K / 10;
1764
1765         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1766
1767         return 0;
1768 }
1769
1770 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1771                           unsigned int freq_in, unsigned int freq_out)
1772 {
1773         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1774         struct wm8994 *control = codec->control_data;
1775         int reg_offset, ret;
1776         struct fll_div fll;
1777         u16 reg, aif1, aif2;
1778         unsigned long timeout;
1779         bool was_enabled;
1780
1781         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1782                 & WM8994_AIF1CLK_ENA;
1783
1784         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1785                 & WM8994_AIF2CLK_ENA;
1786
1787         switch (id) {
1788         case WM8994_FLL1:
1789                 reg_offset = 0;
1790                 id = 0;
1791                 break;
1792         case WM8994_FLL2:
1793                 reg_offset = 0x20;
1794                 id = 1;
1795                 break;
1796         default:
1797                 return -EINVAL;
1798         }
1799
1800         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1801         was_enabled = reg & WM8994_FLL1_ENA;
1802
1803         switch (src) {
1804         case 0:
1805                 /* Allow no source specification when stopping */
1806                 if (freq_out)
1807                         return -EINVAL;
1808                 src = wm8994->fll[id].src;
1809                 break;
1810         case WM8994_FLL_SRC_MCLK1:
1811         case WM8994_FLL_SRC_MCLK2:
1812         case WM8994_FLL_SRC_LRCLK:
1813         case WM8994_FLL_SRC_BCLK:
1814                 break;
1815         default:
1816                 return -EINVAL;
1817         }
1818
1819         /* Are we changing anything? */
1820         if (wm8994->fll[id].src == src &&
1821             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1822                 return 0;
1823
1824         /* If we're stopping the FLL redo the old config - no
1825          * registers will actually be written but we avoid GCC flow
1826          * analysis bugs spewing warnings.
1827          */
1828         if (freq_out)
1829                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1830         else
1831                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1832                                             wm8994->fll[id].out);
1833         if (ret < 0)
1834                 return ret;
1835
1836         /* Gate the AIF clocks while we reclock */
1837         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1838                             WM8994_AIF1CLK_ENA, 0);
1839         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1840                             WM8994_AIF2CLK_ENA, 0);
1841
1842         /* We always need to disable the FLL while reconfiguring */
1843         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1844                             WM8994_FLL1_ENA, 0);
1845
1846         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1847                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1848         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1849                             WM8994_FLL1_OUTDIV_MASK |
1850                             WM8994_FLL1_FRATIO_MASK, reg);
1851
1852         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1853
1854         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1855                             WM8994_FLL1_N_MASK,
1856                                     fll.n << WM8994_FLL1_N_SHIFT);
1857
1858         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1859                             WM8994_FLL1_REFCLK_DIV_MASK |
1860                             WM8994_FLL1_REFCLK_SRC_MASK,
1861                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1862                             (src - 1));
1863
1864         /* Clear any pending completion from a previous failure */
1865         try_wait_for_completion(&wm8994->fll_locked[id]);
1866
1867         /* Enable (with fractional mode if required) */
1868         if (freq_out) {
1869                 /* Enable VMID if we need it */
1870                 if (!was_enabled) {
1871                         switch (control->type) {
1872                         case WM8994:
1873                                 vmid_reference(codec);
1874                                 break;
1875                         case WM8958:
1876                                 if (wm8994->revision < 1)
1877                                         vmid_reference(codec);
1878                                 break;
1879                         default:
1880                                 break;
1881                         }
1882                 }
1883
1884                 if (fll.k)
1885                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1886                 else
1887                         reg = WM8994_FLL1_ENA;
1888                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1889                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1890                                     reg);
1891
1892                 if (wm8994->fll_locked_irq) {
1893                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1894                                                               msecs_to_jiffies(10));
1895                         if (timeout == 0)
1896                                 dev_warn(codec->dev,
1897                                          "Timed out waiting for FLL lock\n");
1898                 } else {
1899                         msleep(5);
1900                 }
1901         } else {
1902                 if (was_enabled) {
1903                         switch (control->type) {
1904                         case WM8994:
1905                                 vmid_dereference(codec);
1906                                 break;
1907                         case WM8958:
1908                                 if (wm8994->revision < 1)
1909                                         vmid_dereference(codec);
1910                                 break;
1911                         default:
1912                                 break;
1913                         }
1914                 }
1915         }
1916
1917         wm8994->fll[id].in = freq_in;
1918         wm8994->fll[id].out = freq_out;
1919         wm8994->fll[id].src = src;
1920
1921         /* Enable any gated AIF clocks */
1922         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1923                             WM8994_AIF1CLK_ENA, aif1);
1924         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1925                             WM8994_AIF2CLK_ENA, aif2);
1926
1927         configure_clock(codec);
1928
1929         return 0;
1930 }
1931
1932 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1933 {
1934         struct completion *completion = data;
1935
1936         complete(completion);
1937
1938         return IRQ_HANDLED;
1939 }
1940
1941 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1942
1943 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1944                           unsigned int freq_in, unsigned int freq_out)
1945 {
1946         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1947 }
1948
1949 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1950                 int clk_id, unsigned int freq, int dir)
1951 {
1952         struct snd_soc_codec *codec = dai->codec;
1953         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1954         int i;
1955
1956         switch (dai->id) {
1957         case 1:
1958         case 2:
1959                 break;
1960
1961         default:
1962                 /* AIF3 shares clocking with AIF1/2 */
1963                 return -EINVAL;
1964         }
1965
1966         switch (clk_id) {
1967         case WM8994_SYSCLK_MCLK1:
1968                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1969                 wm8994->mclk[0] = freq;
1970                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1971                         dai->id, freq);
1972                 break;
1973
1974         case WM8994_SYSCLK_MCLK2:
1975                 /* TODO: Set GPIO AF */
1976                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1977                 wm8994->mclk[1] = freq;
1978                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1979                         dai->id, freq);
1980                 break;
1981
1982         case WM8994_SYSCLK_FLL1:
1983                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1984                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1985                 break;
1986
1987         case WM8994_SYSCLK_FLL2:
1988                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1989                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1990                 break;
1991
1992         case WM8994_SYSCLK_OPCLK:
1993                 /* Special case - a division (times 10) is given and
1994                  * no effect on main clocking.
1995                  */
1996                 if (freq) {
1997                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1998                                 if (opclk_divs[i] == freq)
1999                                         break;
2000                         if (i == ARRAY_SIZE(opclk_divs))
2001                                 return -EINVAL;
2002                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2003                                             WM8994_OPCLK_DIV_MASK, i);
2004                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2005                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2006                 } else {
2007                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2008                                             WM8994_OPCLK_ENA, 0);
2009                 }
2010
2011         default:
2012                 return -EINVAL;
2013         }
2014
2015         configure_clock(codec);
2016
2017         return 0;
2018 }
2019
2020 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2021                                  enum snd_soc_bias_level level)
2022 {
2023         struct wm8994 *control = codec->control_data;
2024         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2025
2026         switch (level) {
2027         case SND_SOC_BIAS_ON:
2028                 break;
2029
2030         case SND_SOC_BIAS_PREPARE:
2031                 break;
2032
2033         case SND_SOC_BIAS_STANDBY:
2034                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2035                         pm_runtime_get_sync(codec->dev);
2036
2037                         switch (control->type) {
2038                         case WM8994:
2039                                 if (wm8994->revision < 4) {
2040                                         /* Tweak DC servo and DSP
2041                                          * configuration for improved
2042                                          * performance. */
2043                                         snd_soc_write(codec, 0x102, 0x3);
2044                                         snd_soc_write(codec, 0x56, 0x3);
2045                                         snd_soc_write(codec, 0x817, 0);
2046                                         snd_soc_write(codec, 0x102, 0);
2047                                 }
2048                                 break;
2049
2050                         case WM8958:
2051                                 if (wm8994->revision == 0) {
2052                                         /* Optimise performance for rev A */
2053                                         snd_soc_write(codec, 0x102, 0x3);
2054                                         snd_soc_write(codec, 0xcb, 0x81);
2055                                         snd_soc_write(codec, 0x817, 0);
2056                                         snd_soc_write(codec, 0x102, 0);
2057
2058                                         snd_soc_update_bits(codec,
2059                                                             WM8958_CHARGE_PUMP_2,
2060                                                             WM8958_CP_DISCH,
2061                                                             WM8958_CP_DISCH);
2062                                 }
2063                                 break;
2064
2065                         case WM1811:
2066                                 if (wm8994->revision < 2) {
2067                                         snd_soc_write(codec, 0x102, 0x3);
2068                                         snd_soc_write(codec, 0x5d, 0x7e);
2069                                         snd_soc_write(codec, 0x5e, 0x0);
2070                                         snd_soc_write(codec, 0x102, 0x0);
2071                                 }
2072                                 break;
2073                         }
2074
2075                         /* Discharge LINEOUT1 & 2 */
2076                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2077                                             WM8994_LINEOUT1_DISCH |
2078                                             WM8994_LINEOUT2_DISCH,
2079                                             WM8994_LINEOUT1_DISCH |
2080                                             WM8994_LINEOUT2_DISCH);
2081                 }
2082
2083
2084                 break;
2085
2086         case SND_SOC_BIAS_OFF:
2087                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2088                         wm8994->cur_fw = NULL;
2089
2090                         pm_runtime_put(codec->dev);
2091                 }
2092                 break;
2093         }
2094         codec->dapm.bias_level = level;
2095         return 0;
2096 }
2097
2098 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2099 {
2100         struct snd_soc_codec *codec = dai->codec;
2101         struct wm8994 *control = codec->control_data;
2102         int ms_reg;
2103         int aif1_reg;
2104         int ms = 0;
2105         int aif1 = 0;
2106
2107         switch (dai->id) {
2108         case 1:
2109                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2110                 aif1_reg = WM8994_AIF1_CONTROL_1;
2111                 break;
2112         case 2:
2113                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2114                 aif1_reg = WM8994_AIF2_CONTROL_1;
2115                 break;
2116         default:
2117                 return -EINVAL;
2118         }
2119
2120         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2121         case SND_SOC_DAIFMT_CBS_CFS:
2122                 break;
2123         case SND_SOC_DAIFMT_CBM_CFM:
2124                 ms = WM8994_AIF1_MSTR;
2125                 break;
2126         default:
2127                 return -EINVAL;
2128         }
2129
2130         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2131         case SND_SOC_DAIFMT_DSP_B:
2132                 aif1 |= WM8994_AIF1_LRCLK_INV;
2133         case SND_SOC_DAIFMT_DSP_A:
2134                 aif1 |= 0x18;
2135                 break;
2136         case SND_SOC_DAIFMT_I2S:
2137                 aif1 |= 0x10;
2138                 break;
2139         case SND_SOC_DAIFMT_RIGHT_J:
2140                 break;
2141         case SND_SOC_DAIFMT_LEFT_J:
2142                 aif1 |= 0x8;
2143                 break;
2144         default:
2145                 return -EINVAL;
2146         }
2147
2148         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2149         case SND_SOC_DAIFMT_DSP_A:
2150         case SND_SOC_DAIFMT_DSP_B:
2151                 /* frame inversion not valid for DSP modes */
2152                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2153                 case SND_SOC_DAIFMT_NB_NF:
2154                         break;
2155                 case SND_SOC_DAIFMT_IB_NF:
2156                         aif1 |= WM8994_AIF1_BCLK_INV;
2157                         break;
2158                 default:
2159                         return -EINVAL;
2160                 }
2161                 break;
2162
2163         case SND_SOC_DAIFMT_I2S:
2164         case SND_SOC_DAIFMT_RIGHT_J:
2165         case SND_SOC_DAIFMT_LEFT_J:
2166                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2167                 case SND_SOC_DAIFMT_NB_NF:
2168                         break;
2169                 case SND_SOC_DAIFMT_IB_IF:
2170                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2171                         break;
2172                 case SND_SOC_DAIFMT_IB_NF:
2173                         aif1 |= WM8994_AIF1_BCLK_INV;
2174                         break;
2175                 case SND_SOC_DAIFMT_NB_IF:
2176                         aif1 |= WM8994_AIF1_LRCLK_INV;
2177                         break;
2178                 default:
2179                         return -EINVAL;
2180                 }
2181                 break;
2182         default:
2183                 return -EINVAL;
2184         }
2185
2186         /* The AIF2 format configuration needs to be mirrored to AIF3
2187          * on WM8958 if it's in use so just do it all the time. */
2188         switch (control->type) {
2189         case WM1811:
2190         case WM8958:
2191                 if (dai->id == 2)
2192                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2193                                             WM8994_AIF1_LRCLK_INV |
2194                                             WM8958_AIF3_FMT_MASK, aif1);
2195                 break;
2196
2197         default:
2198                 break;
2199         }
2200
2201         snd_soc_update_bits(codec, aif1_reg,
2202                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2203                             WM8994_AIF1_FMT_MASK,
2204                             aif1);
2205         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2206                             ms);
2207
2208         return 0;
2209 }
2210
2211 static struct {
2212         int val, rate;
2213 } srs[] = {
2214         { 0,   8000 },
2215         { 1,  11025 },
2216         { 2,  12000 },
2217         { 3,  16000 },
2218         { 4,  22050 },
2219         { 5,  24000 },
2220         { 6,  32000 },
2221         { 7,  44100 },
2222         { 8,  48000 },
2223         { 9,  88200 },
2224         { 10, 96000 },
2225 };
2226
2227 static int fs_ratios[] = {
2228         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2229 };
2230
2231 static int bclk_divs[] = {
2232         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2233         640, 880, 960, 1280, 1760, 1920
2234 };
2235
2236 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2237                             struct snd_pcm_hw_params *params,
2238                             struct snd_soc_dai *dai)
2239 {
2240         struct snd_soc_codec *codec = dai->codec;
2241         struct wm8994 *control = codec->control_data;
2242         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2243         int aif1_reg;
2244         int aif2_reg;
2245         int bclk_reg;
2246         int lrclk_reg;
2247         int rate_reg;
2248         int aif1 = 0;
2249         int aif2 = 0;
2250         int bclk = 0;
2251         int lrclk = 0;
2252         int rate_val = 0;
2253         int id = dai->id - 1;
2254
2255         int i, cur_val, best_val, bclk_rate, best;
2256
2257         switch (dai->id) {
2258         case 1:
2259                 aif1_reg = WM8994_AIF1_CONTROL_1;
2260                 aif2_reg = WM8994_AIF1_CONTROL_2;
2261                 bclk_reg = WM8994_AIF1_BCLK;
2262                 rate_reg = WM8994_AIF1_RATE;
2263                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2264                     wm8994->lrclk_shared[0]) {
2265                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2266                 } else {
2267                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2268                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2269                 }
2270                 break;
2271         case 2:
2272                 aif1_reg = WM8994_AIF2_CONTROL_1;
2273                 aif2_reg = WM8994_AIF2_CONTROL_2;
2274                 bclk_reg = WM8994_AIF2_BCLK;
2275                 rate_reg = WM8994_AIF2_RATE;
2276                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2277                     wm8994->lrclk_shared[1]) {
2278                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2279                 } else {
2280                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2281                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2282                 }
2283                 break;
2284         case 3:
2285                 switch (control->type) {
2286                 case WM1811:
2287                 case WM8958:
2288                         aif1_reg = WM8958_AIF3_CONTROL_1;
2289                         break;
2290                 default:
2291                         return 0;
2292                 }
2293         default:
2294                 return -EINVAL;
2295         }
2296
2297         bclk_rate = params_rate(params) * 2;
2298         switch (params_format(params)) {
2299         case SNDRV_PCM_FORMAT_S16_LE:
2300                 bclk_rate *= 16;
2301                 break;
2302         case SNDRV_PCM_FORMAT_S20_3LE:
2303                 bclk_rate *= 20;
2304                 aif1 |= 0x20;
2305                 break;
2306         case SNDRV_PCM_FORMAT_S24_LE:
2307                 bclk_rate *= 24;
2308                 aif1 |= 0x40;
2309                 break;
2310         case SNDRV_PCM_FORMAT_S32_LE:
2311                 bclk_rate *= 32;
2312                 aif1 |= 0x60;
2313                 break;
2314         default:
2315                 return -EINVAL;
2316         }
2317
2318         /* Try to find an appropriate sample rate; look for an exact match. */
2319         for (i = 0; i < ARRAY_SIZE(srs); i++)
2320                 if (srs[i].rate == params_rate(params))
2321                         break;
2322         if (i == ARRAY_SIZE(srs))
2323                 return -EINVAL;
2324         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2325
2326         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2327         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2328                 dai->id, wm8994->aifclk[id], bclk_rate);
2329
2330         if (params_channels(params) == 1 &&
2331             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2332                 aif2 |= WM8994_AIF1_MONO;
2333
2334         if (wm8994->aifclk[id] == 0) {
2335                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2336                 return -EINVAL;
2337         }
2338
2339         /* AIFCLK/fs ratio; look for a close match in either direction */
2340         best = 0;
2341         best_val = abs((fs_ratios[0] * params_rate(params))
2342                        - wm8994->aifclk[id]);
2343         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2344                 cur_val = abs((fs_ratios[i] * params_rate(params))
2345                               - wm8994->aifclk[id]);
2346                 if (cur_val >= best_val)
2347                         continue;
2348                 best = i;
2349                 best_val = cur_val;
2350         }
2351         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2352                 dai->id, fs_ratios[best]);
2353         rate_val |= best;
2354
2355         /* We may not get quite the right frequency if using
2356          * approximate clocks so look for the closest match that is
2357          * higher than the target (we need to ensure that there enough
2358          * BCLKs to clock out the samples).
2359          */
2360         best = 0;
2361         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2362                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2363                 if (cur_val < 0) /* BCLK table is sorted */
2364                         break;
2365                 best = i;
2366         }
2367         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2368         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2369                 bclk_divs[best], bclk_rate);
2370         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2371
2372         lrclk = bclk_rate / params_rate(params);
2373         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2374                 lrclk, bclk_rate / lrclk);
2375
2376         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2377         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2378         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2379         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2380                             lrclk);
2381         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2382                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2383
2384         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2385                 switch (dai->id) {
2386                 case 1:
2387                         wm8994->dac_rates[0] = params_rate(params);
2388                         wm8994_set_retune_mobile(codec, 0);
2389                         wm8994_set_retune_mobile(codec, 1);
2390                         break;
2391                 case 2:
2392                         wm8994->dac_rates[1] = params_rate(params);
2393                         wm8994_set_retune_mobile(codec, 2);
2394                         break;
2395                 }
2396         }
2397
2398         return 0;
2399 }
2400
2401 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2402                                  struct snd_pcm_hw_params *params,
2403                                  struct snd_soc_dai *dai)
2404 {
2405         struct snd_soc_codec *codec = dai->codec;
2406         struct wm8994 *control = codec->control_data;
2407         int aif1_reg;
2408         int aif1 = 0;
2409
2410         switch (dai->id) {
2411         case 3:
2412                 switch (control->type) {
2413                 case WM1811:
2414                 case WM8958:
2415                         aif1_reg = WM8958_AIF3_CONTROL_1;
2416                         break;
2417                 default:
2418                         return 0;
2419                 }
2420         default:
2421                 return 0;
2422         }
2423
2424         switch (params_format(params)) {
2425         case SNDRV_PCM_FORMAT_S16_LE:
2426                 break;
2427         case SNDRV_PCM_FORMAT_S20_3LE:
2428                 aif1 |= 0x20;
2429                 break;
2430         case SNDRV_PCM_FORMAT_S24_LE:
2431                 aif1 |= 0x40;
2432                 break;
2433         case SNDRV_PCM_FORMAT_S32_LE:
2434                 aif1 |= 0x60;
2435                 break;
2436         default:
2437                 return -EINVAL;
2438         }
2439
2440         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2441 }
2442
2443 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2444                                 struct snd_soc_dai *dai)
2445 {
2446         struct snd_soc_codec *codec = dai->codec;
2447         int rate_reg = 0;
2448
2449         switch (dai->id) {
2450         case 1:
2451                 rate_reg = WM8994_AIF1_RATE;
2452                 break;
2453         case 2:
2454                 rate_reg = WM8994_AIF1_RATE;
2455                 break;
2456         default:
2457                 break;
2458         }
2459
2460         /* If the DAI is idle then configure the divider tree for the
2461          * lowest output rate to save a little power if the clock is
2462          * still active (eg, because it is system clock).
2463          */
2464         if (rate_reg && !dai->playback_active && !dai->capture_active)
2465                 snd_soc_update_bits(codec, rate_reg,
2466                                     WM8994_AIF1_SR_MASK |
2467                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2468 }
2469
2470 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2471 {
2472         struct snd_soc_codec *codec = codec_dai->codec;
2473         int mute_reg;
2474         int reg;
2475
2476         switch (codec_dai->id) {
2477         case 1:
2478                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2479                 break;
2480         case 2:
2481                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2482                 break;
2483         default:
2484                 return -EINVAL;
2485         }
2486
2487         if (mute)
2488                 reg = WM8994_AIF1DAC1_MUTE;
2489         else
2490                 reg = 0;
2491
2492         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2493
2494         return 0;
2495 }
2496
2497 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2498 {
2499         struct snd_soc_codec *codec = codec_dai->codec;
2500         int reg, val, mask;
2501
2502         switch (codec_dai->id) {
2503         case 1:
2504                 reg = WM8994_AIF1_MASTER_SLAVE;
2505                 mask = WM8994_AIF1_TRI;
2506                 break;
2507         case 2:
2508                 reg = WM8994_AIF2_MASTER_SLAVE;
2509                 mask = WM8994_AIF2_TRI;
2510                 break;
2511         case 3:
2512                 reg = WM8994_POWER_MANAGEMENT_6;
2513                 mask = WM8994_AIF3_TRI;
2514                 break;
2515         default:
2516                 return -EINVAL;
2517         }
2518
2519         if (tristate)
2520                 val = mask;
2521         else
2522                 val = 0;
2523
2524         return snd_soc_update_bits(codec, reg, mask, val);
2525 }
2526
2527 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2528 {
2529         struct snd_soc_codec *codec = dai->codec;
2530
2531         /* Disable the pulls on the AIF if we're using it to save power. */
2532         snd_soc_update_bits(codec, WM8994_GPIO_3,
2533                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2534         snd_soc_update_bits(codec, WM8994_GPIO_4,
2535                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2536         snd_soc_update_bits(codec, WM8994_GPIO_5,
2537                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2538
2539         return 0;
2540 }
2541
2542 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2543
2544 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2545                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2546
2547 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2548         .set_sysclk     = wm8994_set_dai_sysclk,
2549         .set_fmt        = wm8994_set_dai_fmt,
2550         .hw_params      = wm8994_hw_params,
2551         .shutdown       = wm8994_aif_shutdown,
2552         .digital_mute   = wm8994_aif_mute,
2553         .set_pll        = wm8994_set_fll,
2554         .set_tristate   = wm8994_set_tristate,
2555 };
2556
2557 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2558         .set_sysclk     = wm8994_set_dai_sysclk,
2559         .set_fmt        = wm8994_set_dai_fmt,
2560         .hw_params      = wm8994_hw_params,
2561         .shutdown       = wm8994_aif_shutdown,
2562         .digital_mute   = wm8994_aif_mute,
2563         .set_pll        = wm8994_set_fll,
2564         .set_tristate   = wm8994_set_tristate,
2565 };
2566
2567 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2568         .hw_params      = wm8994_aif3_hw_params,
2569         .set_tristate   = wm8994_set_tristate,
2570 };
2571
2572 static struct snd_soc_dai_driver wm8994_dai[] = {
2573         {
2574                 .name = "wm8994-aif1",
2575                 .id = 1,
2576                 .playback = {
2577                         .stream_name = "AIF1 Playback",
2578                         .channels_min = 1,
2579                         .channels_max = 2,
2580                         .rates = WM8994_RATES,
2581                         .formats = WM8994_FORMATS,
2582                 },
2583                 .capture = {
2584                         .stream_name = "AIF1 Capture",
2585                         .channels_min = 1,
2586                         .channels_max = 2,
2587                         .rates = WM8994_RATES,
2588                         .formats = WM8994_FORMATS,
2589                  },
2590                 .ops = &wm8994_aif1_dai_ops,
2591         },
2592         {
2593                 .name = "wm8994-aif2",
2594                 .id = 2,
2595                 .playback = {
2596                         .stream_name = "AIF2 Playback",
2597                         .channels_min = 1,
2598                         .channels_max = 2,
2599                         .rates = WM8994_RATES,
2600                         .formats = WM8994_FORMATS,
2601                 },
2602                 .capture = {
2603                         .stream_name = "AIF2 Capture",
2604                         .channels_min = 1,
2605                         .channels_max = 2,
2606                         .rates = WM8994_RATES,
2607                         .formats = WM8994_FORMATS,
2608                 },
2609                 .probe = wm8994_aif2_probe,
2610                 .ops = &wm8994_aif2_dai_ops,
2611         },
2612         {
2613                 .name = "wm8994-aif3",
2614                 .id = 3,
2615                 .playback = {
2616                         .stream_name = "AIF3 Playback",
2617                         .channels_min = 1,
2618                         .channels_max = 2,
2619                         .rates = WM8994_RATES,
2620                         .formats = WM8994_FORMATS,
2621                 },
2622                 .capture = {
2623                         .stream_name = "AIF3 Capture",
2624                         .channels_min = 1,
2625                         .channels_max = 2,
2626                         .rates = WM8994_RATES,
2627                         .formats = WM8994_FORMATS,
2628                 },
2629                 .ops = &wm8994_aif3_dai_ops,
2630         }
2631 };
2632
2633 #ifdef CONFIG_PM
2634 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2635 {
2636         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2637         struct wm8994 *control = codec->control_data;
2638         int i, ret;
2639
2640         switch (control->type) {
2641         case WM8994:
2642                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2643                 break;
2644         case WM1811:
2645         case WM8958:
2646                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2647                                     WM8958_MICD_ENA, 0);
2648                 break;
2649         }
2650
2651         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2652                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2653                        sizeof(struct wm8994_fll_config));
2654                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2655                 if (ret < 0)
2656                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2657                                  i + 1, ret);
2658         }
2659
2660         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2661
2662         return 0;
2663 }
2664
2665 static int wm8994_resume(struct snd_soc_codec *codec)
2666 {
2667         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2668         struct wm8994 *control = codec->control_data;
2669         int i, ret;
2670         unsigned int val, mask;
2671
2672         if (wm8994->revision < 4) {
2673                 /* force a HW read */
2674                 val = wm8994_reg_read(codec->control_data,
2675                                       WM8994_POWER_MANAGEMENT_5);
2676
2677                 /* modify the cache only */
2678                 codec->cache_only = 1;
2679                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2680                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2681                 val &= mask;
2682                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2683                                     mask, val);
2684                 codec->cache_only = 0;
2685         }
2686
2687         /* Restore the registers */
2688         ret = snd_soc_cache_sync(codec);
2689         if (ret != 0)
2690                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2691
2692         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2693
2694         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2695                 if (!wm8994->fll_suspend[i].out)
2696                         continue;
2697
2698                 ret = _wm8994_set_fll(codec, i + 1,
2699                                      wm8994->fll_suspend[i].src,
2700                                      wm8994->fll_suspend[i].in,
2701                                      wm8994->fll_suspend[i].out);
2702                 if (ret < 0)
2703                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2704                                  i + 1, ret);
2705         }
2706
2707         switch (control->type) {
2708         case WM8994:
2709                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2710                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2711                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2712                 break;
2713         case WM1811:
2714         case WM8958:
2715                 if (wm8994->jack_cb)
2716                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2717                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2718                 break;
2719         }
2720
2721         return 0;
2722 }
2723 #else
2724 #define wm8994_suspend NULL
2725 #define wm8994_resume NULL
2726 #endif
2727
2728 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2729 {
2730         struct snd_soc_codec *codec = wm8994->codec;
2731         struct wm8994_pdata *pdata = wm8994->pdata;
2732         struct snd_kcontrol_new controls[] = {
2733                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2734                              wm8994->retune_mobile_enum,
2735                              wm8994_get_retune_mobile_enum,
2736                              wm8994_put_retune_mobile_enum),
2737                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2738                              wm8994->retune_mobile_enum,
2739                              wm8994_get_retune_mobile_enum,
2740                              wm8994_put_retune_mobile_enum),
2741                 SOC_ENUM_EXT("AIF2 EQ Mode",
2742                              wm8994->retune_mobile_enum,
2743                              wm8994_get_retune_mobile_enum,
2744                              wm8994_put_retune_mobile_enum),
2745         };
2746         int ret, i, j;
2747         const char **t;
2748
2749         /* We need an array of texts for the enum API but the number
2750          * of texts is likely to be less than the number of
2751          * configurations due to the sample rate dependency of the
2752          * configurations. */
2753         wm8994->num_retune_mobile_texts = 0;
2754         wm8994->retune_mobile_texts = NULL;
2755         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2756                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2757                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2758                                    wm8994->retune_mobile_texts[j]) == 0)
2759                                 break;
2760                 }
2761
2762                 if (j != wm8994->num_retune_mobile_texts)
2763                         continue;
2764
2765                 /* Expand the array... */
2766                 t = krealloc(wm8994->retune_mobile_texts,
2767                              sizeof(char *) *
2768                              (wm8994->num_retune_mobile_texts + 1),
2769                              GFP_KERNEL);
2770                 if (t == NULL)
2771                         continue;
2772
2773                 /* ...store the new entry... */
2774                 t[wm8994->num_retune_mobile_texts] =
2775                         pdata->retune_mobile_cfgs[i].name;
2776
2777                 /* ...and remember the new version. */
2778                 wm8994->num_retune_mobile_texts++;
2779                 wm8994->retune_mobile_texts = t;
2780         }
2781
2782         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2783                 wm8994->num_retune_mobile_texts);
2784
2785         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2786         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2787
2788         ret = snd_soc_add_controls(wm8994->codec, controls,
2789                                    ARRAY_SIZE(controls));
2790         if (ret != 0)
2791                 dev_err(wm8994->codec->dev,
2792                         "Failed to add ReTune Mobile controls: %d\n", ret);
2793 }
2794
2795 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2796 {
2797         struct snd_soc_codec *codec = wm8994->codec;
2798         struct wm8994_pdata *pdata = wm8994->pdata;
2799         int ret, i;
2800
2801         if (!pdata)
2802                 return;
2803
2804         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2805                                       pdata->lineout2_diff,
2806                                       pdata->lineout1fb,
2807                                       pdata->lineout2fb,
2808                                       pdata->jd_scthr,
2809                                       pdata->jd_thr,
2810                                       pdata->micbias1_lvl,
2811                                       pdata->micbias2_lvl);
2812
2813         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2814
2815         if (pdata->num_drc_cfgs) {
2816                 struct snd_kcontrol_new controls[] = {
2817                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2818                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2819                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2820                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2821                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2822                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2823                 };
2824
2825                 /* We need an array of texts for the enum API */
2826                 wm8994->drc_texts = kmalloc(sizeof(char *)
2827                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2828                 if (!wm8994->drc_texts) {
2829                         dev_err(wm8994->codec->dev,
2830                                 "Failed to allocate %d DRC config texts\n",
2831                                 pdata->num_drc_cfgs);
2832                         return;
2833                 }
2834
2835                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2836                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2837
2838                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2839                 wm8994->drc_enum.texts = wm8994->drc_texts;
2840
2841                 ret = snd_soc_add_controls(wm8994->codec, controls,
2842                                            ARRAY_SIZE(controls));
2843                 if (ret != 0)
2844                         dev_err(wm8994->codec->dev,
2845                                 "Failed to add DRC mode controls: %d\n", ret);
2846
2847                 for (i = 0; i < WM8994_NUM_DRC; i++)
2848                         wm8994_set_drc(codec, i);
2849         }
2850
2851         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2852                 pdata->num_retune_mobile_cfgs);
2853
2854         if (pdata->num_retune_mobile_cfgs)
2855                 wm8994_handle_retune_mobile_pdata(wm8994);
2856         else
2857                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2858                                      ARRAY_SIZE(wm8994_eq_controls));
2859
2860         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2861                 if (pdata->micbias[i]) {
2862                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2863                                 pdata->micbias[i] & 0xffff);
2864                 }
2865         }
2866 }
2867
2868 /**
2869  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2870  *
2871  * @codec:   WM8994 codec
2872  * @jack:    jack to report detection events on
2873  * @micbias: microphone bias to detect on
2874  * @det:     value to report for presence detection
2875  * @shrt:    value to report for short detection
2876  *
2877  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2878  * being used to bring out signals to the processor then only platform
2879  * data configuration is needed for WM8994 and processor GPIOs should
2880  * be configured using snd_soc_jack_add_gpios() instead.
2881  *
2882  * Configuration of detection levels is available via the micbias1_lvl
2883  * and micbias2_lvl platform data members.
2884  */
2885 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2886                       int micbias, int det, int shrt)
2887 {
2888         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2889         struct wm8994_micdet *micdet;
2890         struct wm8994 *control = codec->control_data;
2891         int reg;
2892
2893         if (control->type != WM8994)
2894                 return -EINVAL;
2895
2896         switch (micbias) {
2897         case 1:
2898                 micdet = &wm8994->micdet[0];
2899                 break;
2900         case 2:
2901                 micdet = &wm8994->micdet[1];
2902                 break;
2903         default:
2904                 return -EINVAL;
2905         }
2906
2907         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2908                 micbias, det, shrt);
2909
2910         /* Store the configuration */
2911         micdet->jack = jack;
2912         micdet->det = det;
2913         micdet->shrt = shrt;
2914
2915         /* If either of the jacks is set up then enable detection */
2916         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2917                 reg = WM8994_MICD_ENA;
2918         else
2919                 reg = 0;
2920
2921         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2922
2923         return 0;
2924 }
2925 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2926
2927 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2928 {
2929         struct wm8994_priv *priv = data;
2930         struct snd_soc_codec *codec = priv->codec;
2931         int reg;
2932         int report;
2933
2934 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2935         trace_snd_soc_jack_irq(dev_name(codec->dev));
2936 #endif
2937
2938         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2939         if (reg < 0) {
2940                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2941                         reg);
2942                 return IRQ_HANDLED;
2943         }
2944
2945         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2946
2947         report = 0;
2948         if (reg & WM8994_MIC1_DET_STS)
2949                 report |= priv->micdet[0].det;
2950         if (reg & WM8994_MIC1_SHRT_STS)
2951                 report |= priv->micdet[0].shrt;
2952         snd_soc_jack_report(priv->micdet[0].jack, report,
2953                             priv->micdet[0].det | priv->micdet[0].shrt);
2954
2955         report = 0;
2956         if (reg & WM8994_MIC2_DET_STS)
2957                 report |= priv->micdet[1].det;
2958         if (reg & WM8994_MIC2_SHRT_STS)
2959                 report |= priv->micdet[1].shrt;
2960         snd_soc_jack_report(priv->micdet[1].jack, report,
2961                             priv->micdet[1].det | priv->micdet[1].shrt);
2962
2963         return IRQ_HANDLED;
2964 }
2965
2966 /* Default microphone detection handler for WM8958 - the user can
2967  * override this if they wish.
2968  */
2969 static void wm8958_default_micdet(u16 status, void *data)
2970 {
2971         struct snd_soc_codec *codec = data;
2972         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2973         int report = 0;
2974
2975         /* If nothing present then clear our statuses */
2976         if (!(status & WM8958_MICD_STS))
2977                 goto done;
2978
2979         report = SND_JACK_MICROPHONE;
2980
2981         /* Everything else is buttons; just assign slots */
2982         if (status & 0x1c)
2983                 report |= SND_JACK_BTN_0;
2984
2985 done:
2986         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2987                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2988 }
2989
2990 /**
2991  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2992  *
2993  * @codec:   WM8958 codec
2994  * @jack:    jack to report detection events on
2995  *
2996  * Enable microphone detection functionality for the WM8958.  By
2997  * default simple detection which supports the detection of up to 6
2998  * buttons plus video and microphone functionality is supported.
2999  *
3000  * The WM8958 has an advanced jack detection facility which is able to
3001  * support complex accessory detection, especially when used in
3002  * conjunction with external circuitry.  In order to provide maximum
3003  * flexiblity a callback is provided which allows a completely custom
3004  * detection algorithm.
3005  */
3006 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3007                       wm8958_micdet_cb cb, void *cb_data)
3008 {
3009         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3010         struct wm8994 *control = codec->control_data;
3011
3012         switch (control->type) {
3013         case WM1811:
3014         case WM8958:
3015                 break;
3016         default:
3017                 return -EINVAL;
3018         }
3019
3020         if (jack) {
3021                 if (!cb) {
3022                         dev_dbg(codec->dev, "Using default micdet callback\n");
3023                         cb = wm8958_default_micdet;
3024                         cb_data = codec;
3025                 }
3026
3027                 wm8994->micdet[0].jack = jack;
3028                 wm8994->jack_cb = cb;
3029                 wm8994->jack_cb_data = cb_data;
3030
3031                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3032                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3033         } else {
3034                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3035                                     WM8958_MICD_ENA, 0);
3036         }
3037
3038         return 0;
3039 }
3040 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3041
3042 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3043 {
3044         struct wm8994_priv *wm8994 = data;
3045         struct snd_soc_codec *codec = wm8994->codec;
3046         int reg;
3047
3048         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3049         if (reg < 0) {
3050                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3051                         reg);
3052                 return IRQ_NONE;
3053         }
3054
3055         if (!(reg & WM8958_MICD_VALID)) {
3056                 dev_dbg(codec->dev, "Mic detect data not valid\n");
3057                 goto out;
3058         }
3059
3060 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3061         trace_snd_soc_jack_irq(dev_name(codec->dev));
3062 #endif
3063
3064         if (wm8994->jack_cb)
3065                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3066         else
3067                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3068
3069 out:
3070         return IRQ_HANDLED;
3071 }
3072
3073 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3074 {
3075         struct snd_soc_codec *codec = data;
3076
3077         dev_err(codec->dev, "FIFO error\n");
3078
3079         return IRQ_HANDLED;
3080 }
3081
3082 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3083 {
3084         struct snd_soc_codec *codec = data;
3085
3086         dev_err(codec->dev, "Thermal warning\n");
3087
3088         return IRQ_HANDLED;
3089 }
3090
3091 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3092 {
3093         struct snd_soc_codec *codec = data;
3094
3095         dev_crit(codec->dev, "Thermal shutdown\n");
3096
3097         return IRQ_HANDLED;
3098 }
3099
3100 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3101 {
3102         struct wm8994 *control;
3103         struct wm8994_priv *wm8994;
3104         struct snd_soc_dapm_context *dapm = &codec->dapm;
3105         int ret, i;
3106
3107         codec->control_data = dev_get_drvdata(codec->dev->parent);
3108         control = codec->control_data;
3109
3110         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3111         if (wm8994 == NULL)
3112                 return -ENOMEM;
3113         snd_soc_codec_set_drvdata(codec, wm8994);
3114
3115         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3116         wm8994->codec = codec;
3117
3118         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3119                 init_completion(&wm8994->fll_locked[i]);
3120
3121         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3122                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3123         else if (wm8994->pdata && wm8994->pdata->irq_base)
3124                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3125                                      WM8994_IRQ_MIC1_DET;
3126
3127         pm_runtime_enable(codec->dev);
3128         pm_runtime_resume(codec->dev);
3129
3130         /* Read our current status back from the chip - we don't want to
3131          * reset as this may interfere with the GPIO or LDO operation. */
3132         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3133                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3134                         continue;
3135
3136                 ret = wm8994_reg_read(codec->control_data, i);
3137                 if (ret <= 0)
3138                         continue;
3139
3140                 ret = snd_soc_cache_write(codec, i, ret);
3141                 if (ret != 0) {
3142                         dev_err(codec->dev,
3143                                 "Failed to initialise cache for 0x%x: %d\n",
3144                                 i, ret);
3145                         goto err;
3146                 }
3147         }
3148
3149         /* Set revision-specific configuration */
3150         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3151         switch (control->type) {
3152         case WM8994:
3153                 switch (wm8994->revision) {
3154                 case 2:
3155                 case 3:
3156                         wm8994->hubs.dcs_codes_l = -5;
3157                         wm8994->hubs.dcs_codes_r = -5;
3158                         wm8994->hubs.hp_startup_mode = 1;
3159                         wm8994->hubs.dcs_readback_mode = 1;
3160                         wm8994->hubs.series_startup = 1;
3161                         break;
3162                 default:
3163                         wm8994->hubs.dcs_readback_mode = 2;
3164                         break;
3165                 }
3166                 break;
3167
3168         case WM8958:
3169                 wm8994->hubs.dcs_readback_mode = 1;
3170                 break;
3171
3172         case WM1811:
3173                 wm8994->hubs.dcs_readback_mode = 2;
3174                 wm8994->hubs.no_series_update = 1;
3175
3176                 switch (wm8994->revision) {
3177                 case 0:
3178                 case 1:
3179                         wm8994->hubs.dcs_codes_l = -7;
3180                         wm8994->hubs.dcs_codes_r = -4;
3181                         break;
3182                 default:
3183                         break;
3184                 }
3185
3186                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3187                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3188                 break;
3189
3190         default:
3191                 break;
3192         }
3193
3194         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3195                            wm8994_fifo_error, "FIFO error", codec);
3196         wm8994_request_irq(wm8994->control_data, WM8994_IRQ_TEMP_WARN,
3197                            wm8994_temp_warn, "Thermal warning", codec);
3198         wm8994_request_irq(wm8994->control_data, WM8994_IRQ_TEMP_SHUT,
3199                            wm8994_temp_shut, "Thermal shutdown", codec);
3200
3201         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3202                                  wm_hubs_dcs_done, "DC servo done",
3203                                  &wm8994->hubs);
3204         if (ret == 0)
3205                 wm8994->hubs.dcs_done_irq = true;
3206
3207         switch (control->type) {
3208         case WM8994:
3209                 if (wm8994->micdet_irq) {
3210                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3211                                                    wm8994_mic_irq,
3212                                                    IRQF_TRIGGER_RISING,
3213                                                    "Mic1 detect",
3214                                                    wm8994);
3215                         if (ret != 0)
3216                                 dev_warn(codec->dev,
3217                                          "Failed to request Mic1 detect IRQ: %d\n",
3218                                          ret);
3219                 }
3220
3221                 ret = wm8994_request_irq(codec->control_data,
3222                                          WM8994_IRQ_MIC1_SHRT,
3223                                          wm8994_mic_irq, "Mic 1 short",
3224                                          wm8994);
3225                 if (ret != 0)
3226                         dev_warn(codec->dev,
3227                                  "Failed to request Mic1 short IRQ: %d\n",
3228                                  ret);
3229
3230                 ret = wm8994_request_irq(codec->control_data,
3231                                          WM8994_IRQ_MIC2_DET,
3232                                          wm8994_mic_irq, "Mic 2 detect",
3233                                          wm8994);
3234                 if (ret != 0)
3235                         dev_warn(codec->dev,
3236                                  "Failed to request Mic2 detect IRQ: %d\n",
3237                                  ret);
3238
3239                 ret = wm8994_request_irq(codec->control_data,
3240                                          WM8994_IRQ_MIC2_SHRT,
3241                                          wm8994_mic_irq, "Mic 2 short",
3242                                          wm8994);
3243                 if (ret != 0)
3244                         dev_warn(codec->dev,
3245                                  "Failed to request Mic2 short IRQ: %d\n",
3246                                  ret);
3247                 break;
3248
3249         case WM8958:
3250         case WM1811:
3251                 if (wm8994->micdet_irq) {
3252                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3253                                                    wm8958_mic_irq,
3254                                                    IRQF_TRIGGER_RISING,
3255                                                    "Mic detect",
3256                                                    wm8994);
3257                         if (ret != 0)
3258                                 dev_warn(codec->dev,
3259                                          "Failed to request Mic detect IRQ: %d\n",
3260                                          ret);
3261                 }
3262         }
3263
3264         wm8994->fll_locked_irq = true;
3265         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3266                 ret = wm8994_request_irq(codec->control_data,
3267                                          WM8994_IRQ_FLL1_LOCK + i,
3268                                          wm8994_fll_locked_irq, "FLL lock",
3269                                          &wm8994->fll_locked[i]);
3270                 if (ret != 0)
3271                         wm8994->fll_locked_irq = false;
3272         }
3273
3274         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3275          * configured on init - if a system wants to do this dynamically
3276          * at runtime we can deal with that then.
3277          */
3278         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3279         if (ret < 0) {
3280                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3281                 goto err_irq;
3282         }
3283         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3284                 wm8994->lrclk_shared[0] = 1;
3285                 wm8994_dai[0].symmetric_rates = 1;
3286         } else {
3287                 wm8994->lrclk_shared[0] = 0;
3288         }
3289
3290         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3291         if (ret < 0) {
3292                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3293                 goto err_irq;
3294         }
3295         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3296                 wm8994->lrclk_shared[1] = 1;
3297                 wm8994_dai[1].symmetric_rates = 1;
3298         } else {
3299                 wm8994->lrclk_shared[1] = 0;
3300         }
3301
3302         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3303
3304         /* Latch volume updates (right only; we always do left then right). */
3305         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3306                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3307         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3308                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3309         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3310                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3311         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3312                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3313         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3314                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3315         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3316                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3317         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3318                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3319         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3320                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3321         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3322                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3323         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3324                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3325         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3326                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3327         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3328                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3329         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3330                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3331         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3332                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3333         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3334                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3335         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3336                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3337
3338         /* Set the low bit of the 3D stereo depth so TLV matches */
3339         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3340                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3341                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3342         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3343                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3344                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3345         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3346                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3347                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3348
3349         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3350          * use this; it only affects behaviour on idle TDM clock
3351          * cycles. */
3352         switch (control->type) {
3353         case WM8994:
3354         case WM8958:
3355                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3356                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3357                 break;
3358         default:
3359                 break;
3360         }
3361
3362         wm8994_update_class_w(codec);
3363
3364         wm8994_handle_pdata(wm8994);
3365
3366         wm_hubs_add_analogue_controls(codec);
3367         snd_soc_add_controls(codec, wm8994_snd_controls,
3368                              ARRAY_SIZE(wm8994_snd_controls));
3369         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3370                                   ARRAY_SIZE(wm8994_dapm_widgets));
3371
3372         switch (control->type) {
3373         case WM8994:
3374                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3375                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3376                 if (wm8994->revision < 4) {
3377                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3378                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3379                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3380                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3381                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3382                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3383                 } else {
3384                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3385                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3386                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3387                                                   ARRAY_SIZE(wm8994_adc_widgets));
3388                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3389                                                   ARRAY_SIZE(wm8994_dac_widgets));
3390                 }
3391                 break;
3392         case WM8958:
3393                 snd_soc_add_controls(codec, wm8958_snd_controls,
3394                                      ARRAY_SIZE(wm8958_snd_controls));
3395                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3396                                           ARRAY_SIZE(wm8958_dapm_widgets));
3397                 if (wm8994->revision < 1) {
3398                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3399                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3400                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3401                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3402                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3403                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3404                 } else {
3405                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3406                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3407                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3408                                                   ARRAY_SIZE(wm8994_adc_widgets));
3409                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3410                                                   ARRAY_SIZE(wm8994_dac_widgets));
3411                 }
3412                 break;
3413
3414         case WM1811:
3415                 snd_soc_add_controls(codec, wm8958_snd_controls,
3416                                      ARRAY_SIZE(wm8958_snd_controls));
3417                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3418                                           ARRAY_SIZE(wm8958_dapm_widgets));
3419                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3420                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3421                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3422                                           ARRAY_SIZE(wm8994_adc_widgets));
3423                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3424                                           ARRAY_SIZE(wm8994_dac_widgets));
3425                 break;
3426         }
3427
3428
3429         wm_hubs_add_analogue_routes(codec, 0, 0);
3430         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3431
3432         switch (control->type) {
3433         case WM8994:
3434                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3435                                         ARRAY_SIZE(wm8994_intercon));
3436
3437                 if (wm8994->revision < 4) {
3438                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3439                                                 ARRAY_SIZE(wm8994_revd_intercon));
3440                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3441                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3442                 } else {
3443                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3444                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3445                 }
3446                 break;
3447         case WM8958:
3448                 if (wm8994->revision < 1) {
3449                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3450                                                 ARRAY_SIZE(wm8994_revd_intercon));
3451                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3452                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3453                 } else {
3454                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3455                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3456                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3457                                                 ARRAY_SIZE(wm8958_intercon));
3458                 }
3459
3460                 wm8958_dsp2_init(codec);
3461                 break;
3462         case WM1811:
3463                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3464                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3465                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3466                                         ARRAY_SIZE(wm8958_intercon));
3467                 break;
3468         }
3469
3470         return 0;
3471
3472 err_irq:
3473         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3474         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3475         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3476         if (wm8994->micdet_irq)
3477                 free_irq(wm8994->micdet_irq, wm8994);
3478         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3479                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3480                                 &wm8994->fll_locked[i]);
3481         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3482                         &wm8994->hubs);
3483         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3484         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3485         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3486 err:
3487         kfree(wm8994);
3488         return ret;
3489 }
3490
3491 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3492 {
3493         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3494         struct wm8994 *control = codec->control_data;
3495         int i;
3496
3497         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3498
3499         pm_runtime_disable(codec->dev);
3500
3501         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3502                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3503                                 &wm8994->fll_locked[i]);
3504
3505         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3506                         &wm8994->hubs);
3507         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3508         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_SHUT, codec);
3509         wm8994_free_irq(codec->control_data, WM8994_IRQ_TEMP_WARN, codec);
3510
3511         switch (control->type) {
3512         case WM8994:
3513                 if (wm8994->micdet_irq)
3514                         free_irq(wm8994->micdet_irq, wm8994);
3515                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3516                                 wm8994);
3517                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3518                                 wm8994);
3519                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3520                                 wm8994);
3521                 break;
3522
3523         case WM1811:
3524         case WM8958:
3525                 if (wm8994->micdet_irq)
3526                         free_irq(wm8994->micdet_irq, wm8994);
3527                 break;
3528         }
3529         if (wm8994->mbc)
3530                 release_firmware(wm8994->mbc);
3531         if (wm8994->mbc_vss)
3532                 release_firmware(wm8994->mbc_vss);
3533         if (wm8994->enh_eq)
3534                 release_firmware(wm8994->enh_eq);
3535         kfree(wm8994->retune_mobile_texts);
3536         kfree(wm8994->drc_texts);
3537         kfree(wm8994);
3538
3539         return 0;
3540 }
3541
3542 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3543         .probe =        wm8994_codec_probe,
3544         .remove =       wm8994_codec_remove,
3545         .suspend =      wm8994_suspend,
3546         .resume =       wm8994_resume,
3547         .read =         wm8994_read,
3548         .write =        wm8994_write,
3549         .readable_register = wm8994_readable,
3550         .volatile_register = wm8994_volatile,
3551         .set_bias_level = wm8994_set_bias_level,
3552
3553         .reg_cache_size = WM8994_CACHE_SIZE,
3554         .reg_cache_default = wm8994_reg_defaults,
3555         .reg_word_size = 2,
3556         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3557 };
3558
3559 static int __devinit wm8994_probe(struct platform_device *pdev)
3560 {
3561         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3562                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3563 }
3564
3565 static int __devexit wm8994_remove(struct platform_device *pdev)
3566 {
3567         snd_soc_unregister_codec(&pdev->dev);
3568         return 0;
3569 }
3570
3571 static struct platform_driver wm8994_codec_driver = {
3572         .driver = {
3573                    .name = "wm8994-codec",
3574                    .owner = THIS_MODULE,
3575                    },
3576         .probe = wm8994_probe,
3577         .remove = __devexit_p(wm8994_remove),
3578 };
3579
3580 static __init int wm8994_init(void)
3581 {
3582         return platform_driver_register(&wm8994_codec_driver);
3583 }
3584 module_init(wm8994_init);
3585
3586 static __exit void wm8994_exit(void)
3587 {
3588         platform_driver_unregister(&wm8994_codec_driver);
3589 }
3590 module_exit(wm8994_exit);
3591
3592
3593 MODULE_DESCRIPTION("ASoC WM8994 driver");
3594 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3595 MODULE_LICENSE("GPL");
3596 MODULE_ALIAS("platform:wm8994-codec");