sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = wm8994->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110                 return 1;
 111         default:
 112                 return 0;
 113         }
 114 }
 115
 116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 117         unsigned int value)
 118 {
 119         int ret;
 120
 121         BUG_ON(reg > WM8994_MAX_REGISTER);
 122
 123         if (!wm8994_volatile(codec, reg)) {
 124                 ret = snd_soc_cache_write(codec, reg, value);
 125                 if (ret != 0)
 126                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 127                                 reg, ret);
 128         }
 129
 130         return wm8994_reg_write(codec->control_data, reg, value);
 131 }
 132
 133 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 134                                 unsigned int reg)
 135 {
 136         unsigned int val;
 137         int ret;
 138
 139         BUG_ON(reg > WM8994_MAX_REGISTER);
 140
 141         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 142             reg < codec->driver->reg_cache_size) {
 143                 ret = snd_soc_cache_read(codec, reg, &val);
 144                 if (ret >= 0)
 145                         return val;
 146                 else
 147                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 148                                 reg, ret);
 149         }
 150
 151         return wm8994_reg_read(codec->control_data, reg);
 152 }
 153
 154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 155 {
 156         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 157         int rate;
 158         int reg1 = 0;
 159         int offset;
 160
 161         if (aif)
 162                 offset = 4;
 163         else
 164                 offset = 0;
 165
 166         switch (wm8994->sysclk[aif]) {
 167         case WM8994_SYSCLK_MCLK1:
 168                 rate = wm8994->mclk[0];
 169                 break;
 170
 171         case WM8994_SYSCLK_MCLK2:
 172                 reg1 |= 0x8;
 173                 rate = wm8994->mclk[1];
 174                 break;
 175
 176         case WM8994_SYSCLK_FLL1:
 177                 reg1 |= 0x10;
 178                 rate = wm8994->fll[0].out;
 179                 break;
 180
 181         case WM8994_SYSCLK_FLL2:
 182                 reg1 |= 0x18;
 183                 rate = wm8994->fll[1].out;
 184                 break;
 185
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         if (rate >= 13500000) {
 191                 rate /= 2;
 192                 reg1 |= WM8994_AIF1CLK_DIV;
 193
 194                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 195                         aif + 1, rate);
 196         }
 197
 198         wm8994->aifclk[aif] = rate;
 199
 200         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 201                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 202                             reg1);
 203
 204         return 0;
 205 }
 206
 207 static int configure_clock(struct snd_soc_codec *codec)
 208 {
 209         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 210         int old, new;
 211
 212         /* Bring up the AIF clocks first */
 213         configure_aif_clock(codec, 0);
 214         configure_aif_clock(codec, 1);
 215
 216         /* Then switch CLK_SYS over to the higher of them; a change
 217          * can only happen as a result of a clocking change which can
 218          * only be made outside of DAPM so we can safely redo the
 219          * clocking.
 220          */
 221
 222         /* If they're equal it doesn't matter which is used */
 223         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 224                 return 0;
 225
 226         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 227                 new = WM8994_SYSCLK_SRC;
 228         else
 229                 new = 0;
 230
 231         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 232
 233         /* If there's no change then we're done. */
 234         if (old == new)
 235                 return 0;
 236
 237         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 238
 239         snd_soc_dapm_sync(&codec->dapm);
 240
 241         return 0;
 242 }
 243
 244 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 245                          struct snd_soc_dapm_widget *sink)
 246 {
 247         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 248         const char *clk;
 249
 250         /* Check what we're currently using for CLK_SYS */
 251         if (reg & WM8994_SYSCLK_SRC)
 252                 clk = "AIF2CLK";
 253         else
 254                 clk = "AIF1CLK";
 255
 256         return strcmp(source->name, clk) == 0;
 257 }
 258
 259 static const char *sidetone_hpf_text[] = {
 260         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 261 };
 262
 263 static const struct soc_enum sidetone_hpf =
 264         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 265
 266 static const char *adc_hpf_text[] = {
 267         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 268 };
 269
 270 static const struct soc_enum aif1adc1_hpf =
 271         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 272
 273 static const struct soc_enum aif1adc2_hpf =
 274         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 275
 276 static const struct soc_enum aif2adc_hpf =
 277         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 278
 279 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 280 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 281 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 282 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 283 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 284
 285 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 287         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 288         .put = wm8994_put_drc_sw, \
 289         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 290
 291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 292                              struct snd_ctl_elem_value *ucontrol)
 293 {
 294         struct soc_mixer_control *mc =
 295                 (struct soc_mixer_control *)kcontrol->private_value;
 296         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 297         int mask, ret;
 298
 299         /* Can't enable both ADC and DAC paths simultaneously */
 300         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 301                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 302                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 303         else
 304                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 305
 306         ret = snd_soc_read(codec, mc->reg);
 307         if (ret < 0)
 308                 return ret;
 309         if (ret & mask)
 310                 return -EINVAL;
 311
 312         return snd_soc_put_volsw(kcontrol, ucontrol);
 313 }
 314
 315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 316 {
 317         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 318         struct wm8994_pdata *pdata = wm8994->pdata;
 319         int base = wm8994_drc_base[drc];
 320         int cfg = wm8994->drc_cfg[drc];
 321         int save, i;
 322
 323         /* Save any enables; the configuration should clear them. */
 324         save = snd_soc_read(codec, base);
 325         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 326                 WM8994_AIF1ADC1R_DRC_ENA;
 327
 328         for (i = 0; i < WM8994_DRC_REGS; i++)
 329                 snd_soc_update_bits(codec, base + i, 0xffff,
 330                                     pdata->drc_cfgs[cfg].regs[i]);
 331
 332         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 333                              WM8994_AIF1ADC1L_DRC_ENA |
 334                              WM8994_AIF1ADC1R_DRC_ENA, save);
 335 }
 336
 337 /* Icky as hell but saves code duplication */
 338 static int wm8994_get_drc(const char *name)
 339 {
 340         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 341                 return 0;
 342         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 343                 return 1;
 344         if (strcmp(name, "AIF2DRC Mode") == 0)
 345                 return 2;
 346         return -EINVAL;
 347 }
 348
 349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 350                                struct snd_ctl_elem_value *ucontrol)
 351 {
 352         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 353         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 354         struct wm8994_pdata *pdata = wm8994->pdata;
 355         int drc = wm8994_get_drc(kcontrol->id.name);
 356         int value = ucontrol->value.integer.value[0];
 357
 358         if (drc < 0)
 359                 return drc;
 360
 361         if (value >= pdata->num_drc_cfgs)
 362                 return -EINVAL;
 363
 364         wm8994->drc_cfg[drc] = value;
 365
 366         wm8994_set_drc(codec, drc);
 367
 368         return 0;
 369 }
 370
 371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 372                                struct snd_ctl_elem_value *ucontrol)
 373 {
 374         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 375         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 376         int drc = wm8994_get_drc(kcontrol->id.name);
 377
 378         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 379
 380         return 0;
 381 }
 382
 383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 384 {
 385         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 386         struct wm8994_pdata *pdata = wm8994->pdata;
 387         int base = wm8994_retune_mobile_base[block];
 388         int iface, best, best_val, save, i, cfg;
 389
 390         if (!pdata || !wm8994->num_retune_mobile_texts)
 391                 return;
 392
 393         switch (block) {
 394         case 0:
 395         case 1:
 396                 iface = 0;
 397                 break;
 398         case 2:
 399                 iface = 1;
 400                 break;
 401         default:
 402                 return;
 403         }
 404
 405         /* Find the version of the currently selected configuration
 406          * with the nearest sample rate. */
 407         cfg = wm8994->retune_mobile_cfg[block];
 408         best = 0;
 409         best_val = INT_MAX;
 410         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 411                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 412                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 413                     abs(pdata->retune_mobile_cfgs[i].rate
 414                         - wm8994->dac_rates[iface]) < best_val) {
 415                         best = i;
 416                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 417                                        - wm8994->dac_rates[iface]);
 418                 }
 419         }
 420
 421         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 422                 block,
 423                 pdata->retune_mobile_cfgs[best].name,
 424                 pdata->retune_mobile_cfgs[best].rate,
 425                 wm8994->dac_rates[iface]);
 426
 427         /* The EQ will be disabled while reconfiguring it, remember the
 428          * current configuration.
 429          */
 430         save = snd_soc_read(codec, base);
 431         save &= WM8994_AIF1DAC1_EQ_ENA;
 432
 433         for (i = 0; i < WM8994_EQ_REGS; i++)
 434                 snd_soc_update_bits(codec, base + i, 0xffff,
 435                                 pdata->retune_mobile_cfgs[best].regs[i]);
 436
 437         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 438 }
 439
 440 /* Icky as hell but saves code duplication */
 441 static int wm8994_get_retune_mobile_block(const char *name)
 442 {
 443         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 444                 return 0;
 445         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 446                 return 1;
 447         if (strcmp(name, "AIF2 EQ Mode") == 0)
 448                 return 2;
 449         return -EINVAL;
 450 }
 451
 452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 453                                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 457         struct wm8994_pdata *pdata = wm8994->pdata;
 458         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 459         int value = ucontrol->value.integer.value[0];
 460
 461         if (block < 0)
 462                 return block;
 463
 464         if (value >= pdata->num_retune_mobile_cfgs)
 465                 return -EINVAL;
 466
 467         wm8994->retune_mobile_cfg[block] = value;
 468
 469         wm8994_set_retune_mobile(codec, block);
 470
 471         return 0;
 472 }
 473
 474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 475                                          struct snd_ctl_elem_value *ucontrol)
 476 {
 477         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 478         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 479         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 480
 481         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 482
 483         return 0;
 484 }
 485
 486 static const char *aif_chan_src_text[] = {
 487         "Left", "Right"
 488 };
 489
 490 static const struct soc_enum aif1adcl_src =
 491         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 492
 493 static const struct soc_enum aif1adcr_src =
 494         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 495
 496 static const struct soc_enum aif2adcl_src =
 497         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 498
 499 static const struct soc_enum aif2adcr_src =
 500         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 501
 502 static const struct soc_enum aif1dacl_src =
 503         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 504
 505 static const struct soc_enum aif1dacr_src =
 506         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 507
 508 static const struct soc_enum aif2dacl_src =
 509         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 510
 511 static const struct soc_enum aif2dacr_src =
 512         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 513
 514 static const char *osr_text[] = {
 515         "Low Power", "High Performance",
 516 };
 517
 518 static const struct soc_enum dac_osr =
 519         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 520
 521 static const struct soc_enum adc_osr =
 522         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 523
 524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 526                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 527                  1, 119, 0, digital_tlv),
 528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 529                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 530                  1, 119, 0, digital_tlv),
 531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 532                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 533                  1, 119, 0, digital_tlv),
 534
 535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 539
 540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 542 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 543 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 544
 545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 546                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 548                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 550                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551
 552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 554
 555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 558
 559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 570
 571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 572                5, 12, 0, st_tlv),
 573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 574                0, 12, 0, st_tlv),
 575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 581
 582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 584
 585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 587
 588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 590
 591 SOC_ENUM("ADC OSR", adc_osr),
 592 SOC_ENUM("DAC OSR", dac_osr),
 593
 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 595                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 597              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 598
 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 600                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 602              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 603
 604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 605                6, 1, 1, wm_hubs_spkmix_tlv),
 606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 607                2, 1, 1, wm_hubs_spkmix_tlv),
 608
 609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 610                6, 1, 1, wm_hubs_spkmix_tlv),
 611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 612                2, 1, 1, wm_hubs_spkmix_tlv),
 613
 614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 615                10, 15, 0, wm8994_3d_tlv),
 616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 617            8, 1, 0),
 618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 625            8, 1, 0),
 626 };
 627
 628 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 630                eq_tlv),
 631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 632                eq_tlv),
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 638                eq_tlv),
 639
 640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661 };
 662
 663 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 664 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 665 };
 666
 667 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 668                          struct snd_kcontrol *kcontrol, int event)
 669 {
 670         struct snd_soc_codec *codec = w->codec;
 671
 672         switch (event) {
 673         case SND_SOC_DAPM_PRE_PMU:
 674                 return configure_clock(codec);
 675
 676         case SND_SOC_DAPM_POST_PMD:
 677                 configure_clock(codec);
 678                 break;
 679         }
 680
 681         return 0;
 682 }
 683
 684 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 685 {
 686         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 687         int enable = 1;
 688         int source = 0;  /* GCC flow analysis can't track enable */
 689         int reg, reg_r;
 690
 691         /* Only support direct DAC->headphone paths */
 692         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 693         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 694                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 695                 enable = 0;
 696         }
 697
 698         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 699         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 700                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 701                 enable = 0;
 702         }
 703
 704         /* We also need the same setting for L/R and only one path */
 705         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 706         switch (reg) {
 707         case WM8994_AIF2DACL_TO_DAC1L:
 708                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 709                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 710                 break;
 711         case WM8994_AIF1DAC2L_TO_DAC1L:
 712                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 713                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 714                 break;
 715         case WM8994_AIF1DAC1L_TO_DAC1L:
 716                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 717                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 718                 break;
 719         default:
 720                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 721                 enable = 0;
 722                 break;
 723         }
 724
 725         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 726         if (reg_r != reg) {
 727                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 728                 enable = 0;
 729         }
 730
 731         if (enable) {
 732                 dev_dbg(codec->dev, "Class W enabled\n");
 733                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 734                                     WM8994_CP_DYN_PWR |
 735                                     WM8994_CP_DYN_SRC_SEL_MASK,
 736                                     source | WM8994_CP_DYN_PWR);
 737                 wm8994->hubs.class_w = true;
 738
 739         } else {
 740                 dev_dbg(codec->dev, "Class W disabled\n");
 741                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 742                                     WM8994_CP_DYN_PWR, 0);
 743                 wm8994->hubs.class_w = false;
 744         }
 745 }
 746
 747 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 748                           struct snd_kcontrol *kcontrol, int event)
 749 {
 750         struct snd_soc_codec *codec = w->codec;
 751         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 752
 753         switch (event) {
 754         case SND_SOC_DAPM_PRE_PMU:
 755                 if (wm8994->aif1clk_enable) {
 756                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 757                                             WM8994_AIF1CLK_ENA_MASK,
 758                                             WM8994_AIF1CLK_ENA);
 759                         wm8994->aif1clk_enable = 0;
 760                 }
 761                 if (wm8994->aif2clk_enable) {
 762                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 763                                             WM8994_AIF2CLK_ENA_MASK,
 764                                             WM8994_AIF2CLK_ENA);
 765                         wm8994->aif2clk_enable = 0;
 766                 }
 767                 break;
 768         }
 769
 770         /* We may also have postponed startup of DSP, handle that. */
 771         wm8958_aif_ev(w, kcontrol, event);
 772
 773         return 0;
 774 }
 775
 776 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 777                            struct snd_kcontrol *kcontrol, int event)
 778 {
 779         struct snd_soc_codec *codec = w->codec;
 780         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 781
 782         switch (event) {
 783         case SND_SOC_DAPM_POST_PMD:
 784                 if (wm8994->aif1clk_disable) {
 785                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 786                                             WM8994_AIF1CLK_ENA_MASK, 0);
 787                         wm8994->aif1clk_disable = 0;
 788                 }
 789                 if (wm8994->aif2clk_disable) {
 790                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 791                                             WM8994_AIF2CLK_ENA_MASK, 0);
 792                         wm8994->aif2clk_disable = 0;
 793                 }
 794                 break;
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 801                       struct snd_kcontrol *kcontrol, int event)
 802 {
 803         struct snd_soc_codec *codec = w->codec;
 804         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 805
 806         switch (event) {
 807         case SND_SOC_DAPM_PRE_PMU:
 808                 wm8994->aif1clk_enable = 1;
 809                 break;
 810         case SND_SOC_DAPM_POST_PMD:
 811                 wm8994->aif1clk_disable = 1;
 812                 break;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 819                       struct snd_kcontrol *kcontrol, int event)
 820 {
 821         struct snd_soc_codec *codec = w->codec;
 822         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 823
 824         switch (event) {
 825         case SND_SOC_DAPM_PRE_PMU:
 826                 wm8994->aif2clk_enable = 1;
 827                 break;
 828         case SND_SOC_DAPM_POST_PMD:
 829                 wm8994->aif2clk_disable = 1;
 830                 break;
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 837                       struct snd_kcontrol *kcontrol, int event)
 838 {
 839         late_enable_ev(w, kcontrol, event);
 840         return 0;
 841 }
 842
 843 static int micbias_ev(struct snd_soc_dapm_widget *w,
 844                       struct snd_kcontrol *kcontrol, int event)
 845 {
 846         late_enable_ev(w, kcontrol, event);
 847         return 0;
 848 }
 849
 850 static int dac_ev(struct snd_soc_dapm_widget *w,
 851                   struct snd_kcontrol *kcontrol, int event)
 852 {
 853         struct snd_soc_codec *codec = w->codec;
 854         unsigned int mask = 1 << w->shift;
 855
 856         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 857                             mask, mask);
 858         return 0;
 859 }
 860
 861 static const char *hp_mux_text[] = {
 862         "Mixer",
 863         "DAC",
 864 };
 865
 866 #define WM8994_HP_ENUM(xname, xenum) \
 867 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 868         .info = snd_soc_info_enum_double, \
 869         .get = snd_soc_dapm_get_enum_double, \
 870         .put = wm8994_put_hp_enum, \
 871         .private_value = (unsigned long)&xenum }
 872
 873 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 874                               struct snd_ctl_elem_value *ucontrol)
 875 {
 876         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 877         struct snd_soc_dapm_widget *w = wlist->widgets[0];
 878         struct snd_soc_codec *codec = w->codec;
 879         int ret;
 880
 881         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 882
 883         wm8994_update_class_w(codec);
 884
 885         return ret;
 886 }
 887
 888 static const struct soc_enum hpl_enum =
 889         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 890
 891 static const struct snd_kcontrol_new hpl_mux =
 892         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 893
 894 static const struct soc_enum hpr_enum =
 895         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 896
 897 static const struct snd_kcontrol_new hpr_mux =
 898         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 899
 900 static const char *adc_mux_text[] = {
 901         "ADC",
 902         "DMIC",
 903 };
 904
 905 static const struct soc_enum adc_enum =
 906         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 907
 908 static const struct snd_kcontrol_new adcl_mux =
 909         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 910
 911 static const struct snd_kcontrol_new adcr_mux =
 912         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 913
 914 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 915 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 916 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 917 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 918 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 919 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 920 };
 921
 922 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 923 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 924 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 925 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 926 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 927 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 928 };
 929
 930 /* Debugging; dump chip status after DAPM transitions */
 931 static int post_ev(struct snd_soc_dapm_widget *w,
 932             struct snd_kcontrol *kcontrol, int event)
 933 {
 934         struct snd_soc_codec *codec = w->codec;
 935         dev_dbg(codec->dev, "SRC status: %x\n",
 936                 snd_soc_read(codec,
 937                              WM8994_RATE_STATUS));
 938         return 0;
 939 }
 940
 941 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 942 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 943                 1, 1, 0),
 944 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 945                 0, 1, 0),
 946 };
 947
 948 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 949 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 950                 1, 1, 0),
 951 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 952                 0, 1, 0),
 953 };
 954
 955 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 956 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 957                 1, 1, 0),
 958 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 959                 0, 1, 0),
 960 };
 961
 962 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
 963 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 964                 1, 1, 0),
 965 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 966                 0, 1, 0),
 967 };
 968
 969 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
 970 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 971                 5, 1, 0),
 972 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 973                 4, 1, 0),
 974 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 975                 2, 1, 0),
 976 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 977                 1, 1, 0),
 978 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 979                 0, 1, 0),
 980 };
 981
 982 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
 983 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 984                 5, 1, 0),
 985 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 986                 4, 1, 0),
 987 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 988                 2, 1, 0),
 989 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 990                 1, 1, 0),
 991 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 992                 0, 1, 0),
 993 };
 994
 995 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
 996 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 997         .info = snd_soc_info_volsw, \
 998         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
 999         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1000
1001 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1002                               struct snd_ctl_elem_value *ucontrol)
1003 {
1004         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1005         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1006         struct snd_soc_codec *codec = w->codec;
1007         int ret;
1008
1009         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1010
1011         wm8994_update_class_w(codec);
1012
1013         return ret;
1014 }
1015
1016 static const struct snd_kcontrol_new dac1l_mix[] = {
1017 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1018                       5, 1, 0),
1019 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1020                       4, 1, 0),
1021 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022                       2, 1, 0),
1023 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024                       1, 1, 0),
1025 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026                       0, 1, 0),
1027 };
1028
1029 static const struct snd_kcontrol_new dac1r_mix[] = {
1030 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1031                       5, 1, 0),
1032 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1033                       4, 1, 0),
1034 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035                       2, 1, 0),
1036 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037                       1, 1, 0),
1038 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039                       0, 1, 0),
1040 };
1041
1042 static const char *sidetone_text[] = {
1043         "ADC/DMIC1", "DMIC2",
1044 };
1045
1046 static const struct soc_enum sidetone1_enum =
1047         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1048
1049 static const struct snd_kcontrol_new sidetone1_mux =
1050         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1051
1052 static const struct soc_enum sidetone2_enum =
1053         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1054
1055 static const struct snd_kcontrol_new sidetone2_mux =
1056         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1057
1058 static const char *aif1dac_text[] = {
1059         "AIF1DACDAT", "AIF3DACDAT",
1060 };
1061
1062 static const struct soc_enum aif1dac_enum =
1063         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1064
1065 static const struct snd_kcontrol_new aif1dac_mux =
1066         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1067
1068 static const char *aif2dac_text[] = {
1069         "AIF2DACDAT", "AIF3DACDAT",
1070 };
1071
1072 static const struct soc_enum aif2dac_enum =
1073         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1074
1075 static const struct snd_kcontrol_new aif2dac_mux =
1076         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1077
1078 static const char *aif2adc_text[] = {
1079         "AIF2ADCDAT", "AIF3DACDAT",
1080 };
1081
1082 static const struct soc_enum aif2adc_enum =
1083         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1084
1085 static const struct snd_kcontrol_new aif2adc_mux =
1086         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1087
1088 static const char *aif3adc_text[] = {
1089         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1090 };
1091
1092 static const struct soc_enum wm8994_aif3adc_enum =
1093         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1094
1095 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1096         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1097
1098 static const struct soc_enum wm8958_aif3adc_enum =
1099         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1100
1101 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1102         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1103
1104 static const char *mono_pcm_out_text[] = {
1105         "None", "AIF2ADCL", "AIF2ADCR",
1106 };
1107
1108 static const struct soc_enum mono_pcm_out_enum =
1109         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1110
1111 static const struct snd_kcontrol_new mono_pcm_out_mux =
1112         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1113
1114 static const char *aif2dac_src_text[] = {
1115         "AIF2", "AIF3",
1116 };
1117
1118 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1119 static const struct soc_enum aif2dacl_src_enum =
1120         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1121
1122 static const struct snd_kcontrol_new aif2dacl_src_mux =
1123         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1124
1125 static const struct soc_enum aif2dacr_src_enum =
1126         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1127
1128 static const struct snd_kcontrol_new aif2dacr_src_mux =
1129         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1130
1131 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1132 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1133         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1134 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1135         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1136
1137 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1138         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1139 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1140         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1141 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1146         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147
1148 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1149                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1150                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1151 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1152                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1153                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1154 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1155                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1156 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1157                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1158
1159 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1160 };
1161
1162 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1163 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1164 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1165 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1166 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1167                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1168 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1169                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1170 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1171 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1172 };
1173
1174 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1175 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1176         dac_ev, SND_SOC_DAPM_PRE_PMU),
1177 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1178         dac_ev, SND_SOC_DAPM_PRE_PMU),
1179 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1180         dac_ev, SND_SOC_DAPM_PRE_PMU),
1181 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1182         dac_ev, SND_SOC_DAPM_PRE_PMU),
1183 };
1184
1185 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1186 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1187 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1188 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1189 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1190 };
1191
1192 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1193 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1194                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1195 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1196                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1197 };
1198
1199 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1200 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1201 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1202 };
1203
1204 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1205 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1206 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1207 SND_SOC_DAPM_INPUT("Clock"),
1208
1209 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1210 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1211                       SND_SOC_DAPM_PRE_PMU),
1212
1213 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1214                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1215
1216 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1217 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1218 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1219
1220 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1221                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1222 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1223                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1224 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1225                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1226                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1227 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1228                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1229                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1230
1231 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1232                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1233 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1234                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1235 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1236                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1237                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1238 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1239                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1240                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1241
1242 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1243                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1244 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1245                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1246
1247 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1248                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1249 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1250                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1251
1252 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1253                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1254 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1255                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1256
1257 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1258 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1259
1260 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1261                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1262 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1263                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1264
1265 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1266                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1267 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1268                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1269 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1270                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1271                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1272 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1273                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1274                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1275
1276 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1277 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1278 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1279 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1280
1281 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1282 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1283 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1284
1285 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1286 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1287
1288 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1289
1290 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1291 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1292 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1293 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1294
1295 /* Power is done with the muxes since the ADC power also controls the
1296  * downsampling chain, the chip will automatically manage the analogue
1297  * specific portions.
1298  */
1299 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1300 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1301
1302 SND_SOC_DAPM_POST("Debug log", post_ev),
1303 };
1304
1305 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1306 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1307 };
1308
1309 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1310 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1311 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1312 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1313 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1314 };
1315
1316 static const struct snd_soc_dapm_route intercon[] = {
1317         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1318         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1319
1320         { "DSP1CLK", NULL, "CLK_SYS" },
1321         { "DSP2CLK", NULL, "CLK_SYS" },
1322         { "DSPINTCLK", NULL, "CLK_SYS" },
1323
1324         { "AIF1ADC1L", NULL, "AIF1CLK" },
1325         { "AIF1ADC1L", NULL, "DSP1CLK" },
1326         { "AIF1ADC1R", NULL, "AIF1CLK" },
1327         { "AIF1ADC1R", NULL, "DSP1CLK" },
1328         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1329
1330         { "AIF1DAC1L", NULL, "AIF1CLK" },
1331         { "AIF1DAC1L", NULL, "DSP1CLK" },
1332         { "AIF1DAC1R", NULL, "AIF1CLK" },
1333         { "AIF1DAC1R", NULL, "DSP1CLK" },
1334         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1335
1336         { "AIF1ADC2L", NULL, "AIF1CLK" },
1337         { "AIF1ADC2L", NULL, "DSP1CLK" },
1338         { "AIF1ADC2R", NULL, "AIF1CLK" },
1339         { "AIF1ADC2R", NULL, "DSP1CLK" },
1340         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1341
1342         { "AIF1DAC2L", NULL, "AIF1CLK" },
1343         { "AIF1DAC2L", NULL, "DSP1CLK" },
1344         { "AIF1DAC2R", NULL, "AIF1CLK" },
1345         { "AIF1DAC2R", NULL, "DSP1CLK" },
1346         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1347
1348         { "AIF2ADCL", NULL, "AIF2CLK" },
1349         { "AIF2ADCL", NULL, "DSP2CLK" },
1350         { "AIF2ADCR", NULL, "AIF2CLK" },
1351         { "AIF2ADCR", NULL, "DSP2CLK" },
1352         { "AIF2ADCR", NULL, "DSPINTCLK" },
1353
1354         { "AIF2DACL", NULL, "AIF2CLK" },
1355         { "AIF2DACL", NULL, "DSP2CLK" },
1356         { "AIF2DACR", NULL, "AIF2CLK" },
1357         { "AIF2DACR", NULL, "DSP2CLK" },
1358         { "AIF2DACR", NULL, "DSPINTCLK" },
1359
1360         { "DMIC1L", NULL, "DMIC1DAT" },
1361         { "DMIC1L", NULL, "CLK_SYS" },
1362         { "DMIC1R", NULL, "DMIC1DAT" },
1363         { "DMIC1R", NULL, "CLK_SYS" },
1364         { "DMIC2L", NULL, "DMIC2DAT" },
1365         { "DMIC2L", NULL, "CLK_SYS" },
1366         { "DMIC2R", NULL, "DMIC2DAT" },
1367         { "DMIC2R", NULL, "CLK_SYS" },
1368
1369         { "ADCL", NULL, "AIF1CLK" },
1370         { "ADCL", NULL, "DSP1CLK" },
1371         { "ADCL", NULL, "DSPINTCLK" },
1372
1373         { "ADCR", NULL, "AIF1CLK" },
1374         { "ADCR", NULL, "DSP1CLK" },
1375         { "ADCR", NULL, "DSPINTCLK" },
1376
1377         { "ADCL Mux", "ADC", "ADCL" },
1378         { "ADCL Mux", "DMIC", "DMIC1L" },
1379         { "ADCR Mux", "ADC", "ADCR" },
1380         { "ADCR Mux", "DMIC", "DMIC1R" },
1381
1382         { "DAC1L", NULL, "AIF1CLK" },
1383         { "DAC1L", NULL, "DSP1CLK" },
1384         { "DAC1L", NULL, "DSPINTCLK" },
1385
1386         { "DAC1R", NULL, "AIF1CLK" },
1387         { "DAC1R", NULL, "DSP1CLK" },
1388         { "DAC1R", NULL, "DSPINTCLK" },
1389
1390         { "DAC2L", NULL, "AIF2CLK" },
1391         { "DAC2L", NULL, "DSP2CLK" },
1392         { "DAC2L", NULL, "DSPINTCLK" },
1393
1394         { "DAC2R", NULL, "AIF2DACR" },
1395         { "DAC2R", NULL, "AIF2CLK" },
1396         { "DAC2R", NULL, "DSP2CLK" },
1397         { "DAC2R", NULL, "DSPINTCLK" },
1398
1399         { "TOCLK", NULL, "CLK_SYS" },
1400
1401         /* AIF1 outputs */
1402         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1403         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1404         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1405
1406         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1407         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1408         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1409
1410         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1411         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1412         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1413
1414         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1415         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1416         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1417
1418         /* Pin level routing for AIF3 */
1419         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1420         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1421         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1422         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1423
1424         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1425         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1426         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1427         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1428         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1429         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1430         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1431
1432         /* DAC1 inputs */
1433         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1434         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1435         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1436         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1437         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1438
1439         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1440         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1441         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1442         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1443         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1444
1445         /* DAC2/AIF2 outputs  */
1446         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1447         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1448         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1449         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1450         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1451         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1452
1453         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1454         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1455         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1456         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1457         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1458         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1459
1460         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1461         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1462         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1463         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1464
1465         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1466
1467         /* AIF3 output */
1468         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1469         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1470         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1471         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1472         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1473         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1474         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1475         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1476
1477         /* Sidetone */
1478         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1479         { "Left Sidetone", "DMIC2", "DMIC2L" },
1480         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1481         { "Right Sidetone", "DMIC2", "DMIC2R" },
1482
1483         /* Output stages */
1484         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1485         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1486
1487         { "SPKL", "DAC1 Switch", "DAC1L" },
1488         { "SPKL", "DAC2 Switch", "DAC2L" },
1489
1490         { "SPKR", "DAC1 Switch", "DAC1R" },
1491         { "SPKR", "DAC2 Switch", "DAC2R" },
1492
1493         { "Left Headphone Mux", "DAC", "DAC1L" },
1494         { "Right Headphone Mux", "DAC", "DAC1R" },
1495 };
1496
1497 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1498         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1499         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1500         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1501         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1502         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1503         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1504         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1505         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1506 };
1507
1508 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1509         { "DAC1L", NULL, "DAC1L Mixer" },
1510         { "DAC1R", NULL, "DAC1R Mixer" },
1511         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1512         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1513 };
1514
1515 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1516         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1517         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1518         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1519         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1520         { "MICBIAS", NULL, "CLK_SYS" },
1521         { "MICBIAS", NULL, "MICBIAS Supply" },
1522 };
1523
1524 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1525         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1526         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1527 };
1528
1529 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1530         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1531         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1532
1533         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1534         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1535         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1536         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1537
1538         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1539         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1540
1541         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1542 };
1543
1544 /* The size in bits of the FLL divide multiplied by 10
1545  * to allow rounding later */
1546 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1547
1548 struct fll_div {
1549         u16 outdiv;
1550         u16 n;
1551         u16 k;
1552         u16 clk_ref_div;
1553         u16 fll_fratio;
1554 };
1555
1556 static int wm8994_get_fll_config(struct fll_div *fll,
1557                                  int freq_in, int freq_out)
1558 {
1559         u64 Kpart;
1560         unsigned int K, Ndiv, Nmod;
1561
1562         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1563
1564         /* Scale the input frequency down to <= 13.5MHz */
1565         fll->clk_ref_div = 0;
1566         while (freq_in > 13500000) {
1567                 fll->clk_ref_div++;
1568                 freq_in /= 2;
1569
1570                 if (fll->clk_ref_div > 3)
1571                         return -EINVAL;
1572         }
1573         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1574
1575         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1576         fll->outdiv = 3;
1577         while (freq_out * (fll->outdiv + 1) < 90000000) {
1578                 fll->outdiv++;
1579                 if (fll->outdiv > 63)
1580                         return -EINVAL;
1581         }
1582         freq_out *= fll->outdiv + 1;
1583         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1584
1585         if (freq_in > 1000000) {
1586                 fll->fll_fratio = 0;
1587         } else if (freq_in > 256000) {
1588                 fll->fll_fratio = 1;
1589                 freq_in *= 2;
1590         } else if (freq_in > 128000) {
1591                 fll->fll_fratio = 2;
1592                 freq_in *= 4;
1593         } else if (freq_in > 64000) {
1594                 fll->fll_fratio = 3;
1595                 freq_in *= 8;
1596         } else {
1597                 fll->fll_fratio = 4;
1598                 freq_in *= 16;
1599         }
1600         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1601
1602         /* Now, calculate N.K */
1603         Ndiv = freq_out / freq_in;
1604
1605         fll->n = Ndiv;
1606         Nmod = freq_out % freq_in;
1607         pr_debug("Nmod=%d\n", Nmod);
1608
1609         /* Calculate fractional part - scale up so we can round. */
1610         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1611
1612         do_div(Kpart, freq_in);
1613
1614         K = Kpart & 0xFFFFFFFF;
1615
1616         if ((K % 10) >= 5)
1617                 K += 5;
1618
1619         /* Move down to proper range now rounding is done */
1620         fll->k = K / 10;
1621
1622         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1623
1624         return 0;
1625 }
1626
1627 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1628                           unsigned int freq_in, unsigned int freq_out)
1629 {
1630         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1631         int reg_offset, ret;
1632         struct fll_div fll;
1633         u16 reg, aif1, aif2;
1634         unsigned long timeout;
1635
1636         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1637                 & WM8994_AIF1CLK_ENA;
1638
1639         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1640                 & WM8994_AIF2CLK_ENA;
1641
1642         switch (id) {
1643         case WM8994_FLL1:
1644                 reg_offset = 0;
1645                 id = 0;
1646                 break;
1647         case WM8994_FLL2:
1648                 reg_offset = 0x20;
1649                 id = 1;
1650                 break;
1651         default:
1652                 return -EINVAL;
1653         }
1654
1655         switch (src) {
1656         case 0:
1657                 /* Allow no source specification when stopping */
1658                 if (freq_out)
1659                         return -EINVAL;
1660                 src = wm8994->fll[id].src;
1661                 break;
1662         case WM8994_FLL_SRC_MCLK1:
1663         case WM8994_FLL_SRC_MCLK2:
1664         case WM8994_FLL_SRC_LRCLK:
1665         case WM8994_FLL_SRC_BCLK:
1666                 break;
1667         default:
1668                 return -EINVAL;
1669         }
1670
1671         /* Are we changing anything? */
1672         if (wm8994->fll[id].src == src &&
1673             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1674                 return 0;
1675
1676         /* If we're stopping the FLL redo the old config - no
1677          * registers will actually be written but we avoid GCC flow
1678          * analysis bugs spewing warnings.
1679          */
1680         if (freq_out)
1681                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1682         else
1683                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1684                                             wm8994->fll[id].out);
1685         if (ret < 0)
1686                 return ret;
1687
1688         /* Gate the AIF clocks while we reclock */
1689         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1690                             WM8994_AIF1CLK_ENA, 0);
1691         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1692                             WM8994_AIF2CLK_ENA, 0);
1693
1694         /* We always need to disable the FLL while reconfiguring */
1695         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1696                             WM8994_FLL1_ENA, 0);
1697
1698         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1699                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1700         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1701                             WM8994_FLL1_OUTDIV_MASK |
1702                             WM8994_FLL1_FRATIO_MASK, reg);
1703
1704         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1705
1706         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1707                             WM8994_FLL1_N_MASK,
1708                                     fll.n << WM8994_FLL1_N_SHIFT);
1709
1710         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1711                             WM8994_FLL1_REFCLK_DIV_MASK |
1712                             WM8994_FLL1_REFCLK_SRC_MASK,
1713                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1714                             (src - 1));
1715
1716         /* Enable (with fractional mode if required) */
1717         if (freq_out) {
1718                 if (fll.k)
1719                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1720                 else
1721                         reg = WM8994_FLL1_ENA;
1722                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1723                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1724                                     reg);
1725
1726                 if (wm8994->fll_locked_irq) {
1727                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1728                                                               msecs_to_jiffies(10));
1729                         if (timeout == 0)
1730                                 dev_warn(codec->dev,
1731                                          "Timed out waiting for FLL lock\n");
1732                 } else {
1733                         msleep(5);
1734                 }
1735         }
1736
1737         wm8994->fll[id].in = freq_in;
1738         wm8994->fll[id].out = freq_out;
1739         wm8994->fll[id].src = src;
1740
1741         /* Enable any gated AIF clocks */
1742         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1743                             WM8994_AIF1CLK_ENA, aif1);
1744         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1745                             WM8994_AIF2CLK_ENA, aif2);
1746
1747         configure_clock(codec);
1748
1749         return 0;
1750 }
1751
1752 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1753 {
1754         struct completion *completion = data;
1755
1756         complete(completion);
1757
1758         return IRQ_HANDLED;
1759 }
1760
1761 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1762
1763 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1764                           unsigned int freq_in, unsigned int freq_out)
1765 {
1766         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1767 }
1768
1769 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1770                 int clk_id, unsigned int freq, int dir)
1771 {
1772         struct snd_soc_codec *codec = dai->codec;
1773         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1774         int i;
1775
1776         switch (dai->id) {
1777         case 1:
1778         case 2:
1779                 break;
1780
1781         default:
1782                 /* AIF3 shares clocking with AIF1/2 */
1783                 return -EINVAL;
1784         }
1785
1786         switch (clk_id) {
1787         case WM8994_SYSCLK_MCLK1:
1788                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1789                 wm8994->mclk[0] = freq;
1790                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1791                         dai->id, freq);
1792                 break;
1793
1794         case WM8994_SYSCLK_MCLK2:
1795                 /* TODO: Set GPIO AF */
1796                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1797                 wm8994->mclk[1] = freq;
1798                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1799                         dai->id, freq);
1800                 break;
1801
1802         case WM8994_SYSCLK_FLL1:
1803                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1804                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1805                 break;
1806
1807         case WM8994_SYSCLK_FLL2:
1808                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1809                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1810                 break;
1811
1812         case WM8994_SYSCLK_OPCLK:
1813                 /* Special case - a division (times 10) is given and
1814                  * no effect on main clocking.
1815                  */
1816                 if (freq) {
1817                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1818                                 if (opclk_divs[i] == freq)
1819                                         break;
1820                         if (i == ARRAY_SIZE(opclk_divs))
1821                                 return -EINVAL;
1822                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1823                                             WM8994_OPCLK_DIV_MASK, i);
1824                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1825                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1826                 } else {
1827                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1828                                             WM8994_OPCLK_ENA, 0);
1829                 }
1830
1831         default:
1832                 return -EINVAL;
1833         }
1834
1835         configure_clock(codec);
1836
1837         return 0;
1838 }
1839
1840 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1841                                  enum snd_soc_bias_level level)
1842 {
1843         struct wm8994 *control = codec->control_data;
1844         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1845
1846         switch (level) {
1847         case SND_SOC_BIAS_ON:
1848                 break;
1849
1850         case SND_SOC_BIAS_PREPARE:
1851                 /* VMID=2x40k */
1852                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1853                                     WM8994_VMID_SEL_MASK, 0x2);
1854                 break;
1855
1856         case SND_SOC_BIAS_STANDBY:
1857                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1858                         pm_runtime_get_sync(codec->dev);
1859
1860                         switch (control->type) {
1861                         case WM8994:
1862                                 if (wm8994->revision < 4) {
1863                                         /* Tweak DC servo and DSP
1864                                          * configuration for improved
1865                                          * performance. */
1866                                         snd_soc_write(codec, 0x102, 0x3);
1867                                         snd_soc_write(codec, 0x56, 0x3);
1868                                         snd_soc_write(codec, 0x817, 0);
1869                                         snd_soc_write(codec, 0x102, 0);
1870                                 }
1871                                 break;
1872
1873                         case WM8958:
1874                                 if (wm8994->revision == 0) {
1875                                         /* Optimise performance for rev A */
1876                                         snd_soc_write(codec, 0x102, 0x3);
1877                                         snd_soc_write(codec, 0xcb, 0x81);
1878                                         snd_soc_write(codec, 0x817, 0);
1879                                         snd_soc_write(codec, 0x102, 0);
1880
1881                                         snd_soc_update_bits(codec,
1882                                                             WM8958_CHARGE_PUMP_2,
1883                                                             WM8958_CP_DISCH,
1884                                                             WM8958_CP_DISCH);
1885                                 }
1886                                 break;
1887                         }
1888
1889                         /* Discharge LINEOUT1 & 2 */
1890                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1891                                             WM8994_LINEOUT1_DISCH |
1892                                             WM8994_LINEOUT2_DISCH,
1893                                             WM8994_LINEOUT1_DISCH |
1894                                             WM8994_LINEOUT2_DISCH);
1895
1896                         /* Startup bias, VMID ramp & buffer */
1897                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1898                                             WM8994_STARTUP_BIAS_ENA |
1899                                             WM8994_VMID_BUF_ENA |
1900                                             WM8994_VMID_RAMP_MASK,
1901                                             WM8994_STARTUP_BIAS_ENA |
1902                                             WM8994_VMID_BUF_ENA |
1903                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1904
1905                         /* Main bias enable, VMID=2x40k */
1906                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1907                                             WM8994_BIAS_ENA |
1908                                             WM8994_VMID_SEL_MASK,
1909                                             WM8994_BIAS_ENA | 0x2);
1910
1911                         msleep(20);
1912                 }
1913
1914                 /* VMID=2x500k */
1915                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1916                                     WM8994_VMID_SEL_MASK, 0x4);
1917
1918                 break;
1919
1920         case SND_SOC_BIAS_OFF:
1921                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1922                         /* Switch over to startup biases */
1923                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1924                                             WM8994_BIAS_SRC |
1925                                             WM8994_STARTUP_BIAS_ENA |
1926                                             WM8994_VMID_BUF_ENA |
1927                                             WM8994_VMID_RAMP_MASK,
1928                                             WM8994_BIAS_SRC |
1929                                             WM8994_STARTUP_BIAS_ENA |
1930                                             WM8994_VMID_BUF_ENA |
1931                                             (1 << WM8994_VMID_RAMP_SHIFT));
1932
1933                         /* Disable main biases */
1934                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1935                                             WM8994_BIAS_ENA |
1936                                             WM8994_VMID_SEL_MASK, 0);
1937
1938                         /* Discharge line */
1939                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1940                                             WM8994_LINEOUT1_DISCH |
1941                                             WM8994_LINEOUT2_DISCH,
1942                                             WM8994_LINEOUT1_DISCH |
1943                                             WM8994_LINEOUT2_DISCH);
1944
1945                         msleep(5);
1946
1947                         /* Switch off startup biases */
1948                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1949                                             WM8994_BIAS_SRC |
1950                                             WM8994_STARTUP_BIAS_ENA |
1951                                             WM8994_VMID_BUF_ENA |
1952                                             WM8994_VMID_RAMP_MASK, 0);
1953
1954                         wm8994->cur_fw = NULL;
1955
1956                         pm_runtime_put(codec->dev);
1957                 }
1958                 break;
1959         }
1960         codec->dapm.bias_level = level;
1961         return 0;
1962 }
1963
1964 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1965 {
1966         struct snd_soc_codec *codec = dai->codec;
1967         struct wm8994 *control = codec->control_data;
1968         int ms_reg;
1969         int aif1_reg;
1970         int ms = 0;
1971         int aif1 = 0;
1972
1973         switch (dai->id) {
1974         case 1:
1975                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1976                 aif1_reg = WM8994_AIF1_CONTROL_1;
1977                 break;
1978         case 2:
1979                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1980                 aif1_reg = WM8994_AIF2_CONTROL_1;
1981                 break;
1982         default:
1983                 return -EINVAL;
1984         }
1985
1986         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1987         case SND_SOC_DAIFMT_CBS_CFS:
1988                 break;
1989         case SND_SOC_DAIFMT_CBM_CFM:
1990                 ms = WM8994_AIF1_MSTR;
1991                 break;
1992         default:
1993                 return -EINVAL;
1994         }
1995
1996         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1997         case SND_SOC_DAIFMT_DSP_B:
1998                 aif1 |= WM8994_AIF1_LRCLK_INV;
1999         case SND_SOC_DAIFMT_DSP_A:
2000                 aif1 |= 0x18;
2001                 break;
2002         case SND_SOC_DAIFMT_I2S:
2003                 aif1 |= 0x10;
2004                 break;
2005         case SND_SOC_DAIFMT_RIGHT_J:
2006                 break;
2007         case SND_SOC_DAIFMT_LEFT_J:
2008                 aif1 |= 0x8;
2009                 break;
2010         default:
2011                 return -EINVAL;
2012         }
2013
2014         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2015         case SND_SOC_DAIFMT_DSP_A:
2016         case SND_SOC_DAIFMT_DSP_B:
2017                 /* frame inversion not valid for DSP modes */
2018                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2019                 case SND_SOC_DAIFMT_NB_NF:
2020                         break;
2021                 case SND_SOC_DAIFMT_IB_NF:
2022                         aif1 |= WM8994_AIF1_BCLK_INV;
2023                         break;
2024                 default:
2025                         return -EINVAL;
2026                 }
2027                 break;
2028
2029         case SND_SOC_DAIFMT_I2S:
2030         case SND_SOC_DAIFMT_RIGHT_J:
2031         case SND_SOC_DAIFMT_LEFT_J:
2032                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2033                 case SND_SOC_DAIFMT_NB_NF:
2034                         break;
2035                 case SND_SOC_DAIFMT_IB_IF:
2036                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2037                         break;
2038                 case SND_SOC_DAIFMT_IB_NF:
2039                         aif1 |= WM8994_AIF1_BCLK_INV;
2040                         break;
2041                 case SND_SOC_DAIFMT_NB_IF:
2042                         aif1 |= WM8994_AIF1_LRCLK_INV;
2043                         break;
2044                 default:
2045                         return -EINVAL;
2046                 }
2047                 break;
2048         default:
2049                 return -EINVAL;
2050         }
2051
2052         /* The AIF2 format configuration needs to be mirrored to AIF3
2053          * on WM8958 if it's in use so just do it all the time. */
2054         if (control->type == WM8958 && dai->id == 2)
2055                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2056                                     WM8994_AIF1_LRCLK_INV |
2057                                     WM8958_AIF3_FMT_MASK, aif1);
2058
2059         snd_soc_update_bits(codec, aif1_reg,
2060                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2061                             WM8994_AIF1_FMT_MASK,
2062                             aif1);
2063         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2064                             ms);
2065
2066         return 0;
2067 }
2068
2069 static struct {
2070         int val, rate;
2071 } srs[] = {
2072         { 0,   8000 },
2073         { 1,  11025 },
2074         { 2,  12000 },
2075         { 3,  16000 },
2076         { 4,  22050 },
2077         { 5,  24000 },
2078         { 6,  32000 },
2079         { 7,  44100 },
2080         { 8,  48000 },
2081         { 9,  88200 },
2082         { 10, 96000 },
2083 };
2084
2085 static int fs_ratios[] = {
2086         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2087 };
2088
2089 static int bclk_divs[] = {
2090         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2091         640, 880, 960, 1280, 1760, 1920
2092 };
2093
2094 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2095                             struct snd_pcm_hw_params *params,
2096                             struct snd_soc_dai *dai)
2097 {
2098         struct snd_soc_codec *codec = dai->codec;
2099         struct wm8994 *control = codec->control_data;
2100         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2101         int aif1_reg;
2102         int aif2_reg;
2103         int bclk_reg;
2104         int lrclk_reg;
2105         int rate_reg;
2106         int aif1 = 0;
2107         int aif2 = 0;
2108         int bclk = 0;
2109         int lrclk = 0;
2110         int rate_val = 0;
2111         int id = dai->id - 1;
2112
2113         int i, cur_val, best_val, bclk_rate, best;
2114
2115         switch (dai->id) {
2116         case 1:
2117                 aif1_reg = WM8994_AIF1_CONTROL_1;
2118                 aif2_reg = WM8994_AIF1_CONTROL_2;
2119                 bclk_reg = WM8994_AIF1_BCLK;
2120                 rate_reg = WM8994_AIF1_RATE;
2121                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2122                     wm8994->lrclk_shared[0]) {
2123                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2124                 } else {
2125                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2126                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2127                 }
2128                 break;
2129         case 2:
2130                 aif1_reg = WM8994_AIF2_CONTROL_1;
2131                 aif2_reg = WM8994_AIF2_CONTROL_2;
2132                 bclk_reg = WM8994_AIF2_BCLK;
2133                 rate_reg = WM8994_AIF2_RATE;
2134                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2135                     wm8994->lrclk_shared[1]) {
2136                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2137                 } else {
2138                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2139                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2140                 }
2141                 break;
2142         case 3:
2143                 switch (control->type) {
2144                 case WM8958:
2145                         aif1_reg = WM8958_AIF3_CONTROL_1;
2146                         break;
2147                 default:
2148                         return 0;
2149                 }
2150         default:
2151                 return -EINVAL;
2152         }
2153
2154         bclk_rate = params_rate(params) * 2;
2155         switch (params_format(params)) {
2156         case SNDRV_PCM_FORMAT_S16_LE:
2157                 bclk_rate *= 16;
2158                 break;
2159         case SNDRV_PCM_FORMAT_S20_3LE:
2160                 bclk_rate *= 20;
2161                 aif1 |= 0x20;
2162                 break;
2163         case SNDRV_PCM_FORMAT_S24_LE:
2164                 bclk_rate *= 24;
2165                 aif1 |= 0x40;
2166                 break;
2167         case SNDRV_PCM_FORMAT_S32_LE:
2168                 bclk_rate *= 32;
2169                 aif1 |= 0x60;
2170                 break;
2171         default:
2172                 return -EINVAL;
2173         }
2174
2175         /* Try to find an appropriate sample rate; look for an exact match. */
2176         for (i = 0; i < ARRAY_SIZE(srs); i++)
2177                 if (srs[i].rate == params_rate(params))
2178                         break;
2179         if (i == ARRAY_SIZE(srs))
2180                 return -EINVAL;
2181         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2182
2183         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2184         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2185                 dai->id, wm8994->aifclk[id], bclk_rate);
2186
2187         if (params_channels(params) == 1 &&
2188             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2189                 aif2 |= WM8994_AIF1_MONO;
2190
2191         if (wm8994->aifclk[id] == 0) {
2192                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2193                 return -EINVAL;
2194         }
2195
2196         /* AIFCLK/fs ratio; look for a close match in either direction */
2197         best = 0;
2198         best_val = abs((fs_ratios[0] * params_rate(params))
2199                        - wm8994->aifclk[id]);
2200         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2201                 cur_val = abs((fs_ratios[i] * params_rate(params))
2202                               - wm8994->aifclk[id]);
2203                 if (cur_val >= best_val)
2204                         continue;
2205                 best = i;
2206                 best_val = cur_val;
2207         }
2208         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2209                 dai->id, fs_ratios[best]);
2210         rate_val |= best;
2211
2212         /* We may not get quite the right frequency if using
2213          * approximate clocks so look for the closest match that is
2214          * higher than the target (we need to ensure that there enough
2215          * BCLKs to clock out the samples).
2216          */
2217         best = 0;
2218         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2219                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2220                 if (cur_val < 0) /* BCLK table is sorted */
2221                         break;
2222                 best = i;
2223         }
2224         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2225         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2226                 bclk_divs[best], bclk_rate);
2227         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2228
2229         lrclk = bclk_rate / params_rate(params);
2230         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2231                 lrclk, bclk_rate / lrclk);
2232
2233         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2234         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2235         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2236         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2237                             lrclk);
2238         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2239                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2240
2241         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2242                 switch (dai->id) {
2243                 case 1:
2244                         wm8994->dac_rates[0] = params_rate(params);
2245                         wm8994_set_retune_mobile(codec, 0);
2246                         wm8994_set_retune_mobile(codec, 1);
2247                         break;
2248                 case 2:
2249                         wm8994->dac_rates[1] = params_rate(params);
2250                         wm8994_set_retune_mobile(codec, 2);
2251                         break;
2252                 }
2253         }
2254
2255         return 0;
2256 }
2257
2258 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2259                                  struct snd_pcm_hw_params *params,
2260                                  struct snd_soc_dai *dai)
2261 {
2262         struct snd_soc_codec *codec = dai->codec;
2263         struct wm8994 *control = codec->control_data;
2264         int aif1_reg;
2265         int aif1 = 0;
2266
2267         switch (dai->id) {
2268         case 3:
2269                 switch (control->type) {
2270                 case WM8958:
2271                         aif1_reg = WM8958_AIF3_CONTROL_1;
2272                         break;
2273                 default:
2274                         return 0;
2275                 }
2276         default:
2277                 return 0;
2278         }
2279
2280         switch (params_format(params)) {
2281         case SNDRV_PCM_FORMAT_S16_LE:
2282                 break;
2283         case SNDRV_PCM_FORMAT_S20_3LE:
2284                 aif1 |= 0x20;
2285                 break;
2286         case SNDRV_PCM_FORMAT_S24_LE:
2287                 aif1 |= 0x40;
2288                 break;
2289         case SNDRV_PCM_FORMAT_S32_LE:
2290                 aif1 |= 0x60;
2291                 break;
2292         default:
2293                 return -EINVAL;
2294         }
2295
2296         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2297 }
2298
2299 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2300 {
2301         struct snd_soc_codec *codec = codec_dai->codec;
2302         int mute_reg;
2303         int reg;
2304
2305         switch (codec_dai->id) {
2306         case 1:
2307                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2308                 break;
2309         case 2:
2310                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2311                 break;
2312         default:
2313                 return -EINVAL;
2314         }
2315
2316         if (mute)
2317                 reg = WM8994_AIF1DAC1_MUTE;
2318         else
2319                 reg = 0;
2320
2321         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2322
2323         return 0;
2324 }
2325
2326 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2327 {
2328         struct snd_soc_codec *codec = codec_dai->codec;
2329         int reg, val, mask;
2330
2331         switch (codec_dai->id) {
2332         case 1:
2333                 reg = WM8994_AIF1_MASTER_SLAVE;
2334                 mask = WM8994_AIF1_TRI;
2335                 break;
2336         case 2:
2337                 reg = WM8994_AIF2_MASTER_SLAVE;
2338                 mask = WM8994_AIF2_TRI;
2339                 break;
2340         case 3:
2341                 reg = WM8994_POWER_MANAGEMENT_6;
2342                 mask = WM8994_AIF3_TRI;
2343                 break;
2344         default:
2345                 return -EINVAL;
2346         }
2347
2348         if (tristate)
2349                 val = mask;
2350         else
2351                 val = 0;
2352
2353         return snd_soc_update_bits(codec, reg, mask, val);
2354 }
2355
2356 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2357
2358 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2359                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2360
2361 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2362         .set_sysclk     = wm8994_set_dai_sysclk,
2363         .set_fmt        = wm8994_set_dai_fmt,
2364         .hw_params      = wm8994_hw_params,
2365         .digital_mute   = wm8994_aif_mute,
2366         .set_pll        = wm8994_set_fll,
2367         .set_tristate   = wm8994_set_tristate,
2368 };
2369
2370 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2371         .set_sysclk     = wm8994_set_dai_sysclk,
2372         .set_fmt        = wm8994_set_dai_fmt,
2373         .hw_params      = wm8994_hw_params,
2374         .digital_mute   = wm8994_aif_mute,
2375         .set_pll        = wm8994_set_fll,
2376         .set_tristate   = wm8994_set_tristate,
2377 };
2378
2379 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2380         .hw_params      = wm8994_aif3_hw_params,
2381         .set_tristate   = wm8994_set_tristate,
2382 };
2383
2384 static struct snd_soc_dai_driver wm8994_dai[] = {
2385         {
2386                 .name = "wm8994-aif1",
2387                 .id = 1,
2388                 .playback = {
2389                         .stream_name = "AIF1 Playback",
2390                         .channels_min = 1,
2391                         .channels_max = 2,
2392                         .rates = WM8994_RATES,
2393                         .formats = WM8994_FORMATS,
2394                 },
2395                 .capture = {
2396                         .stream_name = "AIF1 Capture",
2397                         .channels_min = 1,
2398                         .channels_max = 2,
2399                         .rates = WM8994_RATES,
2400                         .formats = WM8994_FORMATS,
2401                  },
2402                 .ops = &wm8994_aif1_dai_ops,
2403         },
2404         {
2405                 .name = "wm8994-aif2",
2406                 .id = 2,
2407                 .playback = {
2408                         .stream_name = "AIF2 Playback",
2409                         .channels_min = 1,
2410                         .channels_max = 2,
2411                         .rates = WM8994_RATES,
2412                         .formats = WM8994_FORMATS,
2413                 },
2414                 .capture = {
2415                         .stream_name = "AIF2 Capture",
2416                         .channels_min = 1,
2417                         .channels_max = 2,
2418                         .rates = WM8994_RATES,
2419                         .formats = WM8994_FORMATS,
2420                 },
2421                 .ops = &wm8994_aif2_dai_ops,
2422         },
2423         {
2424                 .name = "wm8994-aif3",
2425                 .id = 3,
2426                 .playback = {
2427                         .stream_name = "AIF3 Playback",
2428                         .channels_min = 1,
2429                         .channels_max = 2,
2430                         .rates = WM8994_RATES,
2431                         .formats = WM8994_FORMATS,
2432                 },
2433                 .capture = {
2434                         .stream_name = "AIF3 Capture",
2435                         .channels_min = 1,
2436                         .channels_max = 2,
2437                         .rates = WM8994_RATES,
2438                         .formats = WM8994_FORMATS,
2439                 },
2440                 .ops = &wm8994_aif3_dai_ops,
2441         }
2442 };
2443
2444 #ifdef CONFIG_PM
2445 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2446 {
2447         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2448         struct wm8994 *control = codec->control_data;
2449         int i, ret;
2450
2451         switch (control->type) {
2452         case WM8994:
2453                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2454                 break;
2455         case WM8958:
2456                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2457                                     WM8958_MICD_ENA, 0);
2458                 break;
2459         }
2460
2461         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2462                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2463                        sizeof(struct wm8994_fll_config));
2464                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2465                 if (ret < 0)
2466                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2467                                  i + 1, ret);
2468         }
2469
2470         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2471
2472         return 0;
2473 }
2474
2475 static int wm8994_resume(struct snd_soc_codec *codec)
2476 {
2477         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2478         struct wm8994 *control = codec->control_data;
2479         int i, ret;
2480         unsigned int val, mask;
2481
2482         if (wm8994->revision < 4) {
2483                 /* force a HW read */
2484                 val = wm8994_reg_read(codec->control_data,
2485                                       WM8994_POWER_MANAGEMENT_5);
2486
2487                 /* modify the cache only */
2488                 codec->cache_only = 1;
2489                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2490                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2491                 val &= mask;
2492                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2493                                     mask, val);
2494                 codec->cache_only = 0;
2495         }
2496
2497         /* Restore the registers */
2498         ret = snd_soc_cache_sync(codec);
2499         if (ret != 0)
2500                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2501
2502         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2503
2504         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2505                 if (!wm8994->fll_suspend[i].out)
2506                         continue;
2507
2508                 ret = _wm8994_set_fll(codec, i + 1,
2509                                      wm8994->fll_suspend[i].src,
2510                                      wm8994->fll_suspend[i].in,
2511                                      wm8994->fll_suspend[i].out);
2512                 if (ret < 0)
2513                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2514                                  i + 1, ret);
2515         }
2516
2517         switch (control->type) {
2518         case WM8994:
2519                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2520                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2521                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2522                 break;
2523         case WM8958:
2524                 if (wm8994->jack_cb)
2525                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2526                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2527                 break;
2528         }
2529
2530         return 0;
2531 }
2532 #else
2533 #define wm8994_suspend NULL
2534 #define wm8994_resume NULL
2535 #endif
2536
2537 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2538 {
2539         struct snd_soc_codec *codec = wm8994->codec;
2540         struct wm8994_pdata *pdata = wm8994->pdata;
2541         struct snd_kcontrol_new controls[] = {
2542                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2543                              wm8994->retune_mobile_enum,
2544                              wm8994_get_retune_mobile_enum,
2545                              wm8994_put_retune_mobile_enum),
2546                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2547                              wm8994->retune_mobile_enum,
2548                              wm8994_get_retune_mobile_enum,
2549                              wm8994_put_retune_mobile_enum),
2550                 SOC_ENUM_EXT("AIF2 EQ Mode",
2551                              wm8994->retune_mobile_enum,
2552                              wm8994_get_retune_mobile_enum,
2553                              wm8994_put_retune_mobile_enum),
2554         };
2555         int ret, i, j;
2556         const char **t;
2557
2558         /* We need an array of texts for the enum API but the number
2559          * of texts is likely to be less than the number of
2560          * configurations due to the sample rate dependency of the
2561          * configurations. */
2562         wm8994->num_retune_mobile_texts = 0;
2563         wm8994->retune_mobile_texts = NULL;
2564         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2565                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2566                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2567                                    wm8994->retune_mobile_texts[j]) == 0)
2568                                 break;
2569                 }
2570
2571                 if (j != wm8994->num_retune_mobile_texts)
2572                         continue;
2573
2574                 /* Expand the array... */
2575                 t = krealloc(wm8994->retune_mobile_texts,
2576                              sizeof(char *) *
2577                              (wm8994->num_retune_mobile_texts + 1),
2578                              GFP_KERNEL);
2579                 if (t == NULL)
2580                         continue;
2581
2582                 /* ...store the new entry... */
2583                 t[wm8994->num_retune_mobile_texts] =
2584                         pdata->retune_mobile_cfgs[i].name;
2585
2586                 /* ...and remember the new version. */
2587                 wm8994->num_retune_mobile_texts++;
2588                 wm8994->retune_mobile_texts = t;
2589         }
2590
2591         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2592                 wm8994->num_retune_mobile_texts);
2593
2594         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2595         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2596
2597         ret = snd_soc_add_controls(wm8994->codec, controls,
2598                                    ARRAY_SIZE(controls));
2599         if (ret != 0)
2600                 dev_err(wm8994->codec->dev,
2601                         "Failed to add ReTune Mobile controls: %d\n", ret);
2602 }
2603
2604 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2605 {
2606         struct snd_soc_codec *codec = wm8994->codec;
2607         struct wm8994_pdata *pdata = wm8994->pdata;
2608         int ret, i;
2609
2610         if (!pdata)
2611                 return;
2612
2613         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2614                                       pdata->lineout2_diff,
2615                                       pdata->lineout1fb,
2616                                       pdata->lineout2fb,
2617                                       pdata->jd_scthr,
2618                                       pdata->jd_thr,
2619                                       pdata->micbias1_lvl,
2620                                       pdata->micbias2_lvl);
2621
2622         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2623
2624         if (pdata->num_drc_cfgs) {
2625                 struct snd_kcontrol_new controls[] = {
2626                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2627                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2628                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2629                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2630                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2631                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2632                 };
2633
2634                 /* We need an array of texts for the enum API */
2635                 wm8994->drc_texts = kmalloc(sizeof(char *)
2636                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2637                 if (!wm8994->drc_texts) {
2638                         dev_err(wm8994->codec->dev,
2639                                 "Failed to allocate %d DRC config texts\n",
2640                                 pdata->num_drc_cfgs);
2641                         return;
2642                 }
2643
2644                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2645                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2646
2647                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2648                 wm8994->drc_enum.texts = wm8994->drc_texts;
2649
2650                 ret = snd_soc_add_controls(wm8994->codec, controls,
2651                                            ARRAY_SIZE(controls));
2652                 if (ret != 0)
2653                         dev_err(wm8994->codec->dev,
2654                                 "Failed to add DRC mode controls: %d\n", ret);
2655
2656                 for (i = 0; i < WM8994_NUM_DRC; i++)
2657                         wm8994_set_drc(codec, i);
2658         }
2659
2660         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2661                 pdata->num_retune_mobile_cfgs);
2662
2663         if (pdata->num_retune_mobile_cfgs)
2664                 wm8994_handle_retune_mobile_pdata(wm8994);
2665         else
2666                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2667                                      ARRAY_SIZE(wm8994_eq_controls));
2668
2669         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2670                 if (pdata->micbias[i]) {
2671                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2672                                 pdata->micbias[i] & 0xffff);
2673                 }
2674         }
2675 }
2676
2677 /**
2678  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2679  *
2680  * @codec:   WM8994 codec
2681  * @jack:    jack to report detection events on
2682  * @micbias: microphone bias to detect on
2683  * @det:     value to report for presence detection
2684  * @shrt:    value to report for short detection
2685  *
2686  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2687  * being used to bring out signals to the processor then only platform
2688  * data configuration is needed for WM8994 and processor GPIOs should
2689  * be configured using snd_soc_jack_add_gpios() instead.
2690  *
2691  * Configuration of detection levels is available via the micbias1_lvl
2692  * and micbias2_lvl platform data members.
2693  */
2694 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2695                       int micbias, int det, int shrt)
2696 {
2697         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2698         struct wm8994_micdet *micdet;
2699         struct wm8994 *control = codec->control_data;
2700         int reg;
2701
2702         if (control->type != WM8994)
2703                 return -EINVAL;
2704
2705         switch (micbias) {
2706         case 1:
2707                 micdet = &wm8994->micdet[0];
2708                 break;
2709         case 2:
2710                 micdet = &wm8994->micdet[1];
2711                 break;
2712         default:
2713                 return -EINVAL;
2714         }
2715
2716         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2717                 micbias, det, shrt);
2718
2719         /* Store the configuration */
2720         micdet->jack = jack;
2721         micdet->det = det;
2722         micdet->shrt = shrt;
2723
2724         /* If either of the jacks is set up then enable detection */
2725         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2726                 reg = WM8994_MICD_ENA;
2727         else
2728                 reg = 0;
2729
2730         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2731
2732         return 0;
2733 }
2734 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2735
2736 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2737 {
2738         struct wm8994_priv *priv = data;
2739         struct snd_soc_codec *codec = priv->codec;
2740         int reg;
2741         int report;
2742
2743 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2744         trace_snd_soc_jack_irq(dev_name(codec->dev));
2745 #endif
2746
2747         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2748         if (reg < 0) {
2749                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2750                         reg);
2751                 return IRQ_HANDLED;
2752         }
2753
2754         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2755
2756         report = 0;
2757         if (reg & WM8994_MIC1_DET_STS)
2758                 report |= priv->micdet[0].det;
2759         if (reg & WM8994_MIC1_SHRT_STS)
2760                 report |= priv->micdet[0].shrt;
2761         snd_soc_jack_report(priv->micdet[0].jack, report,
2762                             priv->micdet[0].det | priv->micdet[0].shrt);
2763
2764         report = 0;
2765         if (reg & WM8994_MIC2_DET_STS)
2766                 report |= priv->micdet[1].det;
2767         if (reg & WM8994_MIC2_SHRT_STS)
2768                 report |= priv->micdet[1].shrt;
2769         snd_soc_jack_report(priv->micdet[1].jack, report,
2770                             priv->micdet[1].det | priv->micdet[1].shrt);
2771
2772         return IRQ_HANDLED;
2773 }
2774
2775 /* Default microphone detection handler for WM8958 - the user can
2776  * override this if they wish.
2777  */
2778 static void wm8958_default_micdet(u16 status, void *data)
2779 {
2780         struct snd_soc_codec *codec = data;
2781         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2782         int report = 0;
2783
2784         /* If nothing present then clear our statuses */
2785         if (!(status & WM8958_MICD_STS))
2786                 goto done;
2787
2788         report = SND_JACK_MICROPHONE;
2789
2790         /* Everything else is buttons; just assign slots */
2791         if (status & 0x1c0)
2792                 report |= SND_JACK_BTN_0;
2793
2794 done:
2795         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2796                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2797 }
2798
2799 /**
2800  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2801  *
2802  * @codec:   WM8958 codec
2803  * @jack:    jack to report detection events on
2804  *
2805  * Enable microphone detection functionality for the WM8958.  By
2806  * default simple detection which supports the detection of up to 6
2807  * buttons plus video and microphone functionality is supported.
2808  *
2809  * The WM8958 has an advanced jack detection facility which is able to
2810  * support complex accessory detection, especially when used in
2811  * conjunction with external circuitry.  In order to provide maximum
2812  * flexiblity a callback is provided which allows a completely custom
2813  * detection algorithm.
2814  */
2815 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2816                       wm8958_micdet_cb cb, void *cb_data)
2817 {
2818         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2819         struct wm8994 *control = codec->control_data;
2820
2821         if (control->type != WM8958)
2822                 return -EINVAL;
2823
2824         if (jack) {
2825                 if (!cb) {
2826                         dev_dbg(codec->dev, "Using default micdet callback\n");
2827                         cb = wm8958_default_micdet;
2828                         cb_data = codec;
2829                 }
2830
2831                 wm8994->micdet[0].jack = jack;
2832                 wm8994->jack_cb = cb;
2833                 wm8994->jack_cb_data = cb_data;
2834
2835                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2836                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2837         } else {
2838                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2839                                     WM8958_MICD_ENA, 0);
2840         }
2841
2842         return 0;
2843 }
2844 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2845
2846 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2847 {
2848         struct wm8994_priv *wm8994 = data;
2849         struct snd_soc_codec *codec = wm8994->codec;
2850         int reg;
2851
2852         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2853         if (reg < 0) {
2854                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2855                         reg);
2856                 return IRQ_NONE;
2857         }
2858
2859         if (!(reg & WM8958_MICD_VALID)) {
2860                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2861                 goto out;
2862         }
2863
2864 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2865         trace_snd_soc_jack_irq(dev_name(codec->dev));
2866 #endif
2867
2868         if (wm8994->jack_cb)
2869                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2870         else
2871                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2872
2873 out:
2874         return IRQ_HANDLED;
2875 }
2876
2877 static irqreturn_t wm8994_fifo_error(int irq, void *data)
2878 {
2879         struct snd_soc_codec *codec = data;
2880
2881         dev_err(codec->dev, "FIFO error\n");
2882
2883         return IRQ_HANDLED;
2884 }
2885
2886 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2887 {
2888         struct wm8994 *control;
2889         struct wm8994_priv *wm8994;
2890         struct snd_soc_dapm_context *dapm = &codec->dapm;
2891         int ret, i;
2892
2893         codec->control_data = dev_get_drvdata(codec->dev->parent);
2894         control = codec->control_data;
2895
2896         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2897         if (wm8994 == NULL)
2898                 return -ENOMEM;
2899         snd_soc_codec_set_drvdata(codec, wm8994);
2900
2901         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2902         wm8994->codec = codec;
2903
2904         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2905                 init_completion(&wm8994->fll_locked[i]);
2906
2907         if (wm8994->pdata && wm8994->pdata->micdet_irq)
2908                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2909         else if (wm8994->pdata && wm8994->pdata->irq_base)
2910                 wm8994->micdet_irq = wm8994->pdata->irq_base +
2911                                      WM8994_IRQ_MIC1_DET;
2912
2913         pm_runtime_enable(codec->dev);
2914         pm_runtime_resume(codec->dev);
2915
2916         /* Read our current status back from the chip - we don't want to
2917          * reset as this may interfere with the GPIO or LDO operation. */
2918         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2919                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2920                         continue;
2921
2922                 ret = wm8994_reg_read(codec->control_data, i);
2923                 if (ret <= 0)
2924                         continue;
2925
2926                 ret = snd_soc_cache_write(codec, i, ret);
2927                 if (ret != 0) {
2928                         dev_err(codec->dev,
2929                                 "Failed to initialise cache for 0x%x: %d\n",
2930                                 i, ret);
2931                         goto err;
2932                 }
2933         }
2934
2935         /* Set revision-specific configuration */
2936         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2937         switch (control->type) {
2938         case WM8994:
2939                 switch (wm8994->revision) {
2940                 case 2:
2941                 case 3:
2942                         wm8994->hubs.dcs_codes = -5;
2943                         wm8994->hubs.hp_startup_mode = 1;
2944                         wm8994->hubs.dcs_readback_mode = 1;
2945                         wm8994->hubs.series_startup = 1;
2946                         break;
2947                 default:
2948                         wm8994->hubs.dcs_readback_mode = 1;
2949                         break;
2950                 }
2951
2952         case WM8958:
2953                 wm8994->hubs.dcs_readback_mode = 1;
2954                 break;
2955
2956         default:
2957                 break;
2958         }
2959
2960         wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
2961                            wm8994_fifo_error, "FIFO error", codec);
2962
2963         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2964                                  wm_hubs_dcs_done, "DC servo done",
2965                                  &wm8994->hubs);
2966         if (ret == 0)
2967                 wm8994->hubs.dcs_done_irq = true;
2968
2969         switch (control->type) {
2970         case WM8994:
2971                 if (wm8994->micdet_irq) {
2972                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2973                                                    wm8994_mic_irq,
2974                                                    IRQF_TRIGGER_RISING,
2975                                                    "Mic1 detect",
2976                                                    wm8994);
2977                         if (ret != 0)
2978                                 dev_warn(codec->dev,
2979                                          "Failed to request Mic1 detect IRQ: %d\n",
2980                                          ret);
2981                 }
2982
2983                 ret = wm8994_request_irq(codec->control_data,
2984                                          WM8994_IRQ_MIC1_SHRT,
2985                                          wm8994_mic_irq, "Mic 1 short",
2986                                          wm8994);
2987                 if (ret != 0)
2988                         dev_warn(codec->dev,
2989                                  "Failed to request Mic1 short IRQ: %d\n",
2990                                  ret);
2991
2992                 ret = wm8994_request_irq(codec->control_data,
2993                                          WM8994_IRQ_MIC2_DET,
2994                                          wm8994_mic_irq, "Mic 2 detect",
2995                                          wm8994);
2996                 if (ret != 0)
2997                         dev_warn(codec->dev,
2998                                  "Failed to request Mic2 detect IRQ: %d\n",
2999                                  ret);
3000
3001                 ret = wm8994_request_irq(codec->control_data,
3002                                          WM8994_IRQ_MIC2_SHRT,
3003                                          wm8994_mic_irq, "Mic 2 short",
3004                                          wm8994);
3005                 if (ret != 0)
3006                         dev_warn(codec->dev,
3007                                  "Failed to request Mic2 short IRQ: %d\n",
3008                                  ret);
3009                 break;
3010
3011         case WM8958:
3012                 if (wm8994->micdet_irq) {
3013                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3014                                                    wm8958_mic_irq,
3015                                                    IRQF_TRIGGER_RISING,
3016                                                    "Mic detect",
3017                                                    wm8994);
3018                         if (ret != 0)
3019                                 dev_warn(codec->dev,
3020                                          "Failed to request Mic detect IRQ: %d\n",
3021                                          ret);
3022                 }
3023         }
3024
3025         wm8994->fll_locked_irq = true;
3026         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3027                 ret = wm8994_request_irq(codec->control_data,
3028                                          WM8994_IRQ_FLL1_LOCK + i,
3029                                          wm8994_fll_locked_irq, "FLL lock",
3030                                          &wm8994->fll_locked[i]);
3031                 if (ret != 0)
3032                         wm8994->fll_locked_irq = false;
3033         }
3034
3035         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3036          * configured on init - if a system wants to do this dynamically
3037          * at runtime we can deal with that then.
3038          */
3039         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3040         if (ret < 0) {
3041                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3042                 goto err_irq;
3043         }
3044         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3045                 wm8994->lrclk_shared[0] = 1;
3046                 wm8994_dai[0].symmetric_rates = 1;
3047         } else {
3048                 wm8994->lrclk_shared[0] = 0;
3049         }
3050
3051         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3052         if (ret < 0) {
3053                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3054                 goto err_irq;
3055         }
3056         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3057                 wm8994->lrclk_shared[1] = 1;
3058                 wm8994_dai[1].symmetric_rates = 1;
3059         } else {
3060                 wm8994->lrclk_shared[1] = 0;
3061         }
3062
3063         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3064
3065         /* Latch volume updates (right only; we always do left then right). */
3066         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3067                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3068         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3069                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3070         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3071                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3072         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3073                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3074         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3075                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3076         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3077                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3078         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3079                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3080         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3081                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3082         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3083                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3084         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3085                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3086         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3087                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3088         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3089                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3090         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3091                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3092         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3093                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3094         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3095                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3096         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3097                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3098
3099         /* Set the low bit of the 3D stereo depth so TLV matches */
3100         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3101                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3102                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3103         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3104                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3105                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3106         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3107                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3108                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3109
3110         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3111          * use this; it only affects behaviour on idle TDM clock
3112          * cycles. */
3113         switch (control->type) {
3114         case WM8994:
3115         case WM8958:
3116                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3117                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3118                 break;
3119         default:
3120                 break;
3121         }
3122
3123         wm8994_update_class_w(codec);
3124
3125         wm8994_handle_pdata(wm8994);
3126
3127         wm_hubs_add_analogue_controls(codec);
3128         snd_soc_add_controls(codec, wm8994_snd_controls,
3129                              ARRAY_SIZE(wm8994_snd_controls));
3130         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3131                                   ARRAY_SIZE(wm8994_dapm_widgets));
3132
3133         switch (control->type) {
3134         case WM8994:
3135                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3136                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3137                 if (wm8994->revision < 4) {
3138                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3139                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3140                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3141                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3142                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3143                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3144                 } else {
3145                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3146                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3147                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3148                                                   ARRAY_SIZE(wm8994_adc_widgets));
3149                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3150                                                   ARRAY_SIZE(wm8994_dac_widgets));
3151                 }
3152                 break;
3153         case WM8958:
3154                 snd_soc_add_controls(codec, wm8958_snd_controls,
3155                                      ARRAY_SIZE(wm8958_snd_controls));
3156                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3157                                           ARRAY_SIZE(wm8958_dapm_widgets));
3158                 if (wm8994->revision < 1) {
3159                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3160                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3161                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3162                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3163                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3164                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3165                 } else {
3166                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3167                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3168                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3169                                                   ARRAY_SIZE(wm8994_adc_widgets));
3170                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3171                                                   ARRAY_SIZE(wm8994_dac_widgets));
3172                 }
3173                 break;
3174         }
3175
3176
3177         wm_hubs_add_analogue_routes(codec, 0, 0);
3178         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3179
3180         switch (control->type) {
3181         case WM8994:
3182                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3183                                         ARRAY_SIZE(wm8994_intercon));
3184
3185                 if (wm8994->revision < 4) {
3186                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3187                                                 ARRAY_SIZE(wm8994_revd_intercon));
3188                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3189                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3190                 } else {
3191                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3192                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3193                 }
3194                 break;
3195         case WM8958:
3196                 if (wm8994->revision < 1) {
3197                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3198                                                 ARRAY_SIZE(wm8994_revd_intercon));
3199                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3200                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3201                 } else {
3202                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3203                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3204                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3205                                                 ARRAY_SIZE(wm8958_intercon));
3206                 }
3207
3208                 wm8958_dsp2_init(codec);
3209                 break;
3210         }
3211
3212         return 0;
3213
3214 err_irq:
3215         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3216         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3217         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3218         if (wm8994->micdet_irq)
3219                 free_irq(wm8994->micdet_irq, wm8994);
3220         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3221                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3222                                 &wm8994->fll_locked[i]);
3223         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3224                         &wm8994->hubs);
3225         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3226 err:
3227         kfree(wm8994);
3228         return ret;
3229 }
3230
3231 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3232 {
3233         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3234         struct wm8994 *control = codec->control_data;
3235         int i;
3236
3237         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3238
3239         pm_runtime_disable(codec->dev);
3240
3241         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3242                 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3243                                 &wm8994->fll_locked[i]);
3244
3245         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3246                         &wm8994->hubs);
3247         wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3248
3249         switch (control->type) {
3250         case WM8994:
3251                 if (wm8994->micdet_irq)
3252                         free_irq(wm8994->micdet_irq, wm8994);
3253                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3254                                 wm8994);
3255                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3256                                 wm8994);
3257                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3258                                 wm8994);
3259                 break;
3260
3261         case WM8958:
3262                 if (wm8994->micdet_irq)
3263                         free_irq(wm8994->micdet_irq, wm8994);
3264                 break;
3265         }
3266         if (wm8994->mbc)
3267                 release_firmware(wm8994->mbc);
3268         if (wm8994->mbc_vss)
3269                 release_firmware(wm8994->mbc_vss);
3270         if (wm8994->enh_eq)
3271                 release_firmware(wm8994->enh_eq);
3272         kfree(wm8994->retune_mobile_texts);
3273         kfree(wm8994->drc_texts);
3274         kfree(wm8994);
3275
3276         return 0;
3277 }
3278
3279 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3280         .probe =        wm8994_codec_probe,
3281         .remove =       wm8994_codec_remove,
3282         .suspend =      wm8994_suspend,
3283         .resume =       wm8994_resume,
3284         .read =         wm8994_read,
3285         .write =        wm8994_write,
3286         .readable_register = wm8994_readable,
3287         .volatile_register = wm8994_volatile,
3288         .set_bias_level = wm8994_set_bias_level,
3289
3290         .reg_cache_size = WM8994_CACHE_SIZE,
3291         .reg_cache_default = wm8994_reg_defaults,
3292         .reg_word_size = 2,
3293         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3294 };
3295
3296 static int __devinit wm8994_probe(struct platform_device *pdev)
3297 {
3298         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3299                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3300 }
3301
3302 static int __devexit wm8994_remove(struct platform_device *pdev)
3303 {
3304         snd_soc_unregister_codec(&pdev->dev);
3305         return 0;
3306 }
3307
3308 static struct platform_driver wm8994_codec_driver = {
3309         .driver = {
3310                    .name = "wm8994-codec",
3311                    .owner = THIS_MODULE,
3312                    },
3313         .probe = wm8994_probe,
3314         .remove = __devexit_p(wm8994_remove),
3315 };
3316
3317 static __init int wm8994_init(void)
3318 {
3319         return platform_driver_register(&wm8994_codec_driver);
3320 }
3321 module_init(wm8994_init);
3322
3323 static __exit void wm8994_exit(void)
3324 {
3325         platform_driver_unregister(&wm8994_codec_driver);
3326 }
3327 module_exit(wm8994_exit);
3328
3329
3330 MODULE_DESCRIPTION("ASoC WM8994 driver");
3331 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3332 MODULE_LICENSE("GPL");
3333 MODULE_ALIAS("platform:wm8994-codec");