sound/soc/codecs/wm8962.c

   1 /*
   2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/i2c.h>
  21 #include <linux/input.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25 #include <linux/workqueue.h>
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31 #include <sound/initval.h>
  32 #include <sound/tlv.h>
  33 #include <sound/wm8962.h>
  34
  35 #include "wm8962.h"
  36
  37 #define WM8962_NUM_SUPPLIES 8
  38 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  39         "DCVDD",
  40         "DBVDD",
  41         "AVDD",
  42         "CPVDD",
  43         "MICVDD",
  44         "PLLVDD",
  45         "SPKVDD1",
  46         "SPKVDD2",
  47 };
  48
  49 /* codec private data */
  50 struct wm8962_priv {
  51         struct snd_soc_codec *codec;
  52
  53         u16 reg_cache[WM8962_MAX_REGISTER + 1];
  54
  55         int sysclk;
  56         int sysclk_rate;
  57
  58         int bclk;  /* Desired BCLK */
  59         int lrclk;
  60
  61         int fll_src;
  62         int fll_fref;
  63         int fll_fout;
  64
  65         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  66         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  67
  68 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  69         struct input_dev *beep;
  70         struct work_struct beep_work;
  71         int beep_rate;
  72 #endif
  73 };
  74
  75 /* We can't use the same notifier block for more than one supply and
  76  * there's no way I can see to get from a callback to the caller
  77  * except container_of().
  78  */
  79 #define WM8962_REGULATOR_EVENT(n) \
  80 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  81                                     unsigned long event, void *data)    \
  82 { \
  83         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  84                                                   disable_nb[n]); \
  85         if (event & REGULATOR_EVENT_DISABLE) { \
  86                 wm8962->codec->cache_sync = 1; \
  87         } \
  88         return 0; \
  89 }
  90
  91 WM8962_REGULATOR_EVENT(0)
  92 WM8962_REGULATOR_EVENT(1)
  93 WM8962_REGULATOR_EVENT(2)
  94 WM8962_REGULATOR_EVENT(3)
  95 WM8962_REGULATOR_EVENT(4)
  96 WM8962_REGULATOR_EVENT(5)
  97 WM8962_REGULATOR_EVENT(6)
  98 WM8962_REGULATOR_EVENT(7)
  99
 100 static int wm8962_volatile_register(unsigned int reg)
 101 {
 102         if (wm8962_reg_access[reg].vol)
 103                 return 1;
 104         else
 105                 return 0;
 106 }
 107
 108 static int wm8962_readable_register(unsigned int reg)
 109 {
 110         if (wm8962_reg_access[reg].read)
 111                 return 1;
 112         else
 113                 return 0;
 114 }
 115
 116 static int wm8962_reset(struct snd_soc_codec *codec)
 117 {
 118         return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
 119 }
 120
 121 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
 122 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
 123 static const unsigned int mixinpga_tlv[] = {
 124         TLV_DB_RANGE_HEAD(7),
 125         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
 126         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
 127         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
 128         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
 129         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
 130 };
 131 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
 132 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 133 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 134 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
 135 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 136 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 137 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
 138 static const unsigned int classd_tlv[] = {
 139         TLV_DB_RANGE_HEAD(7),
 140         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
 141         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
 142 };
 143
 144 /* The VU bits for the headphones are in a different register to the mute
 145  * bits and only take effect on the PGA if it is actually powered.
 146  */
 147 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
 148                             struct snd_ctl_elem_value *ucontrol)
 149 {
 150         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 151         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 152         u16 *reg_cache = wm8962->reg_cache;
 153         int ret;
 154
 155         /* Apply the update (if any) */
 156         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 157         if (ret == 0)
 158                 return 0;
 159
 160         /* If the left PGA is enabled hit that VU bit... */
 161         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
 162                 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
 163                                      reg_cache[WM8962_HPOUTL_VOLUME]);
 164
 165         /* ...otherwise the right.  The VU is stereo. */
 166         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
 167                 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
 168                                      reg_cache[WM8962_HPOUTR_VOLUME]);
 169
 170         return 0;
 171 }
 172
 173 /* The VU bits for the speakers are in a different register to the mute
 174  * bits and only take effect on the PGA if it is actually powered.
 175  */
 176 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
 177                             struct snd_ctl_elem_value *ucontrol)
 178 {
 179         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 180         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 181         u16 *reg_cache = wm8962->reg_cache;
 182         int ret;
 183
 184         /* Apply the update (if any) */
 185         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 186         if (ret == 0)
 187                 return 0;
 188
 189         /* If the left PGA is enabled hit that VU bit... */
 190         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
 191                 return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
 192                                      reg_cache[WM8962_SPKOUTL_VOLUME]);
 193
 194         /* ...otherwise the right.  The VU is stereo. */
 195         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
 196                 return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
 197                                      reg_cache[WM8962_SPKOUTR_VOLUME]);
 198
 199         return 0;
 200 }
 201
 202 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
 203 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
 204
 205 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
 206                mixin_tlv),
 207 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
 208                mixinpga_tlv),
 209 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
 210                mixin_tlv),
 211
 212 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
 213                mixin_tlv),
 214 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
 215                mixinpga_tlv),
 216 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
 217                mixin_tlv),
 218
 219 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
 220                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
 221 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
 222                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
 223 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
 224              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
 225 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
 226              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
 227
 228 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
 229                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
 230
 231 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
 232                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
 233 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
 234
 235 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
 236            5, 1, 0),
 237
 238 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
 239
 240 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
 241                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
 242 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
 243                snd_soc_get_volsw, wm8962_put_hp_sw),
 244 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
 245              7, 1, 0),
 246 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
 247                hp_tlv),
 248
 249 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
 250              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
 251
 252 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
 253                3, 7, 0, bypass_tlv),
 254 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
 255                0, 7, 0, bypass_tlv),
 256 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
 257                7, 1, 1, inmix_tlv),
 258 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
 259                6, 1, 1, inmix_tlv),
 260
 261 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
 262                3, 7, 0, bypass_tlv),
 263 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
 264                0, 7, 0, bypass_tlv),
 265 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
 266                7, 1, 1, inmix_tlv),
 267 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
 268                6, 1, 1, inmix_tlv),
 269
 270 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
 271                classd_tlv),
 272 };
 273
 274 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
 275 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
 276 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
 277                snd_soc_get_volsw, wm8962_put_spk_sw),
 278 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
 279
 280 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
 281 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
 282                3, 7, 0, bypass_tlv),
 283 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
 284                0, 7, 0, bypass_tlv),
 285 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
 286                7, 1, 1, inmix_tlv),
 287 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
 288                6, 1, 1, inmix_tlv),
 289 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
 290                7, 1, 0, inmix_tlv),
 291 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
 292                6, 1, 0, inmix_tlv),
 293 };
 294
 295 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
 296 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
 297                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
 298 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
 299                snd_soc_get_volsw, wm8962_put_spk_sw),
 300 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
 301              7, 1, 0),
 302
 303 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
 304              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
 305
 306 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
 307                3, 7, 0, bypass_tlv),
 308 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
 309                0, 7, 0, bypass_tlv),
 310 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
 311                7, 1, 1, inmix_tlv),
 312 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
 313                6, 1, 1, inmix_tlv),
 314 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
 315                7, 1, 0, inmix_tlv),
 316 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
 317                6, 1, 0, inmix_tlv),
 318
 319 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
 320                3, 7, 0, bypass_tlv),
 321 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
 322                0, 7, 0, bypass_tlv),
 323 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
 324                7, 1, 1, inmix_tlv),
 325 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
 326                6, 1, 1, inmix_tlv),
 327 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
 328                5, 1, 0, inmix_tlv),
 329 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
 330                4, 1, 0, inmix_tlv),
 331 };
 332
 333 static int sysclk_event(struct snd_soc_dapm_widget *w,
 334                         struct snd_kcontrol *kcontrol, int event)
 335 {
 336         struct snd_soc_codec *codec = w->codec;
 337         int src;
 338         int fll;
 339
 340         src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
 341
 342         switch (src) {
 343         case 0:      /* MCLK */
 344                 fll = 0;
 345                 break;
 346         case 0x200:  /* FLL */
 347                 fll = 1;
 348                 break;
 349         default:
 350                 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
 351                 return -EINVAL;
 352         }
 353
 354         switch (event) {
 355         case SND_SOC_DAPM_PRE_PMU:
 356                 if (fll)
 357                         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
 358                                             WM8962_FLL_ENA, WM8962_FLL_ENA);
 359                 break;
 360
 361         case SND_SOC_DAPM_POST_PMD:
 362                 if (fll)
 363                         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
 364                                             WM8962_FLL_ENA, 0);
 365                 break;
 366
 367         default:
 368                 BUG();
 369                 return -EINVAL;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int cp_event(struct snd_soc_dapm_widget *w,
 376                     struct snd_kcontrol *kcontrol, int event)
 377 {
 378         switch (event) {
 379         case SND_SOC_DAPM_POST_PMU:
 380                 msleep(5);
 381                 break;
 382
 383         default:
 384                 BUG();
 385                 return -EINVAL;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int hp_event(struct snd_soc_dapm_widget *w,
 392                     struct snd_kcontrol *kcontrol, int event)
 393 {
 394         struct snd_soc_codec *codec = w->codec;
 395         int timeout;
 396         int reg;
 397         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
 398                         WM8962_DCS_STARTUP_DONE_HP1R);
 399
 400         switch (event) {
 401         case SND_SOC_DAPM_POST_PMU:
 402                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 403                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
 404                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
 405                 udelay(20);
 406
 407                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 408                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
 409                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
 410
 411                 /* Start the DC servo */
 412                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
 413                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
 414                                     WM8962_HP1L_DCS_STARTUP |
 415                                     WM8962_HP1R_DCS_STARTUP,
 416                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
 417                                     WM8962_HP1L_DCS_STARTUP |
 418                                     WM8962_HP1R_DCS_STARTUP);
 419
 420                 /* Wait for it to complete, should be well under 100ms */
 421                 timeout = 0;
 422                 do {
 423                         msleep(1);
 424                         reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
 425                         if (reg < 0) {
 426                                 dev_err(codec->dev,
 427                                         "Failed to read DCS status: %d\n",
 428                                         reg);
 429                                 continue;
 430                         }
 431                         dev_dbg(codec->dev, "DCS status: %x\n", reg);
 432                 } while (++timeout < 200 && (reg & expected) != expected);
 433
 434                 if ((reg & expected) != expected)
 435                         dev_err(codec->dev, "DC servo timed out\n");
 436                 else
 437                         dev_dbg(codec->dev, "DC servo complete after %dms\n",
 438                                 timeout);
 439
 440                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 441                                     WM8962_HP1L_ENA_OUTP |
 442                                     WM8962_HP1R_ENA_OUTP,
 443                                     WM8962_HP1L_ENA_OUTP |
 444                                     WM8962_HP1R_ENA_OUTP);
 445                 udelay(20);
 446
 447                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 448                                     WM8962_HP1L_RMV_SHORT |
 449                                     WM8962_HP1R_RMV_SHORT,
 450                                     WM8962_HP1L_RMV_SHORT |
 451                                     WM8962_HP1R_RMV_SHORT);
 452                 break;
 453
 454         case SND_SOC_DAPM_PRE_PMD:
 455                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 456                                     WM8962_HP1L_RMV_SHORT |
 457                                     WM8962_HP1R_RMV_SHORT, 0);
 458
 459                 udelay(20);
 460
 461                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
 462                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
 463                                     WM8962_HP1L_DCS_STARTUP |
 464                                     WM8962_HP1R_DCS_STARTUP,
 465                                     0);
 466
 467                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
 468                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
 469                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
 470                                     WM8962_HP1L_ENA_OUTP |
 471                                     WM8962_HP1R_ENA_OUTP, 0);
 472
 473                 break;
 474
 475         default:
 476                 BUG();
 477                 return -EINVAL;
 478
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* VU bits for the output PGAs only take effect while the PGA is powered */
 485 static int out_pga_event(struct snd_soc_dapm_widget *w,
 486                          struct snd_kcontrol *kcontrol, int event)
 487 {
 488         struct snd_soc_codec *codec = w->codec;
 489         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 490         u16 *reg_cache = wm8962->reg_cache;
 491         int reg;
 492
 493         switch (w->shift) {
 494         case WM8962_HPOUTR_PGA_ENA_SHIFT:
 495                 reg = WM8962_HPOUTR_VOLUME;
 496                 break;
 497         case WM8962_HPOUTL_PGA_ENA_SHIFT:
 498                 reg = WM8962_HPOUTL_VOLUME;
 499                 break;
 500         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
 501                 reg = WM8962_SPKOUTR_VOLUME;
 502                 break;
 503         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
 504                 reg = WM8962_SPKOUTL_VOLUME;
 505                 break;
 506         default:
 507                 BUG();
 508                 return -EINVAL;
 509         }
 510
 511         switch (event) {
 512         case SND_SOC_DAPM_POST_PMU:
 513                 return snd_soc_write(codec, reg, reg_cache[reg]);
 514         default:
 515                 BUG();
 516                 return -EINVAL;
 517         }
 518 }
 519
 520 static const char *st_text[] = { "None", "Right", "Left" };
 521
 522 static const struct soc_enum str_enum =
 523         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
 524
 525 static const struct snd_kcontrol_new str_mux =
 526         SOC_DAPM_ENUM("Right Sidetone", str_enum);
 527
 528 static const struct soc_enum stl_enum =
 529         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
 530
 531 static const struct snd_kcontrol_new stl_mux =
 532         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
 533
 534 static const char *outmux_text[] = { "DAC", "Mixer" };
 535
 536 static const struct soc_enum spkoutr_enum =
 537         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
 538
 539 static const struct snd_kcontrol_new spkoutr_mux =
 540         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
 541
 542 static const struct soc_enum spkoutl_enum =
 543         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
 544
 545 static const struct snd_kcontrol_new spkoutl_mux =
 546         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
 547
 548 static const struct soc_enum hpoutr_enum =
 549         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
 550
 551 static const struct snd_kcontrol_new hpoutr_mux =
 552         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
 553
 554 static const struct soc_enum hpoutl_enum =
 555         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
 556
 557 static const struct snd_kcontrol_new hpoutl_mux =
 558         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
 559
 560 static const struct snd_kcontrol_new inpgal[] = {
 561 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
 562 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
 563 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
 564 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
 565 };
 566
 567 static const struct snd_kcontrol_new inpgar[] = {
 568 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
 569 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
 570 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
 571 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
 572 };
 573
 574 static const struct snd_kcontrol_new mixinl[] = {
 575 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
 576 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
 577 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
 578 };
 579
 580 static const struct snd_kcontrol_new mixinr[] = {
 581 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
 582 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
 583 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
 584 };
 585
 586 static const struct snd_kcontrol_new hpmixl[] = {
 587 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
 588 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
 589 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
 590 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
 591 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
 592 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
 593 };
 594
 595 static const struct snd_kcontrol_new hpmixr[] = {
 596 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
 597 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
 598 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
 599 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
 600 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
 601 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
 602 };
 603
 604 static const struct snd_kcontrol_new spkmixl[] = {
 605 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
 606 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
 607 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
 608 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
 609 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
 610 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
 611 };
 612
 613 static const struct snd_kcontrol_new spkmixr[] = {
 614 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
 615 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
 616 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
 617 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
 618 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
 619 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
 620 };
 621
 622 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
 623 SND_SOC_DAPM_INPUT("IN1L"),
 624 SND_SOC_DAPM_INPUT("IN1R"),
 625 SND_SOC_DAPM_INPUT("IN2L"),
 626 SND_SOC_DAPM_INPUT("IN2R"),
 627 SND_SOC_DAPM_INPUT("IN3L"),
 628 SND_SOC_DAPM_INPUT("IN3R"),
 629 SND_SOC_DAPM_INPUT("IN4L"),
 630 SND_SOC_DAPM_INPUT("IN4R"),
 631 SND_SOC_DAPM_INPUT("Beep"),
 632
 633 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
 634 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
 635                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 636 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
 637                     SND_SOC_DAPM_POST_PMU),
 638 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
 639
 640 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
 641                    inpgal, ARRAY_SIZE(inpgal)),
 642 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
 643                    inpgar, ARRAY_SIZE(inpgar)),
 644 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
 645                    mixinl, ARRAY_SIZE(mixinl)),
 646 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
 647                    mixinr, ARRAY_SIZE(mixinr)),
 648
 649 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
 650 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
 651
 652 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
 653 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
 654
 655 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
 656 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
 657
 658 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
 659 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
 660
 661 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
 662                    hpmixl, ARRAY_SIZE(hpmixl)),
 663 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
 664                    hpmixr, ARRAY_SIZE(hpmixr)),
 665
 666 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
 667                    out_pga_event, SND_SOC_DAPM_POST_PMU),
 668 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
 669                    out_pga_event, SND_SOC_DAPM_POST_PMU),
 670
 671 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
 672                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 673
 674 SND_SOC_DAPM_OUTPUT("HPOUTL"),
 675 SND_SOC_DAPM_OUTPUT("HPOUTR"),
 676 };
 677
 678 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
 679 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
 680                    spkmixl, ARRAY_SIZE(spkmixl)),
 681 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
 682                    out_pga_event, SND_SOC_DAPM_POST_PMU),
 683 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
 684 SND_SOC_DAPM_OUTPUT("SPKOUT"),
 685 };
 686
 687 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
 688 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
 689                    spkmixl, ARRAY_SIZE(spkmixl)),
 690 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
 691                    spkmixr, ARRAY_SIZE(spkmixr)),
 692
 693 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
 694                    out_pga_event, SND_SOC_DAPM_POST_PMU),
 695 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
 696                    out_pga_event, SND_SOC_DAPM_POST_PMU),
 697
 698 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
 699 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
 700
 701 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
 702 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
 703 };
 704
 705 static const struct snd_soc_dapm_route wm8962_intercon[] = {
 706         { "INPGAL", "IN1L Switch", "IN1L" },
 707         { "INPGAL", "IN2L Switch", "IN2L" },
 708         { "INPGAL", "IN3L Switch", "IN3L" },
 709         { "INPGAL", "IN4L Switch", "IN4L" },
 710
 711         { "INPGAR", "IN1R Switch", "IN1R" },
 712         { "INPGAR", "IN2R Switch", "IN2R" },
 713         { "INPGAR", "IN3R Switch", "IN3R" },
 714         { "INPGAR", "IN4R Switch", "IN4R" },
 715
 716         { "MIXINL", "IN2L Switch", "IN2L" },
 717         { "MIXINL", "IN3L Switch", "IN3L" },
 718         { "MIXINL", "PGA Switch", "INPGAL" },
 719
 720         { "MIXINR", "IN2R Switch", "IN2R" },
 721         { "MIXINR", "IN3R Switch", "IN3R" },
 722         { "MIXINR", "PGA Switch", "INPGAR" },
 723
 724         { "ADCL", NULL, "SYSCLK" },
 725         { "ADCL", NULL, "TOCLK" },
 726         { "ADCL", NULL, "MIXINL" },
 727
 728         { "ADCR", NULL, "SYSCLK" },
 729         { "ADCR", NULL, "TOCLK" },
 730         { "ADCR", NULL, "MIXINR" },
 731
 732         { "STL", "Left", "ADCL" },
 733         { "STL", "Right", "ADCR" },
 734
 735         { "STR", "Left", "ADCL" },
 736         { "STR", "Right", "ADCR" },
 737
 738         { "DACL", NULL, "SYSCLK" },
 739         { "DACL", NULL, "TOCLK" },
 740         { "DACL", NULL, "Beep" },
 741         { "DACL", NULL, "STL" },
 742
 743         { "DACR", NULL, "SYSCLK" },
 744         { "DACR", NULL, "TOCLK" },
 745         { "DACR", NULL, "Beep" },
 746         { "DACR", NULL, "STR" },
 747
 748         { "HPMIXL", "IN4L Switch", "IN4L" },
 749         { "HPMIXL", "IN4R Switch", "IN4R" },
 750         { "HPMIXL", "DACL Switch", "DACL" },
 751         { "HPMIXL", "DACR Switch", "DACR" },
 752         { "HPMIXL", "MIXINL Switch", "MIXINL" },
 753         { "HPMIXL", "MIXINR Switch", "MIXINR" },
 754
 755         { "HPMIXR", "IN4L Switch", "IN4L" },
 756         { "HPMIXR", "IN4R Switch", "IN4R" },
 757         { "HPMIXR", "DACL Switch", "DACL" },
 758         { "HPMIXR", "DACR Switch", "DACR" },
 759         { "HPMIXR", "MIXINL Switch", "MIXINL" },
 760         { "HPMIXR", "MIXINR Switch", "MIXINR" },
 761
 762         { "Left Bypass", NULL, "HPMIXL" },
 763         { "Left Bypass", NULL, "Class G" },
 764
 765         { "Right Bypass", NULL, "HPMIXR" },
 766         { "Right Bypass", NULL, "Class G" },
 767
 768         { "HPOUTL PGA", "Mixer", "Left Bypass" },
 769         { "HPOUTL PGA", "DAC", "DACL" },
 770
 771         { "HPOUTR PGA", "Mixer", "Right Bypass" },
 772         { "HPOUTR PGA", "DAC", "DACR" },
 773
 774         { "HPOUT", NULL, "HPOUTL PGA" },
 775         { "HPOUT", NULL, "HPOUTR PGA" },
 776         { "HPOUT", NULL, "Charge Pump" },
 777         { "HPOUT", NULL, "SYSCLK" },
 778         { "HPOUT", NULL, "TOCLK" },
 779
 780         { "HPOUTL", NULL, "HPOUT" },
 781         { "HPOUTR", NULL, "HPOUT" },
 782 };
 783
 784 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
 785         { "Speaker Mixer", "IN4L Switch", "IN4L" },
 786         { "Speaker Mixer", "IN4R Switch", "IN4R" },
 787         { "Speaker Mixer", "DACL Switch", "DACL" },
 788         { "Speaker Mixer", "DACR Switch", "DACR" },
 789         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
 790         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
 791
 792         { "Speaker PGA", "Mixer", "Speaker Mixer" },
 793         { "Speaker PGA", "DAC", "DACL" },
 794
 795         { "Speaker Output", NULL, "Speaker PGA" },
 796         { "Speaker Output", NULL, "SYSCLK" },
 797         { "Speaker Output", NULL, "TOCLK" },
 798
 799         { "SPKOUT", NULL, "Speaker Output" },
 800 };
 801
 802 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
 803         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
 804         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
 805         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
 806         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
 807         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
 808         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
 809
 810         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
 811         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
 812         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
 813         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
 814         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
 815         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
 816
 817         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
 818         { "SPKOUTL PGA", "DAC", "DACL" },
 819
 820         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
 821         { "SPKOUTR PGA", "DAC", "DACR" },
 822
 823         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
 824         { "SPKOUTL Output", NULL, "SYSCLK" },
 825         { "SPKOUTL Output", NULL, "TOCLK" },
 826
 827         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
 828         { "SPKOUTR Output", NULL, "SYSCLK" },
 829         { "SPKOUTR Output", NULL, "TOCLK" },
 830
 831         { "SPKOUTL", NULL, "SPKOUTL Output" },
 832         { "SPKOUTR", NULL, "SPKOUTR Output" },
 833 };
 834
 835 static int wm8962_add_widgets(struct snd_soc_codec *codec)
 836 {
 837         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
 838
 839         snd_soc_add_controls(codec, wm8962_snd_controls,
 840                              ARRAY_SIZE(wm8962_snd_controls));
 841         if (pdata && pdata->spk_mono)
 842                 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
 843                                      ARRAY_SIZE(wm8962_spk_mono_controls));
 844         else
 845                 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
 846                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
 847
 848
 849         snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
 850                                   ARRAY_SIZE(wm8962_dapm_widgets));
 851         if (pdata && pdata->spk_mono)
 852                 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
 853                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
 854         else
 855                 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
 856                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
 857
 858         snd_soc_dapm_add_routes(codec, wm8962_intercon,
 859                                 ARRAY_SIZE(wm8962_intercon));
 860         if (pdata && pdata->spk_mono)
 861                 snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
 862                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
 863         else
 864                 snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
 865                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
 866
 867
 868         snd_soc_dapm_disable_pin(codec, "Beep");
 869
 870         return 0;
 871 }
 872
 873 static void wm8962_sync_cache(struct snd_soc_codec *codec)
 874 {
 875         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 876         int i;
 877
 878         if (!codec->cache_sync)
 879                 return;
 880
 881         dev_dbg(codec->dev, "Syncing cache\n");
 882
 883         codec->cache_only = 0;
 884
 885         /* Sync back cached values if they're different from the
 886          * hardware default.
 887          */
 888         for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
 889                 if (i == WM8962_SOFTWARE_RESET)
 890                         continue;
 891                 if (wm8962->reg_cache[i] == wm8962_reg[i])
 892                         continue;
 893
 894                 snd_soc_write(codec, i, wm8962->reg_cache[i]);
 895         }
 896
 897         codec->cache_sync = 0;
 898 }
 899
 900 /* -1 for reserved values */
 901 static const int bclk_divs[] = {
 902         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
 903 };
 904
 905 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
 906 {
 907         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 908         int dspclk, i;
 909         int clocking2 = 0;
 910         int aif2 = 0;
 911
 912         /* If the CODEC is powered on we can configure BCLK */
 913         if (codec->bias_level != SND_SOC_BIAS_OFF) {
 914                 dev_dbg(codec->dev, "Bias is off, can't configure BCLK\n");
 915                 return;
 916         }
 917
 918         if (!wm8962->bclk) {
 919                 dev_dbg(codec->dev, "No BCLK rate configured\n");
 920                 return;
 921         }
 922
 923         dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
 924         if (dspclk < 0) {
 925                 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
 926                 return;
 927         }
 928
 929         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
 930         switch (dspclk) {
 931         case 0:
 932                 dspclk = wm8962->sysclk_rate;
 933                 break;
 934         case 1:
 935                 dspclk = wm8962->sysclk_rate / 2;
 936                 break;
 937         case 2:
 938                 dspclk = wm8962->sysclk_rate / 4;
 939                 break;
 940         default:
 941                 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
 942                 dspclk = wm8962->sysclk;
 943         }
 944
 945         dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
 946
 947         /* We're expecting an exact match */
 948         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
 949                 if (bclk_divs[i] < 0)
 950                         continue;
 951
 952                 if (dspclk / bclk_divs[i] == wm8962->bclk) {
 953                         dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
 954                                 bclk_divs[i], wm8962->bclk);
 955                         clocking2 |= i;
 956                         break;
 957                 }
 958         }
 959         if (i == ARRAY_SIZE(bclk_divs)) {
 960                 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
 961                         dspclk / wm8962->bclk);
 962                 return;
 963         }
 964
 965         aif2 |= wm8962->bclk / wm8962->lrclk;
 966         dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
 967                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
 968
 969         snd_soc_update_bits(codec, WM8962_CLOCKING2,
 970                             WM8962_BCLK_DIV_MASK, clocking2);
 971         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
 972                             WM8962_AIF_RATE_MASK, aif2);
 973 }
 974
 975 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
 976                                  enum snd_soc_bias_level level)
 977 {
 978         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
 979         int ret;
 980
 981         if (level == codec->bias_level)
 982                 return 0;
 983
 984         switch (level) {
 985         case SND_SOC_BIAS_ON:
 986                 break;
 987
 988         case SND_SOC_BIAS_PREPARE:
 989                 /* VMID 2*50k */
 990                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
 991                                     WM8962_VMID_SEL_MASK, 0x80);
 992                 break;
 993
 994         case SND_SOC_BIAS_STANDBY:
 995                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 996                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
 997                                                     wm8962->supplies);
 998                         if (ret != 0) {
 999                                 dev_err(codec->dev,
1000                                         "Failed to enable supplies: %d\n",
1001                                         ret);
1002                                 return ret;
1003                         }
1004
1005                         wm8962_sync_cache(codec);
1006
1007                         snd_soc_update_bits(codec, WM8962_ANTI_POP,
1008                                             WM8962_STARTUP_BIAS_ENA |
1009                                             WM8962_VMID_BUF_ENA,
1010                                             WM8962_STARTUP_BIAS_ENA |
1011                                             WM8962_VMID_BUF_ENA);
1012
1013                         /* Bias enable at 2*50k for ramp */
1014                         snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1015                                             WM8962_VMID_SEL_MASK |
1016                                             WM8962_BIAS_ENA,
1017                                             WM8962_BIAS_ENA | 0x180);
1018
1019                         msleep(5);
1020
1021                         snd_soc_update_bits(codec, WM8962_CLOCKING2,
1022                                             WM8962_CLKREG_OVD,
1023                                             WM8962_CLKREG_OVD);
1024
1025                         wm8962_configure_bclk(codec);
1026                 }
1027
1028                 /* VMID 2*250k */
1029                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1030                                     WM8962_VMID_SEL_MASK, 0x100);
1031                 break;
1032
1033         case SND_SOC_BIAS_OFF:
1034                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1035                                     WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
1036
1037                 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1038                                     WM8962_STARTUP_BIAS_ENA |
1039                                     WM8962_VMID_BUF_ENA, 0);
1040
1041                 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
1042                                        wm8962->supplies);
1043                 break;
1044         }
1045         codec->bias_level = level;
1046         return 0;
1047 }
1048
1049 static const struct {
1050         int rate;
1051         int reg;
1052 } sr_vals[] = {
1053         { 48000, 0 },
1054         { 44100, 0 },
1055         { 32000, 1 },
1056         { 22050, 2 },
1057         { 24000, 2 },
1058         { 16000, 3 },
1059         { 11025, 4 },
1060         { 12000, 4 },
1061         { 8000,  5 },
1062         { 88200, 6 },
1063         { 96000, 6 },
1064 };
1065
1066 static const int sysclk_rates[] = {
1067         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
1068 };
1069
1070 static int wm8962_hw_params(struct snd_pcm_substream *substream,
1071                             struct snd_pcm_hw_params *params,
1072                             struct snd_soc_dai *dai)
1073 {
1074         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1075         struct snd_soc_codec *codec = rtd->codec;
1076         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1077         int rate = params_rate(params);
1078         int i;
1079         int aif0 = 0;
1080         int adctl3 = 0;
1081         int clocking4 = 0;
1082
1083         wm8962->bclk = snd_soc_params_to_bclk(params);
1084         wm8962->lrclk = params_rate(params);
1085
1086         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
1087                 if (sr_vals[i].rate == rate) {
1088                         adctl3 |= sr_vals[i].reg;
1089                         break;
1090                 }
1091         }
1092         if (i == ARRAY_SIZE(sr_vals)) {
1093                 dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
1094                 return -EINVAL;
1095         }
1096
1097         if (rate % 8000 == 0)
1098                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
1099
1100         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
1101                 if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
1102                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
1103                         break;
1104                 }
1105         }
1106         if (i == ARRAY_SIZE(sysclk_rates)) {
1107                 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
1108                         wm8962->sysclk_rate / rate);
1109                 return -EINVAL;
1110         }
1111
1112         switch (params_format(params)) {
1113         case SNDRV_PCM_FORMAT_S16_LE:
1114                 break;
1115         case SNDRV_PCM_FORMAT_S20_3LE:
1116                 aif0 |= 0x40;
1117                 break;
1118         case SNDRV_PCM_FORMAT_S24_LE:
1119                 aif0 |= 0x80;
1120                 break;
1121         case SNDRV_PCM_FORMAT_S32_LE:
1122                 aif0 |= 0xc0;
1123                 break;
1124         default:
1125                 return -EINVAL;
1126         }
1127
1128         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1129                             WM8962_WL_MASK, aif0);
1130         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
1131                             WM8962_SAMPLE_RATE_INT_MODE |
1132                             WM8962_SAMPLE_RATE_MASK, adctl3);
1133         snd_soc_update_bits(codec, WM8962_CLOCKING_4,
1134                             WM8962_SYSCLK_RATE_MASK, clocking4);
1135
1136         wm8962_configure_bclk(codec);
1137
1138         return 0;
1139 }
1140
1141 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1142                                  unsigned int freq, int dir)
1143 {
1144         struct snd_soc_codec *codec = dai->codec;
1145         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1146         int src;
1147
1148         switch (clk_id) {
1149         case WM8962_SYSCLK_MCLK:
1150                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
1151                 src = 0;
1152                 break;
1153         case WM8962_SYSCLK_FLL:
1154                 wm8962->sysclk = WM8962_SYSCLK_FLL;
1155                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
1156                 WARN_ON(freq != wm8962->fll_fout);
1157                 break;
1158         default:
1159                 return -EINVAL;
1160         }
1161
1162         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
1163                             src);
1164
1165         wm8962->sysclk_rate = freq;
1166
1167         return 0;
1168 }
1169
1170 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1171 {
1172         struct snd_soc_codec *codec = dai->codec;
1173         int aif0 = 0;
1174
1175         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1176         case SND_SOC_DAIFMT_DSP_A:
1177                 aif0 |= WM8962_LRCLK_INV;
1178         case SND_SOC_DAIFMT_DSP_B:
1179                 aif0 |= 3;
1180
1181                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1182                 case SND_SOC_DAIFMT_NB_NF:
1183                 case SND_SOC_DAIFMT_IB_NF:
1184                         break;
1185                 default:
1186                         return -EINVAL;
1187                 }
1188                 break;
1189
1190         case SND_SOC_DAIFMT_RIGHT_J:
1191                 break;
1192         case SND_SOC_DAIFMT_LEFT_J:
1193                 aif0 |= 1;
1194                 break;
1195         case SND_SOC_DAIFMT_I2S:
1196                 aif0 |= 2;
1197                 break;
1198         default:
1199                 return -EINVAL;
1200         }
1201
1202         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1203         case SND_SOC_DAIFMT_NB_NF:
1204                 break;
1205         case SND_SOC_DAIFMT_IB_NF:
1206                 aif0 |= WM8962_BCLK_INV;
1207                 break;
1208         case SND_SOC_DAIFMT_NB_IF:
1209                 aif0 |= WM8962_LRCLK_INV;
1210                 break;
1211         case SND_SOC_DAIFMT_IB_IF:
1212                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
1213                 break;
1214         default:
1215                 return -EINVAL;
1216         }
1217
1218         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1219         case SND_SOC_DAIFMT_CBM_CFM:
1220                 aif0 |= WM8962_MSTR;
1221                 break;
1222         case SND_SOC_DAIFMT_CBS_CFS:
1223                 break;
1224         default:
1225                 return -EINVAL;
1226         }
1227
1228         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1229                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
1230                             WM8962_LRCLK_INV, aif0);
1231
1232         return 0;
1233 }
1234
1235 struct _fll_div {
1236         u16 fll_fratio;
1237         u16 fll_outdiv;
1238         u16 fll_refclk_div;
1239         u16 n;
1240         u16 theta;
1241         u16 lambda;
1242 };
1243
1244 /* The size in bits of the FLL divide multiplied by 10
1245  * to allow rounding later */
1246 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1247
1248 static struct {
1249         unsigned int min;
1250         unsigned int max;
1251         u16 fll_fratio;
1252         int ratio;
1253 } fll_fratios[] = {
1254         {       0,    64000, 4, 16 },
1255         {   64000,   128000, 3,  8 },
1256         {  128000,   256000, 2,  4 },
1257         {  256000,  1000000, 1,  2 },
1258         { 1000000, 13500000, 0,  1 },
1259 };
1260
1261 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1262                        unsigned int Fout)
1263 {
1264         unsigned int target;
1265         unsigned int div;
1266         unsigned int fratio, gcd_fll;
1267         int i;
1268
1269         /* Fref must be <=13.5MHz */
1270         div = 1;
1271         fll_div->fll_refclk_div = 0;
1272         while ((Fref / div) > 13500000) {
1273                 div *= 2;
1274                 fll_div->fll_refclk_div++;
1275
1276                 if (div > 4) {
1277                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1278                                Fref);
1279                         return -EINVAL;
1280                 }
1281         }
1282
1283         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1284
1285         /* Apply the division for our remaining calculations */
1286         Fref /= div;
1287
1288         /* Fvco should be 90-100MHz; don't check the upper bound */
1289         div = 2;
1290         while (Fout * div < 90000000) {
1291                 div++;
1292                 if (div > 64) {
1293                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1294                                Fout);
1295                         return -EINVAL;
1296                 }
1297         }
1298         target = Fout * div;
1299         fll_div->fll_outdiv = div - 1;
1300
1301         pr_debug("FLL Fvco=%dHz\n", target);
1302
1303         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1304         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1305                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1306                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1307                         fratio = fll_fratios[i].ratio;
1308                         break;
1309                 }
1310         }
1311         if (i == ARRAY_SIZE(fll_fratios)) {
1312                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1313                 return -EINVAL;
1314         }
1315
1316         fll_div->n = target / (fratio * Fref);
1317
1318         if (target % Fref == 0) {
1319                 fll_div->theta = 0;
1320                 fll_div->lambda = 0;
1321         } else {
1322                 gcd_fll = gcd(target, fratio * Fref);
1323
1324                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1325                         / gcd_fll;
1326                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1327         }
1328
1329         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1330                  fll_div->n, fll_div->theta, fll_div->lambda);
1331         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1332                  fll_div->fll_fratio, fll_div->fll_outdiv,
1333                  fll_div->fll_refclk_div);
1334
1335         return 0;
1336 }
1337
1338 static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1339                           unsigned int Fref, unsigned int Fout)
1340 {
1341         struct snd_soc_codec *codec = dai->codec;
1342         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1343         struct _fll_div fll_div;
1344         int ret;
1345         int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1);
1346
1347         /* Any change? */
1348         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
1349             Fout == wm8962->fll_fout)
1350                 return 0;
1351
1352         if (Fout == 0) {
1353                 dev_dbg(codec->dev, "FLL disabled\n");
1354
1355                 wm8962->fll_fref = 0;
1356                 wm8962->fll_fout = 0;
1357
1358                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1359                                     WM8962_FLL_ENA, 0);
1360
1361                 return 0;
1362         }
1363
1364         ret = fll_factors(&fll_div, Fref, Fout);
1365         if (ret != 0)
1366                 return ret;
1367
1368         switch (fll_id) {
1369         case WM8962_FLL_MCLK:
1370         case WM8962_FLL_BCLK:
1371         case WM8962_FLL_OSC:
1372                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
1373                 break;
1374         case WM8962_FLL_INT:
1375                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1376                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
1377                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
1378                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
1379                 break;
1380         default:
1381                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
1382                 return -EINVAL;
1383         }
1384
1385         if (fll_div.theta || fll_div.lambda)
1386                 fll1 |= WM8962_FLL_FRAC;
1387
1388         /* Stop the FLL while we reconfigure */
1389         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
1390
1391         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
1392                             WM8962_FLL_OUTDIV_MASK |
1393                             WM8962_FLL_REFCLK_DIV_MASK,
1394                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
1395                             (fll_div.fll_refclk_div));
1396
1397         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
1398                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
1399
1400         snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
1401         snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
1402         snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
1403
1404         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1405                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
1406                             WM8962_FLL_ENA, fll1);
1407
1408         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1409
1410         wm8962->fll_fref = Fref;
1411         wm8962->fll_fout = Fout;
1412         wm8962->fll_src = source;
1413
1414         return 0;
1415 }
1416
1417 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
1418 {
1419         struct snd_soc_codec *codec = dai->codec;
1420         int val;
1421
1422         if (mute)
1423                 val = WM8962_DAC_MUTE;
1424         else
1425                 val = 0;
1426
1427         return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1428                                    WM8962_DAC_MUTE, val);
1429 }
1430
1431 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
1432
1433 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1434                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1435
1436 static struct snd_soc_dai_ops wm8962_dai_ops = {
1437         .hw_params = wm8962_hw_params,
1438         .set_sysclk = wm8962_set_dai_sysclk,
1439         .set_fmt = wm8962_set_dai_fmt,
1440         .set_pll = wm8962_set_fll,
1441         .digital_mute = wm8962_mute,
1442 };
1443
1444 static struct snd_soc_dai_driver wm8962_dai = {
1445         .name = "wm8962",
1446         .playback = {
1447                 .stream_name = "Playback",
1448                 .channels_min = 2,
1449                 .channels_max = 2,
1450                 .rates = WM8962_RATES,
1451                 .formats = WM8962_FORMATS,
1452         },
1453         .capture = {
1454                 .stream_name = "Capture",
1455                 .channels_min = 2,
1456                 .channels_max = 2,
1457                 .rates = WM8962_RATES,
1458                 .formats = WM8962_FORMATS,
1459         },
1460         .ops = &wm8962_dai_ops,
1461         .symmetric_rates = 1,
1462 };
1463
1464 #ifdef CONFIG_PM
1465 static int wm8962_resume(struct snd_soc_codec *codec)
1466 {
1467         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1468         u16 *reg_cache = codec->reg_cache;
1469         int i;
1470
1471         /* Restore the registers */
1472         for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
1473                 switch (i) {
1474                 case WM8962_SOFTWARE_RESET:
1475                         continue;
1476                 default:
1477                         break;
1478                 }
1479
1480                 if (reg_cache[i] != wm8962_reg[i])
1481                         snd_soc_write(codec, i, reg_cache[i]);
1482         }
1483
1484         return 0;
1485 }
1486 #else
1487 #define wm8962_resume NULL
1488 #endif
1489
1490 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
1491 static int beep_rates[] = {
1492         500, 1000, 2000, 4000,
1493 };
1494
1495 static void wm8962_beep_work(struct work_struct *work)
1496 {
1497         struct wm8962_priv *wm8962 =
1498                 container_of(work, struct wm8962_priv, beep_work);
1499         struct snd_soc_codec *codec = wm8962->codec;
1500         int i;
1501         int reg = 0;
1502         int best = 0;
1503
1504         if (wm8962->beep_rate) {
1505                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
1506                         if (abs(wm8962->beep_rate - beep_rates[i]) <
1507                             abs(wm8962->beep_rate - beep_rates[best]))
1508                                 best = i;
1509                 }
1510
1511                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
1512                         beep_rates[best], wm8962->beep_rate);
1513
1514                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
1515
1516                 snd_soc_dapm_enable_pin(codec, "Beep");
1517         } else {
1518                 dev_dbg(codec->dev, "Disabling beep\n");
1519                 snd_soc_dapm_disable_pin(codec, "Beep");
1520         }
1521
1522         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
1523                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
1524
1525         snd_soc_dapm_sync(codec);
1526 }
1527
1528 /* For usability define a way of injecting beep events for the device -
1529  * many systems will not have a keyboard.
1530  */
1531 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
1532                              unsigned int code, int hz)
1533 {
1534         struct snd_soc_codec *codec = input_get_drvdata(dev);
1535         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1536
1537         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1538
1539         switch (code) {
1540         case SND_BELL:
1541                 if (hz)
1542                         hz = 1000;
1543         case SND_TONE:
1544                 break;
1545         default:
1546                 return -1;
1547         }
1548
1549         /* Kick the beep from a workqueue */
1550         wm8962->beep_rate = hz;
1551         schedule_work(&wm8962->beep_work);
1552         return 0;
1553 }
1554
1555 static ssize_t wm8962_beep_set(struct device *dev,
1556                                struct device_attribute *attr,
1557                                const char *buf, size_t count)
1558 {
1559         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
1560         long int time;
1561
1562         strict_strtol(buf, 10, &time);
1563
1564         input_event(wm8962->beep, EV_SND, SND_TONE, time);
1565
1566         return count;
1567 }
1568
1569 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
1570
1571 static void wm8962_init_beep(struct snd_soc_codec *codec)
1572 {
1573         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1574         int ret;
1575
1576         wm8962->beep = input_allocate_device();
1577         if (!wm8962->beep) {
1578                 dev_err(codec->dev, "Failed to allocate beep device\n");
1579                 return;
1580         }
1581
1582         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
1583         wm8962->beep_rate = 0;
1584
1585         wm8962->beep->name = "WM8962 Beep Generator";
1586         wm8962->beep->phys = dev_name(codec->dev);
1587         wm8962->beep->id.bustype = BUS_I2C;
1588
1589         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
1590         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1591         wm8962->beep->event = wm8962_beep_event;
1592         wm8962->beep->dev.parent = codec->dev;
1593         input_set_drvdata(wm8962->beep, codec);
1594
1595         ret = input_register_device(wm8962->beep);
1596         if (ret != 0) {
1597                 input_free_device(wm8962->beep);
1598                 wm8962->beep = NULL;
1599                 dev_err(codec->dev, "Failed to register beep device\n");
1600         }
1601
1602         ret = device_create_file(codec->dev, &dev_attr_beep);
1603         if (ret != 0) {
1604                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1605                         ret);
1606         }
1607 }
1608
1609 static void wm8962_free_beep(struct snd_soc_codec *codec)
1610 {
1611         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1612
1613         device_remove_file(codec->dev, &dev_attr_beep);
1614         input_unregister_device(wm8962->beep);
1615         cancel_work_sync(&wm8962->beep_work);
1616         wm8962->beep = NULL;
1617
1618         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
1619 }
1620 #else
1621 static void wm8962_init_beep(struct snd_soc_codec *codec)
1622 {
1623 }
1624
1625 static void wm8962_free_beep(struct snd_soc_codec *codec)
1626 {
1627 }
1628 #endif
1629
1630 static int wm8962_probe(struct snd_soc_codec *codec)
1631 {
1632         int ret;
1633         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1634         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
1635         int i;
1636
1637         wm8962->codec = codec;
1638
1639         codec->cache_sync = 1;
1640         codec->idle_bias_off = 1;
1641
1642         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1643         if (ret != 0) {
1644                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1645                 goto err;
1646         }
1647
1648         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1649                 wm8962->supplies[i].supply = wm8962_supply_names[i];
1650
1651         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
1652                                  wm8962->supplies);
1653         if (ret != 0) {
1654                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1655                 goto err;
1656         }
1657
1658         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
1659         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
1660         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
1661         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
1662         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
1663         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
1664         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
1665         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
1666
1667         /* This should really be moved into the regulator core */
1668         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
1669                 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
1670                                                   &wm8962->disable_nb[i]);
1671                 if (ret != 0) {
1672                         dev_err(codec->dev,
1673                                 "Failed to register regulator notifier: %d\n",
1674                                 ret);
1675                 }
1676         }
1677
1678         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
1679                                     wm8962->supplies);
1680         if (ret != 0) {
1681                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1682                 goto err_get;
1683         }
1684
1685         ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
1686         if (ret < 0) {
1687                 dev_err(codec->dev, "Failed to read ID register\n");
1688                 goto err_enable;
1689         }
1690         if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
1691                 dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
1692                         ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
1693                 ret = -EINVAL;
1694                 goto err_enable;
1695         }
1696
1697         ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
1698         if (ret < 0) {
1699                 dev_err(codec->dev, "Failed to read device revision: %d\n",
1700                         ret);
1701                 goto err_enable;
1702         }
1703
1704         dev_info(codec->dev, "customer id %x revision %c\n",
1705                  (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
1706                  ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
1707                  + 'A');
1708
1709         ret = wm8962_reset(codec);
1710         if (ret < 0) {
1711                 dev_err(codec->dev, "Failed to issue reset\n");
1712                 goto err_enable;
1713         }
1714
1715         /* SYSCLK defaults to on; make sure it is off so we can safely
1716          * write to registers if the device is declocked.
1717          */
1718         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
1719
1720         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1721
1722         if (pdata) {
1723                 /* Apply static configuration for GPIOs */
1724                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
1725                         if (pdata->gpio_init[i])
1726                                 snd_soc_write(codec, 0x200 + i,
1727                                               pdata->gpio_init[i] & 0xffff);
1728
1729                 /* Put the speakers into mono mode? */
1730                 if (pdata->spk_mono)
1731                         wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
1732                                 |= WM8962_SPK_MONO;
1733         }
1734
1735         /* Latch volume update bits */
1736         wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
1737         wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
1738         wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
1739         wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
1740         wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
1741         wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
1742         wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
1743         wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
1744         wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
1745         wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
1746
1747         snd_soc_add_controls(codec, wm8962_snd_controls,
1748                              ARRAY_SIZE(wm8962_snd_controls));
1749         wm8962_add_widgets(codec);
1750
1751         wm8962_init_beep(codec);
1752
1753         return 0;
1754
1755 err_enable:
1756         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1757 err_get:
1758         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1759 err:
1760         kfree(wm8962);
1761         return ret;
1762 }
1763
1764 static int wm8962_remove(struct snd_soc_codec *codec)
1765 {
1766         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1767         int i;
1768
1769         wm8962_free_beep(codec);
1770         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1771                 regulator_unregister_notifier(wm8962->supplies[i].consumer,
1772                                               &wm8962->disable_nb[i]);
1773         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1774
1775         return 0;
1776 }
1777
1778 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
1779         .probe =        wm8962_probe,
1780         .remove =       wm8962_remove,
1781         .resume =       wm8962_resume,
1782         .set_bias_level = wm8962_set_bias_level,
1783         .reg_cache_size = WM8962_MAX_REGISTER + 1,
1784         .reg_word_size = sizeof(u16),
1785         .reg_cache_default = wm8962_reg,
1786         .volatile_register = wm8962_volatile_register,
1787         .readable_register = wm8962_readable_register,
1788 };
1789
1790 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1791 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
1792                                       const struct i2c_device_id *id)
1793 {
1794         struct wm8962_priv *wm8962;
1795         int ret;
1796
1797         wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
1798         if (wm8962 == NULL)
1799                 return -ENOMEM;
1800
1801         i2c_set_clientdata(i2c, wm8962);
1802
1803         ret = snd_soc_register_codec(&i2c->dev,
1804                                      &soc_codec_dev_wm8962, &wm8962_dai, 1);
1805         if (ret < 0)
1806                 kfree(wm8962);
1807
1808         return ret;
1809 }
1810
1811 static __devexit int wm8962_i2c_remove(struct i2c_client *client)
1812 {
1813         snd_soc_unregister_codec(&client->dev);
1814         kfree(i2c_get_clientdata(client));
1815         return 0;
1816 }
1817
1818 static const struct i2c_device_id wm8962_i2c_id[] = {
1819         { "wm8962", 0 },
1820         { }
1821 };
1822 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
1823
1824 static struct i2c_driver wm8962_i2c_driver = {
1825         .driver = {
1826                 .name = "WM8962",
1827                 .owner = THIS_MODULE,
1828         },
1829         .probe =    wm8962_i2c_probe,
1830         .remove =   __devexit_p(wm8962_i2c_remove),
1831         .id_table = wm8962_i2c_id,
1832 };
1833 #endif
1834
1835 static int __init wm8962_modinit(void)
1836 {
1837         int ret;
1838 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1839         ret = i2c_add_driver(&wm8962_i2c_driver);
1840         if (ret != 0) {
1841                 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
1842                        ret);
1843         }
1844 #endif
1845         return 0;
1846 }
1847 module_init(wm8962_modinit);
1848
1849 static void __exit wm8962_exit(void)
1850 {
1851 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1852         i2c_del_driver(&wm8962_i2c_driver);
1853 #endif
1854 }
1855 module_exit(wm8962_exit);
1856
1857 MODULE_DESCRIPTION("ASoC WM8962 driver");
1858 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1859 MODULE_LICENSE("GPL");