2 * wm8961.c -- WM8961 ALSA SoC Audio driver
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Currently unimplemented features:
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
31 #define WM8961_MAX_REGISTER 0xFC
33 static u16 wm8961_reg_defaults[] = {
34 0x009F, /* R0 - Left Input volume */
35 0x009F, /* R1 - Right Input volume */
36 0x0000, /* R2 - LOUT1 volume */
37 0x0000, /* R3 - ROUT1 volume */
38 0x0020, /* R4 - Clocking1 */
39 0x0008, /* R5 - ADC & DAC Control 1 */
40 0x0000, /* R6 - ADC & DAC Control 2 */
41 0x000A, /* R7 - Audio Interface 0 */
42 0x01F4, /* R8 - Clocking2 */
43 0x0000, /* R9 - Audio Interface 1 */
44 0x00FF, /* R10 - Left DAC volume */
45 0x00FF, /* R11 - Right DAC volume */
48 0x0040, /* R14 - Audio Interface 2 */
49 0x0000, /* R15 - Software Reset */
51 0x007B, /* R17 - ALC1 */
52 0x0000, /* R18 - ALC2 */
53 0x0032, /* R19 - ALC3 */
54 0x0000, /* R20 - Noise Gate */
55 0x00C0, /* R21 - Left ADC volume */
56 0x00C0, /* R22 - Right ADC volume */
57 0x0120, /* R23 - Additional control(1) */
58 0x0000, /* R24 - Additional control(2) */
59 0x0000, /* R25 - Pwr Mgmt (1) */
60 0x0000, /* R26 - Pwr Mgmt (2) */
61 0x0000, /* R27 - Additional Control (3) */
62 0x0000, /* R28 - Anti-pop */
64 0x005F, /* R30 - Clocking 3 */
66 0x0000, /* R32 - ADCL signal path */
67 0x0000, /* R33 - ADCR signal path */
74 0x0000, /* R40 - LOUT2 volume */
75 0x0000, /* R41 - ROUT2 volume */
81 0x0000, /* R47 - Pwr Mgmt (3) */
82 0x0023, /* R48 - Additional Control (4) */
83 0x0000, /* R49 - Class D Control 1 */
85 0x0003, /* R51 - Class D Control 2 */
90 0x0106, /* R56 - Clocking 4 */
91 0x0000, /* R57 - DSP Sidetone 0 */
92 0x0000, /* R58 - DSP Sidetone 1 */
94 0x0000, /* R60 - DC Servo 0 */
95 0x0000, /* R61 - DC Servo 1 */
97 0x015E, /* R63 - DC Servo 3 */
99 0x0010, /* R65 - DC Servo 5 */
102 0x0003, /* R68 - Analogue PGA Bias */
103 0x0000, /* R69 - Analogue HP 0 */
105 0x01FB, /* R71 - Analogue HP 2 */
106 0x0000, /* R72 - Charge Pump 1 */
116 0x0000, /* R82 - Charge Pump B */
121 0x0000, /* R87 - Write Sequencer 1 */
122 0x0000, /* R88 - Write Sequencer 2 */
123 0x0000, /* R89 - Write Sequencer 3 */
124 0x0000, /* R90 - Write Sequencer 4 */
125 0x0000, /* R91 - Write Sequencer 5 */
126 0x0000, /* R92 - Write Sequencer 6 */
127 0x0000, /* R93 - Write Sequencer 7 */
286 0x0001, /* R252 - General test 1 */
290 enum snd_soc_control_type control_type;
294 static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
297 case WM8961_SOFTWARE_RESET:
298 case WM8961_WRITE_SEQUENCER_7:
299 case WM8961_DC_SERVO_1:
307 static int wm8961_reset(struct snd_soc_codec *codec)
309 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
313 * The headphone output supports special anti-pop sequences giving
314 * silent power up and power down.
316 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
317 struct snd_kcontrol *kcontrol, int event)
319 struct snd_soc_codec *codec = w->codec;
320 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
321 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
322 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
323 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
326 if (event & SND_SOC_DAPM_POST_PMU) {
327 /* Make sure the output is shorted */
328 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
329 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
331 /* Enable the charge pump */
332 cp_reg |= WM8961_CP_ENA;
333 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
337 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
338 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
340 /* Enable the amplifier */
341 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
342 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
344 /* Second stage enable */
345 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
346 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
348 /* Enable the DC servo & trigger startup */
350 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
351 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
352 dev_dbg(codec->dev, "Enabling DC servo\n");
354 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
357 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
358 } while (--timeout &&
359 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
360 WM8961_DCS_TRIG_STARTUP_HPL));
361 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
362 WM8961_DCS_TRIG_STARTUP_HPL))
363 dev_err(codec->dev, "DC servo timed out\n");
365 dev_dbg(codec->dev, "DC servo startup complete\n");
367 /* Enable the output stage */
368 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
369 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
371 /* Remove the short on the output stage */
372 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
373 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
376 if (event & SND_SOC_DAPM_PRE_PMD) {
377 /* Short the output */
378 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
379 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
381 /* Disable the output stage */
382 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
383 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
385 /* Disable DC offset cancellation */
386 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
387 WM8961_DCS_ENA_CHAN_HPL);
388 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
391 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
392 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
393 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
395 /* Disable the PGA */
396 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
397 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
399 /* Disable the charge pump */
400 dev_dbg(codec->dev, "Disabling charge pump\n");
401 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
402 cp_reg & ~WM8961_CP_ENA);
408 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
409 struct snd_kcontrol *kcontrol, int event)
411 struct snd_soc_codec *codec = w->codec;
412 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
413 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
415 if (event & SND_SOC_DAPM_POST_PMU) {
417 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
418 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
420 /* Enable the amplifier */
421 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
422 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
425 if (event & SND_SOC_DAPM_PRE_PMD) {
426 /* Enable the amplifier */
427 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
428 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
431 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
432 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
438 static const char *adc_hpf_text[] = {
439 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
442 static const struct soc_enum adc_hpf =
443 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
445 static const char *dac_deemph_text[] = {
446 "None", "32kHz", "44.1kHz", "48kHz",
449 static const struct soc_enum dac_deemph =
450 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
452 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
453 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
454 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
455 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
456 static unsigned int boost_tlv[] = {
457 TLV_DB_RANGE_HEAD(4),
458 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
459 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
460 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
461 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
463 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
465 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
466 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
468 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
469 6, 3, 7, 0, hp_sec_tlv),
470 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
473 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
475 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
477 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
479 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
480 SOC_ENUM("DAC Deemphasis", dac_deemph),
481 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
483 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
484 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
486 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
487 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
489 SOC_DOUBLE_R_TLV("Capture Volume",
490 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
492 SOC_DOUBLE_R_TLV("Capture Boost Volume",
493 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
495 SOC_DOUBLE_R_TLV("Capture PGA Volume",
496 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
498 SOC_DOUBLE_R("Capture PGA ZC Switch",
499 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
501 SOC_DOUBLE_R("Capture PGA Switch",
502 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
506 static const char *sidetone_text[] = {
507 "None", "Left", "Right"
510 static const struct soc_enum dacl_sidetone =
511 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
513 static const struct soc_enum dacr_sidetone =
514 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
516 static const struct snd_kcontrol_new dacl_mux =
517 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
519 static const struct snd_kcontrol_new dacr_mux =
520 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
522 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
523 SND_SOC_DAPM_INPUT("LINPUT"),
524 SND_SOC_DAPM_INPUT("RINPUT"),
526 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
528 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
529 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
531 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
532 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
534 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
536 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
537 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
539 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
540 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
542 /* Handle as a mono path for DCS */
543 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
544 4, 0, NULL, 0, wm8961_hp_event,
545 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
546 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
547 4, 0, NULL, 0, wm8961_spk_event,
548 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
550 SND_SOC_DAPM_OUTPUT("HP_L"),
551 SND_SOC_DAPM_OUTPUT("HP_R"),
552 SND_SOC_DAPM_OUTPUT("SPK_LN"),
553 SND_SOC_DAPM_OUTPUT("SPK_LP"),
554 SND_SOC_DAPM_OUTPUT("SPK_RN"),
555 SND_SOC_DAPM_OUTPUT("SPK_RP"),
559 static const struct snd_soc_dapm_route audio_paths[] = {
560 { "DACL", NULL, "CLK_DSP" },
561 { "DACL", NULL, "DACL Sidetone" },
562 { "DACR", NULL, "CLK_DSP" },
563 { "DACR", NULL, "DACR Sidetone" },
565 { "DACL Sidetone", "Left", "ADCL" },
566 { "DACL Sidetone", "Right", "ADCR" },
568 { "DACR Sidetone", "Left", "ADCL" },
569 { "DACR Sidetone", "Right", "ADCR" },
571 { "HP_L", NULL, "Headphone Output" },
572 { "HP_R", NULL, "Headphone Output" },
573 { "Headphone Output", NULL, "DACL" },
574 { "Headphone Output", NULL, "DACR" },
576 { "SPK_LN", NULL, "Speaker Output" },
577 { "SPK_LP", NULL, "Speaker Output" },
578 { "SPK_RN", NULL, "Speaker Output" },
579 { "SPK_RP", NULL, "Speaker Output" },
581 { "Speaker Output", NULL, "DACL" },
582 { "Speaker Output", NULL, "DACR" },
584 { "ADCL", NULL, "Left Input" },
585 { "ADCL", NULL, "CLK_DSP" },
586 { "ADCR", NULL, "Right Input" },
587 { "ADCR", NULL, "CLK_DSP" },
589 { "Left Input", NULL, "LINPUT" },
590 { "Right Input", NULL, "RINPUT" },
594 /* Values for CLK_SYS_RATE */
598 } wm8961_clk_sys_ratio[] = {
611 /* Values for SAMPLE_RATE */
627 static int wm8961_hw_params(struct snd_pcm_substream *substream,
628 struct snd_pcm_hw_params *params,
629 struct snd_soc_dai *dai)
631 struct snd_soc_codec *codec = dai->codec;
632 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
633 int i, best, target, fs;
636 fs = params_rate(params);
638 if (!wm8961->sysclk) {
639 dev_err(codec->dev, "MCLK has not been specified\n");
643 /* Find the closest sample rate for the filters */
645 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
646 if (abs(wm8961_srate[i].rate - fs) <
647 abs(wm8961_srate[best].rate - fs))
650 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
651 reg &= ~WM8961_SAMPLE_RATE_MASK;
652 reg |= wm8961_srate[best].val;
653 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
654 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
655 wm8961_srate[best].rate, fs);
657 /* Select a CLK_SYS/fs ratio equal to or higher than required */
658 target = wm8961->sysclk / fs;
660 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
662 "SYSCLK must be at least 64*fs for DAC\n");
665 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
667 "SYSCLK must be at least 256*fs for ADC\n");
671 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
672 if (wm8961_clk_sys_ratio[i].ratio >= target)
675 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
676 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
679 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
680 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
681 wm8961->sysclk / fs);
683 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
684 reg &= ~WM8961_CLK_SYS_RATE_MASK;
685 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
686 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
688 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
689 reg &= ~WM8961_WL_MASK;
690 switch (params_format(params)) {
691 case SNDRV_PCM_FORMAT_S16_LE:
693 case SNDRV_PCM_FORMAT_S20_3LE:
694 reg |= 1 << WM8961_WL_SHIFT;
696 case SNDRV_PCM_FORMAT_S24_LE:
697 reg |= 2 << WM8961_WL_SHIFT;
699 case SNDRV_PCM_FORMAT_S32_LE:
700 reg |= 3 << WM8961_WL_SHIFT;
705 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
707 /* Sloping stop-band filter is recommended for <= 24kHz */
708 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
710 reg |= WM8961_DACSLOPE;
712 reg &= ~WM8961_DACSLOPE;
713 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
718 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
722 struct snd_soc_codec *codec = dai->codec;
723 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
724 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
726 if (freq > 33000000) {
727 dev_err(codec->dev, "MCLK must be <33MHz\n");
731 if (freq > 16500000) {
732 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
733 reg |= WM8961_MCLKDIV;
736 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
737 reg &= ~WM8961_MCLKDIV;
740 snd_soc_write(codec, WM8961_CLOCKING1, reg);
742 wm8961->sysclk = freq;
747 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
749 struct snd_soc_codec *codec = dai->codec;
750 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
752 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
753 WM8961_MS | WM8961_FORMAT_MASK);
755 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
756 case SND_SOC_DAIFMT_CBM_CFM:
759 case SND_SOC_DAIFMT_CBS_CFS:
765 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
766 case SND_SOC_DAIFMT_RIGHT_J:
769 case SND_SOC_DAIFMT_LEFT_J:
773 case SND_SOC_DAIFMT_I2S:
777 case SND_SOC_DAIFMT_DSP_B:
779 case SND_SOC_DAIFMT_DSP_A:
781 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
782 case SND_SOC_DAIFMT_NB_NF:
783 case SND_SOC_DAIFMT_IB_NF:
794 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
795 case SND_SOC_DAIFMT_NB_NF:
797 case SND_SOC_DAIFMT_NB_IF:
800 case SND_SOC_DAIFMT_IB_NF:
801 aif |= WM8961_BCLKINV;
803 case SND_SOC_DAIFMT_IB_IF:
804 aif |= WM8961_BCLKINV | WM8961_LRP;
810 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
813 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
815 struct snd_soc_codec *codec = dai->codec;
816 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
823 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
826 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
828 struct snd_soc_codec *codec = dai->codec;
829 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
834 reg &= ~WM8961_DACMU;
838 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
841 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
843 struct snd_soc_codec *codec = dai->codec;
848 reg = snd_soc_read(codec, WM8961_CLOCKING2);
849 reg &= ~WM8961_BCLKDIV_MASK;
851 snd_soc_write(codec, WM8961_CLOCKING2, reg);
855 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
856 reg &= ~WM8961_LRCLK_RATE_MASK;
858 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
868 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
869 enum snd_soc_bias_level level)
873 /* This is all slightly unusual since we have no bypass paths
874 * and the output amplifier structure means we can just slam
875 * the biases straight up rather than having to ramp them
879 case SND_SOC_BIAS_ON:
882 case SND_SOC_BIAS_PREPARE:
883 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
884 /* Enable bias generation */
885 reg = snd_soc_read(codec, WM8961_ANTI_POP);
886 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
887 snd_soc_write(codec, WM8961_ANTI_POP, reg);
889 /* VMID=2*50k, VREF */
890 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
891 reg &= ~WM8961_VMIDSEL_MASK;
892 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
893 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
897 case SND_SOC_BIAS_STANDBY:
898 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
900 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
902 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
904 /* Bias generation off */
905 reg = snd_soc_read(codec, WM8961_ANTI_POP);
906 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
907 snd_soc_write(codec, WM8961_ANTI_POP, reg);
910 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
911 reg &= ~WM8961_VMIDSEL_MASK;
912 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
916 case SND_SOC_BIAS_OFF:
920 codec->dapm.bias_level = level;
926 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
928 #define WM8961_FORMATS \
929 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
930 SNDRV_PCM_FMTBIT_S24_LE)
932 static struct snd_soc_dai_ops wm8961_dai_ops = {
933 .hw_params = wm8961_hw_params,
934 .set_sysclk = wm8961_set_sysclk,
935 .set_fmt = wm8961_set_fmt,
936 .digital_mute = wm8961_digital_mute,
937 .set_tristate = wm8961_set_tristate,
938 .set_clkdiv = wm8961_set_clkdiv,
941 static struct snd_soc_dai_driver wm8961_dai = {
942 .name = "wm8961-hifi",
944 .stream_name = "HiFi Playback",
947 .rates = WM8961_RATES,
948 .formats = WM8961_FORMATS,},
950 .stream_name = "HiFi Capture",
953 .rates = WM8961_RATES,
954 .formats = WM8961_FORMATS,},
955 .ops = &wm8961_dai_ops,
958 static int wm8961_probe(struct snd_soc_codec *codec)
960 struct snd_soc_dapm_context *dapm = &codec->dapm;
964 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
966 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
970 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
972 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
976 /* This isn't volatile - readback doesn't correspond to write */
977 codec->cache_bypass = 1;
978 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
979 codec->cache_bypass = 0;
980 dev_info(codec->dev, "WM8961 family %d revision %c\n",
981 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
982 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
985 ret = wm8961_reset(codec);
987 dev_err(codec->dev, "Failed to issue reset\n");
992 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
993 reg |= WM8961_CP_DYN_PWR_MASK;
994 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
996 /* Latch volume update bits (right channel only, we always
997 * write both out) and default ZC on. */
998 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
999 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1000 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1001 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1002 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1003 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1004 reg | WM8961_SPKRZC | WM8961_SPKVU);
1005 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1007 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1008 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1009 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1010 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1012 /* Use soft mute by default */
1013 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1014 reg |= WM8961_DACSMM;
1015 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1017 /* Use automatic clocking mode by default; for now this is all
1020 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1021 reg &= ~WM8961_MANUAL_MODE;
1022 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1024 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1026 snd_soc_add_controls(codec, wm8961_snd_controls,
1027 ARRAY_SIZE(wm8961_snd_controls));
1028 snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
1029 ARRAY_SIZE(wm8961_dapm_widgets));
1030 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
1035 static int wm8961_remove(struct snd_soc_codec *codec)
1037 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1042 static int wm8961_suspend(struct snd_soc_codec *codec, pm_message_t state)
1044 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1049 static int wm8961_resume(struct snd_soc_codec *codec)
1051 u16 *reg_cache = codec->reg_cache;
1054 for (i = 0; i < codec->driver->reg_cache_size; i++) {
1055 if (reg_cache[i] == wm8961_reg_defaults[i])
1058 if (i == WM8961_SOFTWARE_RESET)
1061 snd_soc_write(codec, i, reg_cache[i]);
1064 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1069 #define wm8961_suspend NULL
1070 #define wm8961_resume NULL
1073 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1074 .probe = wm8961_probe,
1075 .remove = wm8961_remove,
1076 .suspend = wm8961_suspend,
1077 .resume = wm8961_resume,
1078 .set_bias_level = wm8961_set_bias_level,
1079 .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
1080 .reg_word_size = sizeof(u16),
1081 .reg_cache_default = wm8961_reg_defaults,
1082 .volatile_register = wm8961_volatile_register,
1085 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1086 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1087 const struct i2c_device_id *id)
1089 struct wm8961_priv *wm8961;
1092 wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1096 i2c_set_clientdata(i2c, wm8961);
1098 ret = snd_soc_register_codec(&i2c->dev,
1099 &soc_codec_dev_wm8961, &wm8961_dai, 1);
1105 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1107 snd_soc_unregister_codec(&client->dev);
1108 kfree(i2c_get_clientdata(client));
1112 static const struct i2c_device_id wm8961_i2c_id[] = {
1116 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1118 static struct i2c_driver wm8961_i2c_driver = {
1120 .name = "wm8961-codec",
1121 .owner = THIS_MODULE,
1123 .probe = wm8961_i2c_probe,
1124 .remove = __devexit_p(wm8961_i2c_remove),
1125 .id_table = wm8961_i2c_id,
1129 static int __init wm8961_modinit(void)
1132 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1133 ret = i2c_add_driver(&wm8961_i2c_driver);
1135 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
1141 module_init(wm8961_modinit);
1143 static void __exit wm8961_exit(void)
1145 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1146 i2c_del_driver(&wm8961_i2c_driver);
1149 module_exit(wm8961_exit);
1151 MODULE_DESCRIPTION("ASoC WM8961 driver");
1152 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1153 MODULE_LICENSE("GPL");