sound/soc/codecs/wm8915.c

   1 /*
   2  * wm8915.c - WM8915 audio codec interface
   3  *
   4  * Copyright 2011 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/delay.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25 #include <linux/workqueue.h>
  26 #include <sound/core.h>
  27 #include <sound/jack.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/initval.h>
  32 #include <sound/tlv.h>
  33 #include <trace/events/asoc.h>
  34
  35 #include <sound/wm8915.h>
  36 #include "wm8915.h"
  37
  38 #define WM8915_AIFS 2
  39
  40 #define HPOUT1L 1
  41 #define HPOUT1R 2
  42 #define HPOUT2L 4
  43 #define HPOUT2R 8
  44
  45 #define WM8915_NUM_SUPPLIES 6
  46 static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
  47         "DCVDD",
  48         "DBVDD",
  49         "AVDD1",
  50         "AVDD2",
  51         "CPVDD",
  52         "MICVDD",
  53 };
  54
  55 struct wm8915_priv {
  56         struct snd_soc_codec *codec;
  57
  58         int ldo1ena;
  59
  60         int sysclk;
  61
  62         int fll_src;
  63         int fll_fref;
  64         int fll_fout;
  65
  66         struct completion fll_lock;
  67
  68         u16 dcs_pending;
  69         struct completion dcs_done;
  70
  71         u16 hpout_ena;
  72         u16 hpout_pending;
  73
  74         struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
  75         struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
  76
  77         struct wm8915_pdata pdata;
  78
  79         int rx_rate[WM8915_AIFS];
  80
  81         /* Platform dependant ReTune mobile configuration */
  82         int num_retune_mobile_texts;
  83         const char **retune_mobile_texts;
  84         int retune_mobile_cfg[2];
  85         struct soc_enum retune_mobile_enum;
  86
  87         struct snd_soc_jack *jack;
  88         bool detecting;
  89         bool jack_mic;
  90         wm8915_polarity_fn polarity_cb;
  91
  92 #ifdef CONFIG_GPIOLIB
  93         struct gpio_chip gpio_chip;
  94 #endif
  95 };
  96
  97 /* We can't use the same notifier block for more than one supply and
  98  * there's no way I can see to get from a callback to the caller
  99  * except container_of().
 100  */
 101 #define WM8915_REGULATOR_EVENT(n) \
 102 static int wm8915_regulator_event_##n(struct notifier_block *nb, \
 103                                     unsigned long event, void *data)    \
 104 { \
 105         struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
 106                                                   disable_nb[n]); \
 107         if (event & REGULATOR_EVENT_DISABLE) { \
 108                 wm8915->codec->cache_sync = 1; \
 109         } \
 110         return 0; \
 111 }
 112
 113 WM8915_REGULATOR_EVENT(0)
 114 WM8915_REGULATOR_EVENT(1)
 115 WM8915_REGULATOR_EVENT(2)
 116 WM8915_REGULATOR_EVENT(3)
 117 WM8915_REGULATOR_EVENT(4)
 118 WM8915_REGULATOR_EVENT(5)
 119
 120 static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
 121         [WM8915_SOFTWARE_RESET] = 0x8915,
 122         [WM8915_POWER_MANAGEMENT_7] = 0x10,
 123         [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
 124         [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
 125         [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
 126         [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
 127         [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
 128         [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
 129         [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
 130         [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
 131         [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
 132         [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
 133         [WM8915_MICBIAS_1] = 0x39,
 134         [WM8915_MICBIAS_2] = 0x39,
 135         [WM8915_LDO_1] = 0x3,
 136         [WM8915_LDO_2] = 0x13,
 137         [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
 138         [WM8915_HEADPHONE_DETECT_1] = 0x20,
 139         [WM8915_MIC_DETECT_1] = 0x7600,
 140         [WM8915_MIC_DETECT_2] = 0xbf,
 141         [WM8915_CHARGE_PUMP_1] = 0x1f25,
 142         [WM8915_CHARGE_PUMP_2] = 0xab19,
 143         [WM8915_DC_SERVO_5] = 0x2a2a,
 144         [WM8915_CONTROL_INTERFACE_1] = 0x8004,
 145         [WM8915_CLOCKING_1] = 0x10,
 146         [WM8915_AIF_RATE] = 0x83,
 147         [WM8915_FLL_CONTROL_4] = 0x5dc0,
 148         [WM8915_FLL_CONTROL_5] = 0xc84,
 149         [WM8915_FLL_EFS_2] = 0x2,
 150         [WM8915_AIF1_TX_LRCLK_1] = 0x80,
 151         [WM8915_AIF1_TX_LRCLK_2] = 0x8,
 152         [WM8915_AIF1_RX_LRCLK_1] = 0x80,
 153         [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
 154         [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
 155         [WM8915_AIF1TX_TEST] = 0x7,
 156         [WM8915_AIF2_TX_LRCLK_1] = 0x80,
 157         [WM8915_AIF2_TX_LRCLK_2] = 0x8,
 158         [WM8915_AIF2_RX_LRCLK_1] = 0x80,
 159         [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
 160         [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
 161         [WM8915_AIF2TX_TEST] = 0x1,
 162         [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
 163         [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
 164         [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
 165         [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
 166         [WM8915_DSP1_TX_FILTERS] = 0x2000,
 167         [WM8915_DSP1_RX_FILTERS_1] = 0x200,
 168         [WM8915_DSP1_RX_FILTERS_2] = 0x10,
 169         [WM8915_DSP1_DRC_1] = 0x98,
 170         [WM8915_DSP1_DRC_2] = 0x845,
 171         [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
 172         [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
 173         [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
 174         [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
 175         [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
 176         [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
 177         [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
 178         [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
 179         [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
 180         [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
 181         [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
 182         [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
 183         [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
 184         [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
 185         [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
 186         [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
 187         [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
 188         [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
 189         [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
 190         [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
 191         [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
 192         [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
 193         [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
 194         [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
 195         [WM8915_DSP2_TX_FILTERS] = 0x2000,
 196         [WM8915_DSP2_RX_FILTERS_1] = 0x200,
 197         [WM8915_DSP2_RX_FILTERS_2] = 0x10,
 198         [WM8915_DSP2_DRC_1] = 0x98,
 199         [WM8915_DSP2_DRC_2] = 0x845,
 200         [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
 201         [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
 202         [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
 203         [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
 204         [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
 205         [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
 206         [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
 207         [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
 208         [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
 209         [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
 210         [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
 211         [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
 212         [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
 213         [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
 214         [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
 215         [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
 216         [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
 217         [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
 218         [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
 219         [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
 220         [WM8915_OVERSAMPLING] = 0xd,
 221         [WM8915_SIDETONE] = 0x1040,
 222         [WM8915_GPIO_1] = 0xa101,
 223         [WM8915_GPIO_2] = 0xa101,
 224         [WM8915_GPIO_3] = 0xa101,
 225         [WM8915_GPIO_4] = 0xa101,
 226         [WM8915_GPIO_5] = 0xa101,
 227         [WM8915_PULL_CONTROL_2] = 0x140,
 228         [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
 229         [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
 230         [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
 231         [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
 232         [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
 233         [WM8915_WRITE_SEQUENCER_0] = 0x1,
 234         [WM8915_WRITE_SEQUENCER_1] = 0x1,
 235         [WM8915_WRITE_SEQUENCER_3] = 0x6,
 236         [WM8915_WRITE_SEQUENCER_4] = 0x40,
 237         [WM8915_WRITE_SEQUENCER_5] = 0x1,
 238         [WM8915_WRITE_SEQUENCER_6] = 0xf,
 239         [WM8915_WRITE_SEQUENCER_7] = 0x6,
 240         [WM8915_WRITE_SEQUENCER_8] = 0x1,
 241         [WM8915_WRITE_SEQUENCER_9] = 0x3,
 242         [WM8915_WRITE_SEQUENCER_10] = 0x104,
 243         [WM8915_WRITE_SEQUENCER_12] = 0x60,
 244         [WM8915_WRITE_SEQUENCER_13] = 0x11,
 245         [WM8915_WRITE_SEQUENCER_14] = 0x401,
 246         [WM8915_WRITE_SEQUENCER_16] = 0x50,
 247         [WM8915_WRITE_SEQUENCER_17] = 0x3,
 248         [WM8915_WRITE_SEQUENCER_18] = 0x100,
 249         [WM8915_WRITE_SEQUENCER_20] = 0x51,
 250         [WM8915_WRITE_SEQUENCER_21] = 0x3,
 251         [WM8915_WRITE_SEQUENCER_22] = 0x104,
 252         [WM8915_WRITE_SEQUENCER_23] = 0xa,
 253         [WM8915_WRITE_SEQUENCER_24] = 0x60,
 254         [WM8915_WRITE_SEQUENCER_25] = 0x3b,
 255         [WM8915_WRITE_SEQUENCER_26] = 0x502,
 256         [WM8915_WRITE_SEQUENCER_27] = 0x100,
 257         [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
 258         [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
 259         [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
 260         [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
 261         [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
 262         [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
 263         [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
 264         [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
 265         [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
 266         [WM8915_WRITE_SEQUENCER_64] = 0x1,
 267         [WM8915_WRITE_SEQUENCER_65] = 0x1,
 268         [WM8915_WRITE_SEQUENCER_67] = 0x6,
 269         [WM8915_WRITE_SEQUENCER_68] = 0x40,
 270         [WM8915_WRITE_SEQUENCER_69] = 0x1,
 271         [WM8915_WRITE_SEQUENCER_70] = 0xf,
 272         [WM8915_WRITE_SEQUENCER_71] = 0x6,
 273         [WM8915_WRITE_SEQUENCER_72] = 0x1,
 274         [WM8915_WRITE_SEQUENCER_73] = 0x3,
 275         [WM8915_WRITE_SEQUENCER_74] = 0x104,
 276         [WM8915_WRITE_SEQUENCER_76] = 0x60,
 277         [WM8915_WRITE_SEQUENCER_77] = 0x11,
 278         [WM8915_WRITE_SEQUENCER_78] = 0x401,
 279         [WM8915_WRITE_SEQUENCER_80] = 0x50,
 280         [WM8915_WRITE_SEQUENCER_81] = 0x3,
 281         [WM8915_WRITE_SEQUENCER_82] = 0x100,
 282         [WM8915_WRITE_SEQUENCER_84] = 0x60,
 283         [WM8915_WRITE_SEQUENCER_85] = 0x3b,
 284         [WM8915_WRITE_SEQUENCER_86] = 0x502,
 285         [WM8915_WRITE_SEQUENCER_87] = 0x100,
 286         [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
 287         [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
 288         [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
 289         [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
 290         [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
 291         [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
 292         [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
 293         [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
 294         [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
 295         [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
 296         [WM8915_WRITE_SEQUENCER_128] = 0x1,
 297         [WM8915_WRITE_SEQUENCER_129] = 0x1,
 298         [WM8915_WRITE_SEQUENCER_131] = 0x6,
 299         [WM8915_WRITE_SEQUENCER_132] = 0x40,
 300         [WM8915_WRITE_SEQUENCER_133] = 0x1,
 301         [WM8915_WRITE_SEQUENCER_134] = 0xf,
 302         [WM8915_WRITE_SEQUENCER_135] = 0x6,
 303         [WM8915_WRITE_SEQUENCER_136] = 0x1,
 304         [WM8915_WRITE_SEQUENCER_137] = 0x3,
 305         [WM8915_WRITE_SEQUENCER_138] = 0x106,
 306         [WM8915_WRITE_SEQUENCER_140] = 0x61,
 307         [WM8915_WRITE_SEQUENCER_141] = 0x11,
 308         [WM8915_WRITE_SEQUENCER_142] = 0x401,
 309         [WM8915_WRITE_SEQUENCER_144] = 0x50,
 310         [WM8915_WRITE_SEQUENCER_145] = 0x3,
 311         [WM8915_WRITE_SEQUENCER_146] = 0x102,
 312         [WM8915_WRITE_SEQUENCER_148] = 0x51,
 313         [WM8915_WRITE_SEQUENCER_149] = 0x3,
 314         [WM8915_WRITE_SEQUENCER_150] = 0x106,
 315         [WM8915_WRITE_SEQUENCER_151] = 0xa,
 316         [WM8915_WRITE_SEQUENCER_152] = 0x61,
 317         [WM8915_WRITE_SEQUENCER_153] = 0x3b,
 318         [WM8915_WRITE_SEQUENCER_154] = 0x502,
 319         [WM8915_WRITE_SEQUENCER_155] = 0x100,
 320         [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
 321         [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
 322         [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
 323         [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
 324         [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
 325         [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
 326         [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
 327         [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
 328         [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
 329         [WM8915_WRITE_SEQUENCER_192] = 0x1,
 330         [WM8915_WRITE_SEQUENCER_193] = 0x1,
 331         [WM8915_WRITE_SEQUENCER_195] = 0x6,
 332         [WM8915_WRITE_SEQUENCER_196] = 0x40,
 333         [WM8915_WRITE_SEQUENCER_197] = 0x1,
 334         [WM8915_WRITE_SEQUENCER_198] = 0xf,
 335         [WM8915_WRITE_SEQUENCER_199] = 0x6,
 336         [WM8915_WRITE_SEQUENCER_200] = 0x1,
 337         [WM8915_WRITE_SEQUENCER_201] = 0x3,
 338         [WM8915_WRITE_SEQUENCER_202] = 0x106,
 339         [WM8915_WRITE_SEQUENCER_204] = 0x61,
 340         [WM8915_WRITE_SEQUENCER_205] = 0x11,
 341         [WM8915_WRITE_SEQUENCER_206] = 0x401,
 342         [WM8915_WRITE_SEQUENCER_208] = 0x50,
 343         [WM8915_WRITE_SEQUENCER_209] = 0x3,
 344         [WM8915_WRITE_SEQUENCER_210] = 0x102,
 345         [WM8915_WRITE_SEQUENCER_212] = 0x61,
 346         [WM8915_WRITE_SEQUENCER_213] = 0x3b,
 347         [WM8915_WRITE_SEQUENCER_214] = 0x502,
 348         [WM8915_WRITE_SEQUENCER_215] = 0x100,
 349         [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
 350         [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
 351         [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
 352         [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
 353         [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
 354         [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
 355         [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
 356         [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
 357         [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
 358         [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
 359         [WM8915_WRITE_SEQUENCER_256] = 0x60,
 360         [WM8915_WRITE_SEQUENCER_258] = 0x601,
 361         [WM8915_WRITE_SEQUENCER_260] = 0x50,
 362         [WM8915_WRITE_SEQUENCER_262] = 0x100,
 363         [WM8915_WRITE_SEQUENCER_264] = 0x1,
 364         [WM8915_WRITE_SEQUENCER_266] = 0x104,
 365         [WM8915_WRITE_SEQUENCER_267] = 0x100,
 366         [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
 367         [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
 368         [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
 369         [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
 370         [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
 371         [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
 372         [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
 373         [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
 374         [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
 375         [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
 376         [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
 377         [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
 378         [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
 379         [WM8915_WRITE_SEQUENCER_320] = 0x61,
 380         [WM8915_WRITE_SEQUENCER_322] = 0x601,
 381         [WM8915_WRITE_SEQUENCER_324] = 0x50,
 382         [WM8915_WRITE_SEQUENCER_326] = 0x102,
 383         [WM8915_WRITE_SEQUENCER_328] = 0x1,
 384         [WM8915_WRITE_SEQUENCER_330] = 0x106,
 385         [WM8915_WRITE_SEQUENCER_331] = 0x100,
 386         [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
 387         [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
 388         [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
 389         [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
 390         [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
 391         [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
 392         [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
 393         [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
 394         [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
 395         [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
 396         [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
 397         [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
 398         [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
 399         [WM8915_WRITE_SEQUENCER_384] = 0x60,
 400         [WM8915_WRITE_SEQUENCER_386] = 0x601,
 401         [WM8915_WRITE_SEQUENCER_388] = 0x61,
 402         [WM8915_WRITE_SEQUENCER_390] = 0x601,
 403         [WM8915_WRITE_SEQUENCER_392] = 0x50,
 404         [WM8915_WRITE_SEQUENCER_394] = 0x300,
 405         [WM8915_WRITE_SEQUENCER_396] = 0x1,
 406         [WM8915_WRITE_SEQUENCER_398] = 0x304,
 407         [WM8915_WRITE_SEQUENCER_400] = 0x40,
 408         [WM8915_WRITE_SEQUENCER_402] = 0xf,
 409         [WM8915_WRITE_SEQUENCER_404] = 0x1,
 410         [WM8915_WRITE_SEQUENCER_407] = 0x100,
 411 };
 412
 413 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
 414 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
 415 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 416 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
 417 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
 418 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
 419 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 420
 421 static const char *sidetone_hpf_text[] = {
 422         "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
 423 };
 424
 425 static const struct soc_enum sidetone_hpf =
 426         SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
 427
 428 static const char *hpf_mode_text[] = {
 429         "HiFi", "Custom", "Voice"
 430 };
 431
 432 static const struct soc_enum dsp1tx_hpf_mode =
 433         SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
 434
 435 static const struct soc_enum dsp2tx_hpf_mode =
 436         SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
 437
 438 static const char *hpf_cutoff_text[] = {
 439         "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 440 };
 441
 442 static const struct soc_enum dsp1tx_hpf_cutoff =
 443         SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
 444
 445 static const struct soc_enum dsp2tx_hpf_cutoff =
 446         SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
 447
 448 static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
 449 {
 450         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 451         struct wm8915_pdata *pdata = &wm8915->pdata;
 452         int base, best, best_val, save, i, cfg, iface;
 453
 454         if (!wm8915->num_retune_mobile_texts)
 455                 return;
 456
 457         switch (block) {
 458         case 0:
 459                 base = WM8915_DSP1_RX_EQ_GAINS_1;
 460                 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
 461                     WM8915_DSP1RX_SRC)
 462                         iface = 1;
 463                 else
 464                         iface = 0;
 465                 break;
 466         case 1:
 467                 base = WM8915_DSP1_RX_EQ_GAINS_2;
 468                 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
 469                     WM8915_DSP2RX_SRC)
 470                         iface = 1;
 471                 else
 472                         iface = 0;
 473                 break;
 474         default:
 475                 return;
 476         }
 477
 478         /* Find the version of the currently selected configuration
 479          * with the nearest sample rate. */
 480         cfg = wm8915->retune_mobile_cfg[block];
 481         best = 0;
 482         best_val = INT_MAX;
 483         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 484                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 485                            wm8915->retune_mobile_texts[cfg]) == 0 &&
 486                     abs(pdata->retune_mobile_cfgs[i].rate
 487                         - wm8915->rx_rate[iface]) < best_val) {
 488                         best = i;
 489                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 490                                        - wm8915->rx_rate[iface]);
 491                 }
 492         }
 493
 494         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 495                 block,
 496                 pdata->retune_mobile_cfgs[best].name,
 497                 pdata->retune_mobile_cfgs[best].rate,
 498                 wm8915->rx_rate[iface]);
 499
 500         /* The EQ will be disabled while reconfiguring it, remember the
 501          * current configuration.
 502          */
 503         save = snd_soc_read(codec, base);
 504         save &= WM8915_DSP1RX_EQ_ENA;
 505
 506         for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
 507                 snd_soc_update_bits(codec, base + i, 0xffff,
 508                                     pdata->retune_mobile_cfgs[best].regs[i]);
 509
 510         snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
 511 }
 512
 513 /* Icky as hell but saves code duplication */
 514 static int wm8915_get_retune_mobile_block(const char *name)
 515 {
 516         if (strcmp(name, "DSP1 EQ Mode") == 0)
 517                 return 0;
 518         if (strcmp(name, "DSP2 EQ Mode") == 0)
 519                 return 1;
 520         return -EINVAL;
 521 }
 522
 523 static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 524                                          struct snd_ctl_elem_value *ucontrol)
 525 {
 526         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 527         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 528         struct wm8915_pdata *pdata = &wm8915->pdata;
 529         int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
 530         int value = ucontrol->value.integer.value[0];
 531
 532         if (block < 0)
 533                 return block;
 534
 535         if (value >= pdata->num_retune_mobile_cfgs)
 536                 return -EINVAL;
 537
 538         wm8915->retune_mobile_cfg[block] = value;
 539
 540         wm8915_set_retune_mobile(codec, block);
 541
 542         return 0;
 543 }
 544
 545 static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 546                                          struct snd_ctl_elem_value *ucontrol)
 547 {
 548         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 549         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 550         int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
 551
 552         ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
 553
 554         return 0;
 555 }
 556
 557 static const struct snd_kcontrol_new wm8915_snd_controls[] = {
 558 SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
 559                  WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
 560 SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
 561              WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
 562
 563 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
 564                0, 5, 24, 0, sidetone_tlv),
 565 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
 566                0, 5, 24, 0, sidetone_tlv),
 567 SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
 568 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
 569 SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
 570
 571 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
 572                  WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 573 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
 574                  WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 575
 576 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
 577            13, 1, 0),
 578 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
 579 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
 580 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
 581
 582 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
 583            13, 1, 0),
 584 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
 585 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
 586 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
 587
 588 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
 589                  WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 590 SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
 591
 592 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
 593                  WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 594 SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
 595
 596 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
 597                  WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 598 SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
 599              WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
 600
 601 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
 602                  WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 603 SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
 604              WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
 605
 606 SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
 607 SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
 608 SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
 609 SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
 610
 611 SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
 612 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
 613
 614 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
 615                8, 0, out_digital_tlv),
 616 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
 617                8, 0, out_digital_tlv),
 618
 619 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
 620                  WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 621 SOC_DOUBLE_R("Output 1 ZC Switch",  WM8915_OUTPUT1_LEFT_VOLUME,
 622              WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
 623
 624 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
 625                  WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 626 SOC_DOUBLE_R("Output 2 ZC Switch",  WM8915_OUTPUT2_LEFT_VOLUME,
 627              WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
 628
 629 SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
 630                spk_tlv),
 631 SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
 632              WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
 633 SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
 634              WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
 635
 636 SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
 637 SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
 638 };
 639
 640 static const struct snd_kcontrol_new wm8915_eq_controls[] = {
 641 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
 642                eq_tlv),
 643 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
 644                eq_tlv),
 645 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
 646                eq_tlv),
 647 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
 650                eq_tlv),
 651
 652 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
 653                eq_tlv),
 654 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
 655                eq_tlv),
 656 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
 657                eq_tlv),
 658 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
 659                eq_tlv),
 660 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
 661                eq_tlv),
 662 };
 663
 664 static int cp_event(struct snd_soc_dapm_widget *w,
 665                     struct snd_kcontrol *kcontrol, int event)
 666 {
 667         switch (event) {
 668         case SND_SOC_DAPM_POST_PMU:
 669                 msleep(5);
 670                 break;
 671         default:
 672                 BUG();
 673                 return -EINVAL;
 674         }
 675
 676         return 0;
 677 }
 678
 679 static int rmv_short_event(struct snd_soc_dapm_widget *w,
 680                            struct snd_kcontrol *kcontrol, int event)
 681 {
 682         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
 683
 684         /* Record which outputs we enabled */
 685         switch (event) {
 686         case SND_SOC_DAPM_PRE_PMD:
 687                 wm8915->hpout_pending &= ~w->shift;
 688                 break;
 689         case SND_SOC_DAPM_PRE_PMU:
 690                 wm8915->hpout_pending |= w->shift;
 691                 break;
 692         default:
 693                 BUG();
 694                 return -EINVAL;
 695         }
 696
 697         return 0;
 698 }
 699
 700 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
 701 {
 702         struct i2c_client *i2c = to_i2c_client(codec->dev);
 703         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 704         int i, ret;
 705         unsigned long timeout = 200;
 706
 707         snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
 708
 709         /* Use the interrupt if possible */
 710         do {
 711                 if (i2c->irq) {
 712                         timeout = wait_for_completion_timeout(&wm8915->dcs_done,
 713                                                               msecs_to_jiffies(200));
 714                         if (timeout == 0)
 715                                 dev_err(codec->dev, "DC servo timed out\n");
 716
 717                 } else {
 718                         msleep(1);
 719                         if (--i) {
 720                                 timeout = 0;
 721                                 break;
 722                         }
 723                 }
 724
 725                 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
 726                 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
 727         } while (ret & mask);
 728
 729         if (timeout == 0)
 730                 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
 731         else
 732                 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
 733 }
 734
 735 static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
 736                                 enum snd_soc_dapm_type event, int subseq)
 737 {
 738         struct snd_soc_codec *codec = container_of(dapm,
 739                                                    struct snd_soc_codec, dapm);
 740         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 741         u16 val, mask;
 742
 743         /* Complete any pending DC servo starts */
 744         if (wm8915->dcs_pending) {
 745                 dev_dbg(codec->dev, "Starting DC servo for %x\n",
 746                         wm8915->dcs_pending);
 747
 748                 /* Trigger a startup sequence */
 749                 wait_for_dc_servo(codec, wm8915->dcs_pending
 750                                          << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
 751
 752                 wm8915->dcs_pending = 0;
 753         }
 754
 755         if (wm8915->hpout_pending != wm8915->hpout_ena) {
 756                 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
 757                         wm8915->hpout_ena, wm8915->hpout_pending);
 758
 759                 val = 0;
 760                 mask = 0;
 761                 if (wm8915->hpout_pending & HPOUT1L) {
 762                         val |= WM8915_HPOUT1L_RMV_SHORT;
 763                         mask |= WM8915_HPOUT1L_RMV_SHORT;
 764                 } else {
 765                         mask |= WM8915_HPOUT1L_RMV_SHORT |
 766                                 WM8915_HPOUT1L_OUTP |
 767                                 WM8915_HPOUT1L_DLY;
 768                 }
 769
 770                 if (wm8915->hpout_pending & HPOUT1R) {
 771                         val |= WM8915_HPOUT1R_RMV_SHORT;
 772                         mask |= WM8915_HPOUT1R_RMV_SHORT;
 773                 } else {
 774                         mask |= WM8915_HPOUT1R_RMV_SHORT |
 775                                 WM8915_HPOUT1R_OUTP |
 776                                 WM8915_HPOUT1R_DLY;
 777                 }
 778
 779                 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
 780
 781                 val = 0;
 782                 mask = 0;
 783                 if (wm8915->hpout_pending & HPOUT2L) {
 784                         val |= WM8915_HPOUT2L_RMV_SHORT;
 785                         mask |= WM8915_HPOUT2L_RMV_SHORT;
 786                 } else {
 787                         mask |= WM8915_HPOUT2L_RMV_SHORT |
 788                                 WM8915_HPOUT2L_OUTP |
 789                                 WM8915_HPOUT2L_DLY;
 790                 }
 791
 792                 if (wm8915->hpout_pending & HPOUT2R) {
 793                         val |= WM8915_HPOUT2R_RMV_SHORT;
 794                         mask |= WM8915_HPOUT2R_RMV_SHORT;
 795                 } else {
 796                         mask |= WM8915_HPOUT2R_RMV_SHORT |
 797                                 WM8915_HPOUT2R_OUTP |
 798                                 WM8915_HPOUT2R_DLY;
 799                 }
 800
 801                 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
 802
 803                 wm8915->hpout_ena = wm8915->hpout_pending;
 804         }
 805 }
 806
 807 static int dcs_start(struct snd_soc_dapm_widget *w,
 808                      struct snd_kcontrol *kcontrol, int event)
 809 {
 810         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
 811
 812         switch (event) {
 813         case SND_SOC_DAPM_POST_PMU:
 814                 wm8915->dcs_pending |= 1 << w->shift;
 815                 break;
 816         default:
 817                 BUG();
 818                 return -EINVAL;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static const char *sidetone_text[] = {
 825         "IN1", "IN2",
 826 };
 827
 828 static const struct soc_enum left_sidetone_enum =
 829         SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
 830
 831 static const struct snd_kcontrol_new left_sidetone =
 832         SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
 833
 834 static const struct soc_enum right_sidetone_enum =
 835         SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
 836
 837 static const struct snd_kcontrol_new right_sidetone =
 838         SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
 839
 840 static const char *spk_text[] = {
 841         "DAC1L", "DAC1R", "DAC2L", "DAC2R"
 842 };
 843
 844 static const struct soc_enum spkl_enum =
 845         SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
 846
 847 static const struct snd_kcontrol_new spkl_mux =
 848         SOC_DAPM_ENUM("SPKL", spkl_enum);
 849
 850 static const struct soc_enum spkr_enum =
 851         SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
 852
 853 static const struct snd_kcontrol_new spkr_mux =
 854         SOC_DAPM_ENUM("SPKR", spkr_enum);
 855
 856 static const char *dsp1rx_text[] = {
 857         "AIF1", "AIF2"
 858 };
 859
 860 static const struct soc_enum dsp1rx_enum =
 861         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
 862
 863 static const struct snd_kcontrol_new dsp1rx =
 864         SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
 865
 866 static const char *dsp2rx_text[] = {
 867          "AIF2", "AIF1"
 868 };
 869
 870 static const struct soc_enum dsp2rx_enum =
 871         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
 872
 873 static const struct snd_kcontrol_new dsp2rx =
 874         SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
 875
 876 static const char *aif2tx_text[] = {
 877         "DSP2", "DSP1", "AIF1"
 878 };
 879
 880 static const struct soc_enum aif2tx_enum =
 881         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
 882
 883 static const struct snd_kcontrol_new aif2tx =
 884         SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
 885
 886 static const char *inmux_text[] = {
 887         "ADC", "DMIC1", "DMIC2"
 888 };
 889
 890 static const struct soc_enum in1_enum =
 891         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
 892
 893 static const struct snd_kcontrol_new in1_mux =
 894         SOC_DAPM_ENUM("IN1 Mux", in1_enum);
 895
 896 static const struct soc_enum in2_enum =
 897         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
 898
 899 static const struct snd_kcontrol_new in2_mux =
 900         SOC_DAPM_ENUM("IN2 Mux", in2_enum);
 901
 902 static const struct snd_kcontrol_new dac2r_mix[] = {
 903 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
 904                 5, 1, 0),
 905 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
 906                 4, 1, 0),
 907 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
 908 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
 909 };
 910
 911 static const struct snd_kcontrol_new dac2l_mix[] = {
 912 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
 913                 5, 1, 0),
 914 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
 915                 4, 1, 0),
 916 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
 917 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
 918 };
 919
 920 static const struct snd_kcontrol_new dac1r_mix[] = {
 921 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
 922                 5, 1, 0),
 923 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
 924                 4, 1, 0),
 925 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
 926 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
 927 };
 928
 929 static const struct snd_kcontrol_new dac1l_mix[] = {
 930 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
 931                 5, 1, 0),
 932 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
 933                 4, 1, 0),
 934 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
 935 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
 936 };
 937
 938 static const struct snd_kcontrol_new dsp1txl[] = {
 939 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
 940                 1, 1, 0),
 941 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
 942                 0, 1, 0),
 943 };
 944
 945 static const struct snd_kcontrol_new dsp1txr[] = {
 946 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
 947                 1, 1, 0),
 948 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
 949                 0, 1, 0),
 950 };
 951
 952 static const struct snd_kcontrol_new dsp2txl[] = {
 953 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
 954                 1, 1, 0),
 955 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
 956                 0, 1, 0),
 957 };
 958
 959 static const struct snd_kcontrol_new dsp2txr[] = {
 960 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
 961                 1, 1, 0),
 962 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
 963                 0, 1, 0),
 964 };
 965
 966
 967 static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
 968 SND_SOC_DAPM_INPUT("IN1LN"),
 969 SND_SOC_DAPM_INPUT("IN1LP"),
 970 SND_SOC_DAPM_INPUT("IN1RN"),
 971 SND_SOC_DAPM_INPUT("IN1RP"),
 972
 973 SND_SOC_DAPM_INPUT("IN2LN"),
 974 SND_SOC_DAPM_INPUT("IN2LP"),
 975 SND_SOC_DAPM_INPUT("IN2RN"),
 976 SND_SOC_DAPM_INPUT("IN2RP"),
 977
 978 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 979 SND_SOC_DAPM_INPUT("DMIC2DAT"),
 980
 981 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
 982 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
 983 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
 984 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
 985                       SND_SOC_DAPM_POST_PMU),
 986
 987 SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
 988 SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
 989 SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
 990
 991 SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
 992 SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
 993
 994 SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
 995 SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
 996 SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
 997 SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
 998
 999 SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
1000 SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
1001 SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
1002 SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1003
1004 SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1005 SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1006
1007 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1008 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1009 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1010 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1011
1012 SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1013 SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1014
1015 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1016 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1017
1018 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1019 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1020 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1021 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1022
1023 SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1024                    dsp2txl, ARRAY_SIZE(dsp2txl)),
1025 SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1026                    dsp2txr, ARRAY_SIZE(dsp2txr)),
1027 SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1028                    dsp1txl, ARRAY_SIZE(dsp1txl)),
1029 SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1030                    dsp1txr, ARRAY_SIZE(dsp1txr)),
1031
1032 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1033                    dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1034 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1035                    dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1036 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1037                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1038 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1039                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1040
1041 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1042 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1043 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1044 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1045
1046 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1047                     WM8915_POWER_MANAGEMENT_4, 9, 0),
1048 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1049                     WM8915_POWER_MANAGEMENT_4, 8, 0),
1050
1051 SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1052                     WM8915_POWER_MANAGEMENT_6, 9, 0),
1053 SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1054                     WM8915_POWER_MANAGEMENT_6, 8, 0),
1055
1056 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1057                     WM8915_POWER_MANAGEMENT_4, 5, 0),
1058 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1059                     WM8915_POWER_MANAGEMENT_4, 4, 0),
1060 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1061                     WM8915_POWER_MANAGEMENT_4, 3, 0),
1062 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1063                     WM8915_POWER_MANAGEMENT_4, 2, 0),
1064 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1065                     WM8915_POWER_MANAGEMENT_4, 1, 0),
1066 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1067                     WM8915_POWER_MANAGEMENT_4, 0, 0),
1068
1069 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1070                      WM8915_POWER_MANAGEMENT_6, 5, 0),
1071 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1072                      WM8915_POWER_MANAGEMENT_6, 4, 0),
1073 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1074                      WM8915_POWER_MANAGEMENT_6, 3, 0),
1075 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1076                      WM8915_POWER_MANAGEMENT_6, 2, 0),
1077 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1078                      WM8915_POWER_MANAGEMENT_6, 1, 0),
1079 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1080                      WM8915_POWER_MANAGEMENT_6, 0, 0),
1081
1082 /* We route as stereo pairs so define some dummy widgets to squash
1083  * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
1084 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1085 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1086 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1087 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1088 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1089
1090 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1091 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1092 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1093
1094 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1095 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1096 SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1097 SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1098
1099 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1100 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1101 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1102                    SND_SOC_DAPM_POST_PMU),
1103 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1104 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1105                    rmv_short_event,
1106                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1107
1108 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1109 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1110 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1111                    SND_SOC_DAPM_POST_PMU),
1112 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1113 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1114                    rmv_short_event,
1115                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1116
1117 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1118 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1119 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1120                    SND_SOC_DAPM_POST_PMU),
1121 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1122 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1123                    rmv_short_event,
1124                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1125
1126 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1127 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1128 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1129                    SND_SOC_DAPM_POST_PMU),
1130 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1131 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1132                    rmv_short_event,
1133                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1134
1135 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1136 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1137 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1138 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1139 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1140 };
1141
1142 static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1143         { "AIFCLK", NULL, "SYSCLK" },
1144         { "SYSDSPCLK", NULL, "SYSCLK" },
1145         { "Charge Pump", NULL, "SYSCLK" },
1146
1147         { "MICB1", NULL, "LDO2" },
1148         { "MICB2", NULL, "LDO2" },
1149
1150         { "IN1L PGA", NULL, "IN2LN" },
1151         { "IN1L PGA", NULL, "IN2LP" },
1152         { "IN1L PGA", NULL, "IN1LN" },
1153         { "IN1L PGA", NULL, "IN1LP" },
1154
1155         { "IN1R PGA", NULL, "IN2RN" },
1156         { "IN1R PGA", NULL, "IN2RP" },
1157         { "IN1R PGA", NULL, "IN1RN" },
1158         { "IN1R PGA", NULL, "IN1RP" },
1159
1160         { "ADCL", NULL, "IN1L PGA" },
1161
1162         { "ADCR", NULL, "IN1R PGA" },
1163
1164         { "DMIC1L", NULL, "DMIC1DAT" },
1165         { "DMIC1R", NULL, "DMIC1DAT" },
1166         { "DMIC2L", NULL, "DMIC2DAT" },
1167         { "DMIC2R", NULL, "DMIC2DAT" },
1168
1169         { "DMIC2L", NULL, "DMIC2" },
1170         { "DMIC2R", NULL, "DMIC2" },
1171         { "DMIC1L", NULL, "DMIC1" },
1172         { "DMIC1R", NULL, "DMIC1" },
1173
1174         { "IN1L Mux", "ADC", "ADCL" },
1175         { "IN1L Mux", "DMIC1", "DMIC1L" },
1176         { "IN1L Mux", "DMIC2", "DMIC2L" },
1177
1178         { "IN1R Mux", "ADC", "ADCR" },
1179         { "IN1R Mux", "DMIC1", "DMIC1R" },
1180         { "IN1R Mux", "DMIC2", "DMIC2R" },
1181
1182         { "IN2L Mux", "ADC", "ADCL" },
1183         { "IN2L Mux", "DMIC1", "DMIC1L" },
1184         { "IN2L Mux", "DMIC2", "DMIC2L" },
1185
1186         { "IN2R Mux", "ADC", "ADCR" },
1187         { "IN2R Mux", "DMIC1", "DMIC1R" },
1188         { "IN2R Mux", "DMIC2", "DMIC2R" },
1189
1190         { "Left Sidetone", "IN1", "IN1L Mux" },
1191         { "Left Sidetone", "IN2", "IN2L Mux" },
1192
1193         { "Right Sidetone", "IN1", "IN1R Mux" },
1194         { "Right Sidetone", "IN2", "IN2R Mux" },
1195
1196         { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1197         { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1198
1199         { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1200         { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1201
1202         { "AIF1TX0", NULL, "DSP1TXL" },
1203         { "AIF1TX1", NULL, "DSP1TXR" },
1204         { "AIF1TX2", NULL, "DSP2TXL" },
1205         { "AIF1TX3", NULL, "DSP2TXR" },
1206         { "AIF1TX4", NULL, "AIF2RX0" },
1207         { "AIF1TX5", NULL, "AIF2RX1" },
1208
1209         { "AIF1RX0", NULL, "AIFCLK" },
1210         { "AIF1RX1", NULL, "AIFCLK" },
1211         { "AIF1RX2", NULL, "AIFCLK" },
1212         { "AIF1RX3", NULL, "AIFCLK" },
1213         { "AIF1RX4", NULL, "AIFCLK" },
1214         { "AIF1RX5", NULL, "AIFCLK" },
1215
1216         { "AIF2RX0", NULL, "AIFCLK" },
1217         { "AIF2RX1", NULL, "AIFCLK" },
1218
1219         { "DSP1RXL", NULL, "SYSDSPCLK" },
1220         { "DSP1RXR", NULL, "SYSDSPCLK" },
1221         { "DSP2RXL", NULL, "SYSDSPCLK" },
1222         { "DSP2RXR", NULL, "SYSDSPCLK" },
1223         { "DSP1TXL", NULL, "SYSDSPCLK" },
1224         { "DSP1TXR", NULL, "SYSDSPCLK" },
1225         { "DSP2TXL", NULL, "SYSDSPCLK" },
1226         { "DSP2TXR", NULL, "SYSDSPCLK" },
1227
1228         { "AIF1RXA", NULL, "AIF1RX0" },
1229         { "AIF1RXA", NULL, "AIF1RX1" },
1230         { "AIF1RXB", NULL, "AIF1RX2" },
1231         { "AIF1RXB", NULL, "AIF1RX3" },
1232         { "AIF1RXC", NULL, "AIF1RX4" },
1233         { "AIF1RXC", NULL, "AIF1RX5" },
1234
1235         { "AIF2RX", NULL, "AIF2RX0" },
1236         { "AIF2RX", NULL, "AIF2RX1" },
1237
1238         { "AIF2TX", "DSP2", "DSP2TX" },
1239         { "AIF2TX", "DSP1", "DSP1RX" },
1240         { "AIF2TX", "AIF1", "AIF1RXC" },
1241
1242         { "DSP1RXL", NULL, "DSP1RX" },
1243         { "DSP1RXR", NULL, "DSP1RX" },
1244         { "DSP2RXL", NULL, "DSP2RX" },
1245         { "DSP2RXR", NULL, "DSP2RX" },
1246
1247         { "DSP2TX", NULL, "DSP2TXL" },
1248         { "DSP2TX", NULL, "DSP2TXR" },
1249
1250         { "DSP1RX", "AIF1", "AIF1RXA" },
1251         { "DSP1RX", "AIF2", "AIF2RX" },
1252
1253         { "DSP2RX", "AIF1", "AIF1RXB" },
1254         { "DSP2RX", "AIF2", "AIF2RX" },
1255
1256         { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1257         { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1258         { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1259         { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1260
1261         { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1262         { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1263         { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1264         { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1265
1266         { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1267         { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1268         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1269         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1270
1271         { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1272         { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1273         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1274         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1275
1276         { "DAC1L", NULL, "DAC1L Mixer" },
1277         { "DAC1R", NULL, "DAC1R Mixer" },
1278         { "DAC2L", NULL, "DAC2L Mixer" },
1279         { "DAC2R", NULL, "DAC2R Mixer" },
1280
1281         { "HPOUT2L PGA", NULL, "Charge Pump" },
1282         { "HPOUT2L PGA", NULL, "DAC2L" },
1283         { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1284         { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1285         { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1286         { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1287
1288         { "HPOUT2R PGA", NULL, "Charge Pump" },
1289         { "HPOUT2R PGA", NULL, "DAC2R" },
1290         { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1291         { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1292         { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1293         { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1294
1295         { "HPOUT1L PGA", NULL, "Charge Pump" },
1296         { "HPOUT1L PGA", NULL, "DAC1L" },
1297         { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1298         { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1299         { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1300         { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1301
1302         { "HPOUT1R PGA", NULL, "Charge Pump" },
1303         { "HPOUT1R PGA", NULL, "DAC1R" },
1304         { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1305         { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1306         { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1307         { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1308
1309         { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1310         { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1311         { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1312         { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1313
1314         { "SPKL", "DAC1L", "DAC1L" },
1315         { "SPKL", "DAC1R", "DAC1R" },
1316         { "SPKL", "DAC2L", "DAC2L" },
1317         { "SPKL", "DAC2R", "DAC2R" },
1318
1319         { "SPKR", "DAC1L", "DAC1L" },
1320         { "SPKR", "DAC1R", "DAC1R" },
1321         { "SPKR", "DAC2L", "DAC2L" },
1322         { "SPKR", "DAC2R", "DAC2R" },
1323
1324         { "SPKL PGA", NULL, "SPKL" },
1325         { "SPKR PGA", NULL, "SPKR" },
1326
1327         { "SPKDAT", NULL, "SPKL PGA" },
1328         { "SPKDAT", NULL, "SPKR PGA" },
1329 };
1330
1331 static int wm8915_readable_register(struct snd_soc_codec *codec,
1332                                     unsigned int reg)
1333 {
1334         /* Due to the sparseness of the register map the compiler
1335          * output from an explicit switch statement ends up being much
1336          * more efficient than a table.
1337          */
1338         switch (reg) {
1339         case WM8915_SOFTWARE_RESET:
1340         case WM8915_POWER_MANAGEMENT_1:
1341         case WM8915_POWER_MANAGEMENT_2:
1342         case WM8915_POWER_MANAGEMENT_3:
1343         case WM8915_POWER_MANAGEMENT_4:
1344         case WM8915_POWER_MANAGEMENT_5:
1345         case WM8915_POWER_MANAGEMENT_6:
1346         case WM8915_POWER_MANAGEMENT_7:
1347         case WM8915_POWER_MANAGEMENT_8:
1348         case WM8915_LEFT_LINE_INPUT_VOLUME:
1349         case WM8915_RIGHT_LINE_INPUT_VOLUME:
1350         case WM8915_LINE_INPUT_CONTROL:
1351         case WM8915_DAC1_HPOUT1_VOLUME:
1352         case WM8915_DAC2_HPOUT2_VOLUME:
1353         case WM8915_DAC1_LEFT_VOLUME:
1354         case WM8915_DAC1_RIGHT_VOLUME:
1355         case WM8915_DAC2_LEFT_VOLUME:
1356         case WM8915_DAC2_RIGHT_VOLUME:
1357         case WM8915_OUTPUT1_LEFT_VOLUME:
1358         case WM8915_OUTPUT1_RIGHT_VOLUME:
1359         case WM8915_OUTPUT2_LEFT_VOLUME:
1360         case WM8915_OUTPUT2_RIGHT_VOLUME:
1361         case WM8915_MICBIAS_1:
1362         case WM8915_MICBIAS_2:
1363         case WM8915_LDO_1:
1364         case WM8915_LDO_2:
1365         case WM8915_ACCESSORY_DETECT_MODE_1:
1366         case WM8915_ACCESSORY_DETECT_MODE_2:
1367         case WM8915_HEADPHONE_DETECT_1:
1368         case WM8915_HEADPHONE_DETECT_2:
1369         case WM8915_MIC_DETECT_1:
1370         case WM8915_MIC_DETECT_2:
1371         case WM8915_MIC_DETECT_3:
1372         case WM8915_CHARGE_PUMP_1:
1373         case WM8915_CHARGE_PUMP_2:
1374         case WM8915_DC_SERVO_1:
1375         case WM8915_DC_SERVO_2:
1376         case WM8915_DC_SERVO_3:
1377         case WM8915_DC_SERVO_5:
1378         case WM8915_DC_SERVO_6:
1379         case WM8915_DC_SERVO_7:
1380         case WM8915_DC_SERVO_READBACK_0:
1381         case WM8915_ANALOGUE_HP_1:
1382         case WM8915_ANALOGUE_HP_2:
1383         case WM8915_CHIP_REVISION:
1384         case WM8915_CONTROL_INTERFACE_1:
1385         case WM8915_WRITE_SEQUENCER_CTRL_1:
1386         case WM8915_WRITE_SEQUENCER_CTRL_2:
1387         case WM8915_AIF_CLOCKING_1:
1388         case WM8915_AIF_CLOCKING_2:
1389         case WM8915_CLOCKING_1:
1390         case WM8915_CLOCKING_2:
1391         case WM8915_AIF_RATE:
1392         case WM8915_FLL_CONTROL_1:
1393         case WM8915_FLL_CONTROL_2:
1394         case WM8915_FLL_CONTROL_3:
1395         case WM8915_FLL_CONTROL_4:
1396         case WM8915_FLL_CONTROL_5:
1397         case WM8915_FLL_CONTROL_6:
1398         case WM8915_FLL_EFS_1:
1399         case WM8915_FLL_EFS_2:
1400         case WM8915_AIF1_CONTROL:
1401         case WM8915_AIF1_BCLK:
1402         case WM8915_AIF1_TX_LRCLK_1:
1403         case WM8915_AIF1_TX_LRCLK_2:
1404         case WM8915_AIF1_RX_LRCLK_1:
1405         case WM8915_AIF1_RX_LRCLK_2:
1406         case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1407         case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1408         case WM8915_AIF1RX_DATA_CONFIGURATION:
1409         case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1410         case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1411         case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1412         case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1413         case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1414         case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1415         case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1416         case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1417         case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1418         case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1419         case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1420         case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1421         case WM8915_AIF1RX_MONO_CONFIGURATION:
1422         case WM8915_AIF1TX_TEST:
1423         case WM8915_AIF2_CONTROL:
1424         case WM8915_AIF2_BCLK:
1425         case WM8915_AIF2_TX_LRCLK_1:
1426         case WM8915_AIF2_TX_LRCLK_2:
1427         case WM8915_AIF2_RX_LRCLK_1:
1428         case WM8915_AIF2_RX_LRCLK_2:
1429         case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1430         case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1431         case WM8915_AIF2RX_DATA_CONFIGURATION:
1432         case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1433         case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1434         case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1435         case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1436         case WM8915_AIF2RX_MONO_CONFIGURATION:
1437         case WM8915_AIF2TX_TEST:
1438         case WM8915_DSP1_TX_LEFT_VOLUME:
1439         case WM8915_DSP1_TX_RIGHT_VOLUME:
1440         case WM8915_DSP1_RX_LEFT_VOLUME:
1441         case WM8915_DSP1_RX_RIGHT_VOLUME:
1442         case WM8915_DSP1_TX_FILTERS:
1443         case WM8915_DSP1_RX_FILTERS_1:
1444         case WM8915_DSP1_RX_FILTERS_2:
1445         case WM8915_DSP1_DRC_1:
1446         case WM8915_DSP1_DRC_2:
1447         case WM8915_DSP1_DRC_3:
1448         case WM8915_DSP1_DRC_4:
1449         case WM8915_DSP1_DRC_5:
1450         case WM8915_DSP1_RX_EQ_GAINS_1:
1451         case WM8915_DSP1_RX_EQ_GAINS_2:
1452         case WM8915_DSP1_RX_EQ_BAND_1_A:
1453         case WM8915_DSP1_RX_EQ_BAND_1_B:
1454         case WM8915_DSP1_RX_EQ_BAND_1_PG:
1455         case WM8915_DSP1_RX_EQ_BAND_2_A:
1456         case WM8915_DSP1_RX_EQ_BAND_2_B:
1457         case WM8915_DSP1_RX_EQ_BAND_2_C:
1458         case WM8915_DSP1_RX_EQ_BAND_2_PG:
1459         case WM8915_DSP1_RX_EQ_BAND_3_A:
1460         case WM8915_DSP1_RX_EQ_BAND_3_B:
1461         case WM8915_DSP1_RX_EQ_BAND_3_C:
1462         case WM8915_DSP1_RX_EQ_BAND_3_PG:
1463         case WM8915_DSP1_RX_EQ_BAND_4_A:
1464         case WM8915_DSP1_RX_EQ_BAND_4_B:
1465         case WM8915_DSP1_RX_EQ_BAND_4_C:
1466         case WM8915_DSP1_RX_EQ_BAND_4_PG:
1467         case WM8915_DSP1_RX_EQ_BAND_5_A:
1468         case WM8915_DSP1_RX_EQ_BAND_5_B:
1469         case WM8915_DSP1_RX_EQ_BAND_5_PG:
1470         case WM8915_DSP2_TX_LEFT_VOLUME:
1471         case WM8915_DSP2_TX_RIGHT_VOLUME:
1472         case WM8915_DSP2_RX_LEFT_VOLUME:
1473         case WM8915_DSP2_RX_RIGHT_VOLUME:
1474         case WM8915_DSP2_TX_FILTERS:
1475         case WM8915_DSP2_RX_FILTERS_1:
1476         case WM8915_DSP2_RX_FILTERS_2:
1477         case WM8915_DSP2_DRC_1:
1478         case WM8915_DSP2_DRC_2:
1479         case WM8915_DSP2_DRC_3:
1480         case WM8915_DSP2_DRC_4:
1481         case WM8915_DSP2_DRC_5:
1482         case WM8915_DSP2_RX_EQ_GAINS_1:
1483         case WM8915_DSP2_RX_EQ_GAINS_2:
1484         case WM8915_DSP2_RX_EQ_BAND_1_A:
1485         case WM8915_DSP2_RX_EQ_BAND_1_B:
1486         case WM8915_DSP2_RX_EQ_BAND_1_PG:
1487         case WM8915_DSP2_RX_EQ_BAND_2_A:
1488         case WM8915_DSP2_RX_EQ_BAND_2_B:
1489         case WM8915_DSP2_RX_EQ_BAND_2_C:
1490         case WM8915_DSP2_RX_EQ_BAND_2_PG:
1491         case WM8915_DSP2_RX_EQ_BAND_3_A:
1492         case WM8915_DSP2_RX_EQ_BAND_3_B:
1493         case WM8915_DSP2_RX_EQ_BAND_3_C:
1494         case WM8915_DSP2_RX_EQ_BAND_3_PG:
1495         case WM8915_DSP2_RX_EQ_BAND_4_A:
1496         case WM8915_DSP2_RX_EQ_BAND_4_B:
1497         case WM8915_DSP2_RX_EQ_BAND_4_C:
1498         case WM8915_DSP2_RX_EQ_BAND_4_PG:
1499         case WM8915_DSP2_RX_EQ_BAND_5_A:
1500         case WM8915_DSP2_RX_EQ_BAND_5_B:
1501         case WM8915_DSP2_RX_EQ_BAND_5_PG:
1502         case WM8915_DAC1_MIXER_VOLUMES:
1503         case WM8915_DAC1_LEFT_MIXER_ROUTING:
1504         case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1505         case WM8915_DAC2_MIXER_VOLUMES:
1506         case WM8915_DAC2_LEFT_MIXER_ROUTING:
1507         case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1508         case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1509         case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1510         case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1511         case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1512         case WM8915_DSP_TX_MIXER_SELECT:
1513         case WM8915_DAC_SOFTMUTE:
1514         case WM8915_OVERSAMPLING:
1515         case WM8915_SIDETONE:
1516         case WM8915_GPIO_1:
1517         case WM8915_GPIO_2:
1518         case WM8915_GPIO_3:
1519         case WM8915_GPIO_4:
1520         case WM8915_GPIO_5:
1521         case WM8915_PULL_CONTROL_1:
1522         case WM8915_PULL_CONTROL_2:
1523         case WM8915_INTERRUPT_STATUS_1:
1524         case WM8915_INTERRUPT_STATUS_2:
1525         case WM8915_INTERRUPT_RAW_STATUS_2:
1526         case WM8915_INTERRUPT_STATUS_1_MASK:
1527         case WM8915_INTERRUPT_STATUS_2_MASK:
1528         case WM8915_INTERRUPT_CONTROL:
1529         case WM8915_LEFT_PDM_SPEAKER:
1530         case WM8915_RIGHT_PDM_SPEAKER:
1531         case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1532         case WM8915_PDM_SPEAKER_VOLUME:
1533                 return 1;
1534         default:
1535                 return 0;
1536         }
1537 }
1538
1539 static int wm8915_volatile_register(struct snd_soc_codec *codec,
1540                                     unsigned int reg)
1541 {
1542         switch (reg) {
1543         case WM8915_SOFTWARE_RESET:
1544         case WM8915_CHIP_REVISION:
1545         case WM8915_LDO_1:
1546         case WM8915_LDO_2:
1547         case WM8915_INTERRUPT_STATUS_1:
1548         case WM8915_INTERRUPT_STATUS_2:
1549         case WM8915_INTERRUPT_RAW_STATUS_2:
1550         case WM8915_DC_SERVO_READBACK_0:
1551         case WM8915_DC_SERVO_2:
1552         case WM8915_DC_SERVO_6:
1553         case WM8915_DC_SERVO_7:
1554         case WM8915_FLL_CONTROL_6:
1555         case WM8915_MIC_DETECT_3:
1556         case WM8915_HEADPHONE_DETECT_1:
1557         case WM8915_HEADPHONE_DETECT_2:
1558                 return 1;
1559         default:
1560                 return 0;
1561         }
1562 }
1563
1564 static int wm8915_reset(struct snd_soc_codec *codec)
1565 {
1566         return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1567 }
1568
1569 static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1570                                  enum snd_soc_bias_level level)
1571 {
1572         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1573         int ret;
1574
1575         switch (level) {
1576         case SND_SOC_BIAS_ON:
1577                 break;
1578
1579         case SND_SOC_BIAS_PREPARE:
1580                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1581                         snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1582                                             WM8915_BG_ENA, WM8915_BG_ENA);
1583                         msleep(2);
1584                 }
1585                 break;
1586
1587         case SND_SOC_BIAS_STANDBY:
1588                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1589                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1590                                                     wm8915->supplies);
1591                         if (ret != 0) {
1592                                 dev_err(codec->dev,
1593                                         "Failed to enable supplies: %d\n",
1594                                         ret);
1595                                 return ret;
1596                         }
1597
1598                         if (wm8915->pdata.ldo_ena >= 0) {
1599                                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1600                                                         1);
1601                                 msleep(5);
1602                         }
1603
1604                         codec->cache_only = false;
1605                         snd_soc_cache_sync(codec);
1606                 }
1607
1608                 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1609                                     WM8915_BG_ENA, 0);
1610                 break;
1611
1612         case SND_SOC_BIAS_OFF:
1613                 codec->cache_only = true;
1614                 if (wm8915->pdata.ldo_ena >= 0)
1615                         gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1616                 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1617                                        wm8915->supplies);
1618                 break;
1619         }
1620
1621         codec->dapm.bias_level = level;
1622
1623         return 0;
1624 }
1625
1626 static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1627 {
1628         struct snd_soc_codec *codec = dai->codec;
1629         int aifctrl = 0;
1630         int bclk = 0;
1631         int lrclk_tx = 0;
1632         int lrclk_rx = 0;
1633         int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1634
1635         switch (dai->id) {
1636         case 0:
1637                 aifctrl_reg = WM8915_AIF1_CONTROL;
1638                 bclk_reg = WM8915_AIF1_BCLK;
1639                 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1640                 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1641                 break;
1642         case 1:
1643                 aifctrl_reg = WM8915_AIF2_CONTROL;
1644                 bclk_reg = WM8915_AIF2_BCLK;
1645                 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1646                 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1647                 break;
1648         default:
1649                 BUG();
1650                 return -EINVAL;
1651         }
1652
1653         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1654         case SND_SOC_DAIFMT_NB_NF:
1655                 break;
1656         case SND_SOC_DAIFMT_IB_NF:
1657                 bclk |= WM8915_AIF1_BCLK_INV;
1658                 break;
1659         case SND_SOC_DAIFMT_NB_IF:
1660                 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1661                 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1662                 break;
1663         case SND_SOC_DAIFMT_IB_IF:
1664                 bclk |= WM8915_AIF1_BCLK_INV;
1665                 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1666                 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1667                 break;
1668         }
1669
1670         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1671         case SND_SOC_DAIFMT_CBS_CFS:
1672                 break;
1673         case SND_SOC_DAIFMT_CBS_CFM:
1674                 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1675                 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1676                 break;
1677         case SND_SOC_DAIFMT_CBM_CFS:
1678                 bclk |= WM8915_AIF1_BCLK_MSTR;
1679                 break;
1680         case SND_SOC_DAIFMT_CBM_CFM:
1681                 bclk |= WM8915_AIF1_BCLK_MSTR;
1682                 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1683                 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1684                 break;
1685         default:
1686                 return -EINVAL;
1687         }
1688
1689         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1690         case SND_SOC_DAIFMT_DSP_A:
1691                 break;
1692         case SND_SOC_DAIFMT_DSP_B:
1693                 aifctrl |= 1;
1694                 break;
1695         case SND_SOC_DAIFMT_I2S:
1696                 aifctrl |= 2;
1697                 break;
1698         case SND_SOC_DAIFMT_LEFT_J:
1699                 aifctrl |= 3;
1700                 break;
1701         default:
1702                 return -EINVAL;
1703         }
1704
1705         snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1706         snd_soc_update_bits(codec, bclk_reg,
1707                             WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1708                             bclk);
1709         snd_soc_update_bits(codec, lrclk_tx_reg,
1710                             WM8915_AIF1TX_LRCLK_INV |
1711                             WM8915_AIF1TX_LRCLK_MSTR,
1712                             lrclk_tx);
1713         snd_soc_update_bits(codec, lrclk_rx_reg,
1714                             WM8915_AIF1RX_LRCLK_INV |
1715                             WM8915_AIF1RX_LRCLK_MSTR,
1716                             lrclk_rx);
1717
1718         return 0;
1719 }
1720
1721 static const int bclk_divs[] = {
1722         1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1723 };
1724
1725 static const int dsp_divs[] = {
1726         48000, 32000, 16000, 8000
1727 };
1728
1729 static int wm8915_hw_params(struct snd_pcm_substream *substream,
1730                             struct snd_pcm_hw_params *params,
1731                             struct snd_soc_dai *dai)
1732 {
1733         struct snd_soc_codec *codec = dai->codec;
1734         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1735         int bits, i, bclk_rate, best, cur_val;
1736         int aifdata = 0;
1737         int bclk = 0;
1738         int lrclk = 0;
1739         int dsp = 0;
1740         int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
1741
1742         if (!wm8915->sysclk) {
1743                 dev_err(codec->dev, "SYSCLK not configured\n");
1744                 return -EINVAL;
1745         }
1746
1747         switch (dai->id) {
1748         case 0:
1749                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1750                     (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1751                         aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1752                         lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1753                 } else {
1754                         aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1755                         lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1756                 }
1757                 bclk_reg = WM8915_AIF1_BCLK;
1758                 dsp_shift = 0;
1759                 break;
1760         case 1:
1761                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1762                     (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1763                         aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1764                         lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1765                 } else {
1766                         aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1767                         lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1768                 }
1769                 bclk_reg = WM8915_AIF2_BCLK;
1770                 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1771                 break;
1772         default:
1773                 BUG();
1774                 return -EINVAL;
1775         }
1776
1777         bclk_rate = snd_soc_params_to_bclk(params);
1778         if (bclk_rate < 0) {
1779                 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1780                 return bclk_rate;
1781         }
1782
1783         /* Needs looking at for TDM */
1784         bits = snd_pcm_format_width(params_format(params));
1785         if (bits < 0)
1786                 return bits;
1787         aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1788
1789         for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1790                 if (dsp_divs[i] == params_rate(params))
1791                         break;
1792         }
1793         if (i == ARRAY_SIZE(dsp_divs)) {
1794                 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1795                         params_rate(params));
1796                 return -EINVAL;
1797         }
1798         dsp |= i << dsp_shift;
1799
1800         /* Pick a divisor for BCLK as close as we can get to ideal */
1801         best = 0;
1802         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1803                 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1804                 if (cur_val < 0) /* BCLK table is sorted */
1805                         break;
1806                 best = i;
1807         }
1808         bclk_rate = wm8915->sysclk / bclk_divs[best];
1809         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1810                 bclk_divs[best], bclk_rate);
1811         bclk |= best;
1812
1813         lrclk = bclk_rate / params_rate(params);
1814         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1815                 lrclk, bclk_rate / lrclk);
1816
1817         snd_soc_update_bits(codec, aifdata_reg,
1818                             WM8915_AIF1TX_WL_MASK |
1819                             WM8915_AIF1TX_SLOT_LEN_MASK,
1820                             aifdata);
1821         snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
1822         snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1823                             lrclk);
1824         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1825                             WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1826
1827         wm8915->rx_rate[dai->id] = params_rate(params);
1828
1829         return 0;
1830 }
1831
1832 static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1833                 int clk_id, unsigned int freq, int dir)
1834 {
1835         struct snd_soc_codec *codec = dai->codec;
1836         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1837         int lfclk = 0;
1838         int ratediv = 0;
1839         int src;
1840         int old;
1841
1842         /* Disable SYSCLK while we reconfigure */
1843         old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1);
1844         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1845                             WM8915_SYSCLK_ENA, 0);
1846
1847         switch (clk_id) {
1848         case WM8915_SYSCLK_MCLK1:
1849                 wm8915->sysclk = freq;
1850                 src = 0;
1851                 break;
1852         case WM8915_SYSCLK_MCLK2:
1853                 wm8915->sysclk = freq;
1854                 src = 1;
1855                 break;
1856         case WM8915_SYSCLK_FLL:
1857                 wm8915->sysclk = freq;
1858                 src = 2;
1859                 break;
1860         default:
1861                 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1862                 return -EINVAL;
1863         }
1864
1865         switch (wm8915->sysclk) {
1866         case 6144000:
1867                 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1868                                     WM8915_SYSCLK_RATE, 0);
1869                 break;
1870         case 24576000:
1871                 ratediv = WM8915_SYSCLK_DIV;
1872         case 12288000:
1873                 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1874                                     WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1875                 break;
1876         case 32000:
1877         case 32768:
1878                 lfclk = WM8915_LFCLK_ENA;
1879                 break;
1880         default:
1881                 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1882                          wm8915->sysclk);
1883                 return -EINVAL;
1884         }
1885
1886         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1887                             WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
1888                             src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
1889         snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1890         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1891                             WM8915_SYSCLK_ENA, old);
1892
1893         return 0;
1894 }
1895
1896 struct _fll_div {
1897         u16 fll_fratio;
1898         u16 fll_outdiv;
1899         u16 fll_refclk_div;
1900         u16 fll_loop_gain;
1901         u16 fll_ref_freq;
1902         u16 n;
1903         u16 theta;
1904         u16 lambda;
1905 };
1906
1907 static struct {
1908         unsigned int min;
1909         unsigned int max;
1910         u16 fll_fratio;
1911         int ratio;
1912 } fll_fratios[] = {
1913         {       0,    64000, 4, 16 },
1914         {   64000,   128000, 3,  8 },
1915         {  128000,   256000, 2,  4 },
1916         {  256000,  1000000, 1,  2 },
1917         { 1000000, 13500000, 0,  1 },
1918 };
1919
1920 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1921                        unsigned int Fout)
1922 {
1923         unsigned int target;
1924         unsigned int div;
1925         unsigned int fratio, gcd_fll;
1926         int i;
1927
1928         /* Fref must be <=13.5MHz */
1929         div = 1;
1930         fll_div->fll_refclk_div = 0;
1931         while ((Fref / div) > 13500000) {
1932                 div *= 2;
1933                 fll_div->fll_refclk_div++;
1934
1935                 if (div > 8) {
1936                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1937                                Fref);
1938                         return -EINVAL;
1939                 }
1940         }
1941
1942         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1943
1944         /* Apply the division for our remaining calculations */
1945         Fref /= div;
1946
1947         if (Fref >= 3000000)
1948                 fll_div->fll_loop_gain = 5;
1949         else
1950                 fll_div->fll_loop_gain = 0;
1951
1952         if (Fref >= 48000)
1953                 fll_div->fll_ref_freq = 0;
1954         else
1955                 fll_div->fll_ref_freq = 1;
1956
1957         /* Fvco should be 90-100MHz; don't check the upper bound */
1958         div = 2;
1959         while (Fout * div < 90000000) {
1960                 div++;
1961                 if (div > 64) {
1962                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1963                                Fout);
1964                         return -EINVAL;
1965                 }
1966         }
1967         target = Fout * div;
1968         fll_div->fll_outdiv = div - 1;
1969
1970         pr_debug("FLL Fvco=%dHz\n", target);
1971
1972         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1973         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1974                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1975                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1976                         fratio = fll_fratios[i].ratio;
1977                         break;
1978                 }
1979         }
1980         if (i == ARRAY_SIZE(fll_fratios)) {
1981                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1982                 return -EINVAL;
1983         }
1984
1985         fll_div->n = target / (fratio * Fref);
1986
1987         if (target % Fref == 0) {
1988                 fll_div->theta = 0;
1989                 fll_div->lambda = 0;
1990         } else {
1991                 gcd_fll = gcd(target, fratio * Fref);
1992
1993                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1994                         / gcd_fll;
1995                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1996         }
1997
1998         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1999                  fll_div->n, fll_div->theta, fll_div->lambda);
2000         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2001                  fll_div->fll_fratio, fll_div->fll_outdiv,
2002                  fll_div->fll_refclk_div);
2003
2004         return 0;
2005 }
2006
2007 static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2008                           unsigned int Fref, unsigned int Fout)
2009 {
2010         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2011         struct _fll_div fll_div;
2012         unsigned long timeout;
2013         int ret, reg;
2014
2015         /* Any change? */
2016         if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2017             Fout == wm8915->fll_fout)
2018                 return 0;
2019
2020         if (Fout == 0) {
2021                 dev_dbg(codec->dev, "FLL disabled\n");
2022
2023                 wm8915->fll_fref = 0;
2024                 wm8915->fll_fout = 0;
2025
2026                 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2027                                     WM8915_FLL_ENA, 0);
2028
2029                 return 0;
2030         }
2031
2032         ret = fll_factors(&fll_div, Fref, Fout);
2033         if (ret != 0)
2034                 return ret;
2035
2036         switch (source) {
2037         case WM8915_FLL_MCLK1:
2038                 reg = 0;
2039                 break;
2040         case WM8915_FLL_MCLK2:
2041                 reg = 1;
2042         case WM8915_FLL_DACLRCLK1:
2043                 reg = 2;
2044                 break;
2045         case WM8915_FLL_BCLK1:
2046                 reg = 3;
2047                 break;
2048         default:
2049                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2050                 return -EINVAL;
2051         }
2052
2053         reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2054         reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2055
2056         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2057                             WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2058                             WM8915_FLL_REFCLK_SRC_MASK, reg);
2059
2060         reg = 0;
2061         if (fll_div.theta || fll_div.lambda)
2062                 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2063         else
2064                 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2065         snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2066
2067         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2068                             WM8915_FLL_OUTDIV_MASK |
2069                             WM8915_FLL_FRATIO_MASK,
2070                             (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2071                             (fll_div.fll_fratio));
2072
2073         snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2074
2075         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2076                             WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2077                             (fll_div.n << WM8915_FLL_N_SHIFT) |
2078                             fll_div.fll_loop_gain);
2079
2080         snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2081
2082         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2083                             WM8915_FLL_ENA, WM8915_FLL_ENA);
2084
2085         /* The FLL supports live reconfiguration - kick that in case we were
2086          * already enabled.
2087          */
2088         snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2089
2090         /* Wait for the FLL to lock, using the interrupt if possible */
2091         if (Fref > 1000000)
2092                 timeout = usecs_to_jiffies(300);
2093         else
2094                 timeout = msecs_to_jiffies(2);
2095
2096         wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2097
2098         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2099
2100         wm8915->fll_fref = Fref;
2101         wm8915->fll_fout = Fout;
2102         wm8915->fll_src = source;
2103
2104         return 0;
2105 }
2106
2107 #ifdef CONFIG_GPIOLIB
2108 static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2109 {
2110         return container_of(chip, struct wm8915_priv, gpio_chip);
2111 }
2112
2113 static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2114 {
2115         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2116         struct snd_soc_codec *codec = wm8915->codec;
2117
2118         snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2119                             WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2120 }
2121
2122 static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2123                                      unsigned offset, int value)
2124 {
2125         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2126         struct snd_soc_codec *codec = wm8915->codec;
2127         int val;
2128
2129         val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2130
2131         return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2132                                    WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2133                                    WM8915_GP1_LVL, val);
2134 }
2135
2136 static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2137 {
2138         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2139         struct snd_soc_codec *codec = wm8915->codec;
2140         int ret;
2141
2142         ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2143         if (ret < 0)
2144                 return ret;
2145
2146         return (ret & WM8915_GP1_LVL) != 0;
2147 }
2148
2149 static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2150 {
2151         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2152         struct snd_soc_codec *codec = wm8915->codec;
2153
2154         return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2155                                    WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2156                                    (1 << WM8915_GP1_FN_SHIFT) |
2157                                    (1 << WM8915_GP1_DIR_SHIFT));
2158 }
2159
2160 static struct gpio_chip wm8915_template_chip = {
2161         .label                  = "wm8915",
2162         .owner                  = THIS_MODULE,
2163         .direction_output       = wm8915_gpio_direction_out,
2164         .set                    = wm8915_gpio_set,
2165         .direction_input        = wm8915_gpio_direction_in,
2166         .get                    = wm8915_gpio_get,
2167         .can_sleep              = 1,
2168 };
2169
2170 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2171 {
2172         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2173         int ret;
2174
2175         wm8915->gpio_chip = wm8915_template_chip;
2176         wm8915->gpio_chip.ngpio = 5;
2177         wm8915->gpio_chip.dev = codec->dev;
2178
2179         if (wm8915->pdata.gpio_base)
2180                 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2181         else
2182                 wm8915->gpio_chip.base = -1;
2183
2184         ret = gpiochip_add(&wm8915->gpio_chip);
2185         if (ret != 0)
2186                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2187 }
2188
2189 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2190 {
2191         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2192         int ret;
2193
2194         ret = gpiochip_remove(&wm8915->gpio_chip);
2195         if (ret != 0)
2196                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2197 }
2198 #else
2199 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2200 {
2201 }
2202
2203 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2204 {
2205 }
2206 #endif
2207
2208 /**
2209  * wm8915_detect - Enable default WM8915 jack detection
2210  *
2211  * The WM8915 has advanced accessory detection support for headsets.
2212  * This function provides a default implementation which integrates
2213  * the majority of this functionality with minimal user configuration.
2214  *
2215  * This will detect headset, headphone and short circuit button and
2216  * will also detect inverted microphone ground connections and update
2217  * the polarity of the connections.
2218  */
2219 int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2220                   wm8915_polarity_fn polarity_cb)
2221 {
2222         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2223
2224         wm8915->jack = jack;
2225         wm8915->detecting = true;
2226         wm8915->polarity_cb = polarity_cb;
2227
2228         if (wm8915->polarity_cb)
2229                 wm8915->polarity_cb(codec, 0);
2230
2231         /* Clear discarge to avoid noise during detection */
2232         snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2233                             WM8915_MICB1_DISCH, 0);
2234         snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2235                             WM8915_MICB2_DISCH, 0);
2236
2237         /* LDO2 powers the microphones, SYSCLK clocks detection */
2238         snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2239         snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2240
2241         /* We start off just enabling microphone detection - even a
2242          * plain headphone will trigger detection.
2243          */
2244         snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2245                             WM8915_MICD_ENA, WM8915_MICD_ENA);
2246
2247         /* Slowest detection rate, gives debounce for initial detection */
2248         snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2249                             WM8915_MICD_RATE_MASK,
2250                             WM8915_MICD_RATE_MASK);
2251
2252         /* Enable interrupts and we're off */
2253         snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2254                             WM8915_IM_MICD_EINT, 0);
2255
2256         return 0;
2257 }
2258 EXPORT_SYMBOL_GPL(wm8915_detect);
2259
2260 static void wm8915_micd(struct snd_soc_codec *codec)
2261 {
2262         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2263         int val, reg;
2264
2265         val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2266
2267         dev_dbg(codec->dev, "Microphone event: %x\n", val);
2268
2269         if (!(val & WM8915_MICD_VALID)) {
2270                 dev_warn(codec->dev, "Microphone detection state invalid\n");
2271                 return;
2272         }
2273
2274         /* No accessory, reset everything and report removal */
2275         if (!(val & WM8915_MICD_STS)) {
2276                 dev_dbg(codec->dev, "Jack removal detected\n");
2277                 wm8915->jack_mic = false;
2278                 wm8915->detecting = true;
2279                 snd_soc_jack_report(wm8915->jack, 0,
2280                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2281                 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2282                                     WM8915_MICD_RATE_MASK,
2283                                     WM8915_MICD_RATE_MASK);
2284                 return;
2285         }
2286
2287         /* If the measurement is very high we've got a microphone but
2288          * do a little debounce to account for mechanical issues.
2289          */
2290         if (val & 0x400) {
2291                 dev_dbg(codec->dev, "Microphone detected\n");
2292                 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2293                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2294                 wm8915->jack_mic = true;
2295                 wm8915->detecting = false;
2296         }
2297
2298         /* If we detected a lower impedence during initial startup
2299          * then we probably have the wrong polarity, flip it.  Don't
2300          * do this for the lowest impedences to speed up detection of
2301          * plain headphones.
2302          */
2303         if (wm8915->detecting && (val & 0x3f0)) {
2304                 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2305                 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2306                         WM8915_MICD_BIAS_SRC;
2307                 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2308                                     WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2309                                     WM8915_MICD_BIAS_SRC, reg);
2310
2311                 if (wm8915->polarity_cb)
2312                         wm8915->polarity_cb(codec,
2313                                             (reg & WM8915_MICD_SRC) != 0);
2314
2315                 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2316                         (reg & WM8915_MICD_SRC) != 0);
2317
2318                 return;
2319         }
2320
2321         /* Don't distinguish between buttons, just report any low
2322          * impedence as BTN_0.
2323          */
2324         if (val & 0x3fc) {
2325                 if (wm8915->jack_mic) {
2326                         dev_dbg(codec->dev, "Mic button detected\n");
2327                         snd_soc_jack_report(wm8915->jack,
2328                                             SND_JACK_HEADSET | SND_JACK_BTN_0,
2329                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2330                 } else {
2331                         dev_dbg(codec->dev, "Headphone detected\n");
2332                         snd_soc_jack_report(wm8915->jack,
2333                                             SND_JACK_HEADPHONE,
2334                                             SND_JACK_HEADSET |
2335                                             SND_JACK_BTN_0);
2336                         wm8915->detecting = false;
2337                 }
2338         }
2339
2340         /* Increase poll rate to give better responsiveness for buttons */
2341         if (!wm8915->detecting)
2342                 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2343                                     WM8915_MICD_RATE_MASK,
2344                                     5 << WM8915_MICD_RATE_SHIFT);
2345 }
2346
2347 static irqreturn_t wm8915_irq(int irq, void *data)
2348 {
2349         struct snd_soc_codec *codec = data;
2350         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2351         int irq_val;
2352
2353         irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2354         if (irq_val < 0) {
2355                 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2356                         irq_val);
2357                 return IRQ_NONE;
2358         }
2359         irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2360
2361         if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2362                 dev_dbg(codec->dev, "DC servo IRQ\n");
2363                 complete(&wm8915->dcs_done);
2364         }
2365
2366         if (irq_val & WM8915_FIFOS_ERR_EINT)
2367                 dev_err(codec->dev, "Digital core FIFO error\n");
2368
2369         if (irq_val & WM8915_FLL_LOCK_EINT) {
2370                 dev_dbg(codec->dev, "FLL locked\n");
2371                 complete(&wm8915->fll_lock);
2372         }
2373
2374         if (irq_val & WM8915_MICD_EINT)
2375                 wm8915_micd(codec);
2376
2377         if (irq_val) {
2378                 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2379
2380                 return IRQ_HANDLED;
2381         } else {
2382                 return IRQ_NONE;
2383         }
2384 }
2385
2386 static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2387 {
2388         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2389         struct wm8915_pdata *pdata = &wm8915->pdata;
2390
2391         struct snd_kcontrol_new controls[] = {
2392                 SOC_ENUM_EXT("DSP1 EQ Mode",
2393                              wm8915->retune_mobile_enum,
2394                              wm8915_get_retune_mobile_enum,
2395                              wm8915_put_retune_mobile_enum),
2396                 SOC_ENUM_EXT("DSP2 EQ Mode",
2397                              wm8915->retune_mobile_enum,
2398                              wm8915_get_retune_mobile_enum,
2399                              wm8915_put_retune_mobile_enum),
2400         };
2401         int ret, i, j;
2402         const char **t;
2403
2404         /* We need an array of texts for the enum API but the number
2405          * of texts is likely to be less than the number of
2406          * configurations due to the sample rate dependency of the
2407          * configurations. */
2408         wm8915->num_retune_mobile_texts = 0;
2409         wm8915->retune_mobile_texts = NULL;
2410         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2411                 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2412                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2413                                    wm8915->retune_mobile_texts[j]) == 0)
2414                                 break;
2415                 }
2416
2417                 if (j != wm8915->num_retune_mobile_texts)
2418                         continue;
2419
2420                 /* Expand the array... */
2421                 t = krealloc(wm8915->retune_mobile_texts,
2422                              sizeof(char *) *
2423                              (wm8915->num_retune_mobile_texts + 1),
2424                              GFP_KERNEL);
2425                 if (t == NULL)
2426                         continue;
2427
2428                 /* ...store the new entry... */
2429                 t[wm8915->num_retune_mobile_texts] =
2430                         pdata->retune_mobile_cfgs[i].name;
2431
2432                 /* ...and remember the new version. */
2433                 wm8915->num_retune_mobile_texts++;
2434                 wm8915->retune_mobile_texts = t;
2435         }
2436
2437         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2438                 wm8915->num_retune_mobile_texts);
2439
2440         wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2441         wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2442
2443         ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2444         if (ret != 0)
2445                 dev_err(codec->dev,
2446                         "Failed to add ReTune Mobile controls: %d\n", ret);
2447 }
2448
2449 static int wm8915_probe(struct snd_soc_codec *codec)
2450 {
2451         int ret;
2452         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2453         struct i2c_client *i2c = to_i2c_client(codec->dev);
2454         struct snd_soc_dapm_context *dapm = &codec->dapm;
2455         int i, irq_flags;
2456
2457         wm8915->codec = codec;
2458
2459         init_completion(&wm8915->dcs_done);
2460         init_completion(&wm8915->fll_lock);
2461
2462         dapm->idle_bias_off = true;
2463         dapm->bias_level = SND_SOC_BIAS_OFF;
2464
2465         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2466         if (ret != 0) {
2467                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2468                 goto err;
2469         }
2470
2471         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2472                 wm8915->supplies[i].supply = wm8915_supply_names[i];
2473
2474         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2475                                  wm8915->supplies);
2476         if (ret != 0) {
2477                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2478                 goto err;
2479         }
2480
2481         wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2482         wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2483         wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2484         wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2485         wm8915->disable_nb[4].notifier_call = wm8915_regulator_event_4;
2486         wm8915->disable_nb[5].notifier_call = wm8915_regulator_event_5;
2487
2488         /* This should really be moved into the regulator core */
2489         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2490                 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2491                                                   &wm8915->disable_nb[i]);
2492                 if (ret != 0) {
2493                         dev_err(codec->dev,
2494                                 "Failed to register regulator notifier: %d\n",
2495                                 ret);
2496                 }
2497         }
2498
2499         ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2500                                     wm8915->supplies);
2501         if (ret != 0) {
2502                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2503                 goto err_get;
2504         }
2505
2506         if (wm8915->pdata.ldo_ena >= 0) {
2507                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2508                 msleep(5);
2509         }
2510
2511         ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2512         if (ret < 0) {
2513                 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2514                 goto err_enable;
2515         }
2516         if (ret != 0x8915) {
2517                 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2518                 ret = -EINVAL;
2519                 goto err_enable;
2520         }
2521
2522         ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2523         if (ret < 0) {
2524                 dev_err(codec->dev, "Failed to read device revision: %d\n",
2525                         ret);
2526                 goto err_enable;
2527         }
2528
2529         dev_info(codec->dev, "revision %c\n",
2530                  (ret & WM8915_CHIP_REV_MASK) + 'A');
2531
2532         if (wm8915->pdata.ldo_ena >= 0) {
2533                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2534         } else {
2535                 ret = wm8915_reset(codec);
2536                 if (ret < 0) {
2537                         dev_err(codec->dev, "Failed to issue reset\n");
2538                         goto err_enable;
2539                 }
2540         }
2541
2542         codec->cache_only = true;
2543
2544         /* Apply platform data settings */
2545         snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2546                             WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2547                             wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2548                             wm8915->pdata.inr_mode);
2549
2550         for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2551                 if (!wm8915->pdata.gpio_default[i])
2552                         continue;
2553
2554                 snd_soc_write(codec, WM8915_GPIO_1 + i,
2555                               wm8915->pdata.gpio_default[i] & 0xffff);
2556         }
2557
2558         if (wm8915->pdata.spkmute_seq)
2559                 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2560                                     WM8915_SPK_MUTE_ENDIAN |
2561                                     WM8915_SPK_MUTE_SEQ1_MASK,
2562                                     wm8915->pdata.spkmute_seq);
2563
2564         snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2565                             WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2566                             WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2567
2568         /* Latch volume update bits */
2569         snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2570                             WM8915_IN1_VU, WM8915_IN1_VU);
2571         snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2572                             WM8915_IN1_VU, WM8915_IN1_VU);
2573
2574         snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2575                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2576         snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2577                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2578         snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2579                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2580         snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2581                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2582
2583         snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2584                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2585         snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2586                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2587         snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2588                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2589         snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2590                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2591
2592         snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2593                             WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2594         snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2595                             WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2596         snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2597                             WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2598         snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2599                             WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2600
2601         snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2602                             WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2603         snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2604                             WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2605         snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2606                             WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2607         snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2608                             WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2609
2610         /* No support currently for the underclocked TDM modes and
2611          * pick a default TDM layout with each channel pair working with
2612          * slots 0 and 1. */
2613         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2614                             WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2615                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2616                             1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2617         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2618                             WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2619                             WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2620                             1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2621         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2622                             WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2623                             WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2624                             1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2625         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2626                             WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2627                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2628                             1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2629         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2630                             WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2631                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2632                             1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2633         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2634                             WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2635                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2636                             1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2637
2638         snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2639                             WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2640                             WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2641                             1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2642         snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2643                             WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2644                             WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2645                             1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2646
2647         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2648                             WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2649                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2650                             1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2651         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2652                             WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2653                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2654                             1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2655         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2656                             WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2657                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2658                             1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2659         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2660                             WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2661                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2662                             1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2663         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2664                             WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2665                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2666                             1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2667         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2668                             WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2669                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2670                             1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2671
2672         snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2673                             WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2674                             WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2675                             1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2676         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2677                             WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2678                             WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2679                             1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2680
2681         if (wm8915->pdata.num_retune_mobile_cfgs)
2682                 wm8915_retune_mobile_pdata(codec);
2683         else
2684                 snd_soc_add_controls(codec, wm8915_eq_controls,
2685                                      ARRAY_SIZE(wm8915_eq_controls));
2686
2687         /* If the TX LRCLK pins are not in LRCLK mode configure the
2688          * AIFs to source their clocks from the RX LRCLKs.
2689          */
2690         if ((snd_soc_read(codec, WM8915_GPIO_1)))
2691                 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2692                                     WM8915_AIF1TX_LRCLK_MODE,
2693                                     WM8915_AIF1TX_LRCLK_MODE);
2694
2695         if ((snd_soc_read(codec, WM8915_GPIO_2)))
2696                 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2697                                     WM8915_AIF2TX_LRCLK_MODE,
2698                                     WM8915_AIF2TX_LRCLK_MODE);
2699
2700         regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2701
2702         wm8915_init_gpio(codec);
2703
2704         if (i2c->irq) {
2705                 if (wm8915->pdata.irq_flags)
2706                         irq_flags = wm8915->pdata.irq_flags;
2707                 else
2708                         irq_flags = IRQF_TRIGGER_LOW;
2709
2710                 irq_flags |= IRQF_ONESHOT;
2711
2712                 ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2713                                            irq_flags, "wm8915", codec);
2714                 if (ret == 0) {
2715                         /* Unmask the interrupt */
2716                         snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2717                                             WM8915_IM_IRQ, 0);
2718
2719                         /* Enable error reporting and DC servo status */
2720                         snd_soc_update_bits(codec,
2721                                             WM8915_INTERRUPT_STATUS_2_MASK,
2722                                             WM8915_IM_DCS_DONE_23_EINT |
2723                                             WM8915_IM_DCS_DONE_01_EINT |
2724                                             WM8915_IM_FLL_LOCK_EINT |
2725                                             WM8915_IM_FIFOS_ERR_EINT,
2726                                             0);
2727                 } else {
2728                         dev_err(codec->dev, "Failed to request IRQ: %d\n",
2729                                 ret);
2730                 }
2731         }
2732
2733         return 0;
2734
2735 err_enable:
2736         if (wm8915->pdata.ldo_ena >= 0)
2737                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2738
2739         regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2740 err_get:
2741         regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2742 err:
2743         return ret;
2744 }
2745
2746 static int wm8915_remove(struct snd_soc_codec *codec)
2747 {
2748         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2749         struct i2c_client *i2c = to_i2c_client(codec->dev);
2750         int i;
2751
2752         snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2753                             WM8915_IM_IRQ, WM8915_IM_IRQ);
2754
2755         if (i2c->irq)
2756                 free_irq(i2c->irq, codec);
2757
2758         wm8915_free_gpio(codec);
2759
2760         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2761                 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2762                                               &wm8915->disable_nb[i]);
2763         regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2764
2765         return 0;
2766 }
2767
2768 static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2769         .probe =        wm8915_probe,
2770         .remove =       wm8915_remove,
2771         .set_bias_level = wm8915_set_bias_level,
2772         .seq_notifier = wm8915_seq_notifier,
2773         .reg_cache_size = WM8915_MAX_REGISTER + 1,
2774         .reg_word_size = sizeof(u16),
2775         .reg_cache_default = wm8915_reg,
2776         .volatile_register = wm8915_volatile_register,
2777         .readable_register = wm8915_readable_register,
2778         .compress_type = SND_SOC_RBTREE_COMPRESSION,
2779         .controls = wm8915_snd_controls,
2780         .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2781         .dapm_widgets = wm8915_dapm_widgets,
2782         .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2783         .dapm_routes = wm8915_dapm_routes,
2784         .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
2785         .set_pll = wm8915_set_fll,
2786 };
2787
2788 #define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2789                       SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2790 #define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2791                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2792                         SNDRV_PCM_FMTBIT_S32_LE)
2793
2794 static struct snd_soc_dai_ops wm8915_dai_ops = {
2795         .set_fmt = wm8915_set_fmt,
2796         .hw_params = wm8915_hw_params,
2797         .set_sysclk = wm8915_set_sysclk,
2798 };
2799
2800 static struct snd_soc_dai_driver wm8915_dai[] = {
2801         {
2802                 .name = "wm8915-aif1",
2803                 .playback = {
2804                         .stream_name = "AIF1 Playback",
2805                         .channels_min = 1,
2806                         .channels_max = 6,
2807                         .rates = WM8915_RATES,
2808                         .formats = WM8915_FORMATS,
2809                 },
2810                 .capture = {
2811                          .stream_name = "AIF1 Capture",
2812                          .channels_min = 1,
2813                          .channels_max = 6,
2814                          .rates = WM8915_RATES,
2815                          .formats = WM8915_FORMATS,
2816                  },
2817                 .ops = &wm8915_dai_ops,
2818         },
2819         {
2820                 .name = "wm8915-aif2",
2821                 .playback = {
2822                         .stream_name = "AIF2 Playback",
2823                         .channels_min = 1,
2824                         .channels_max = 2,
2825                         .rates = WM8915_RATES,
2826                         .formats = WM8915_FORMATS,
2827                 },
2828                 .capture = {
2829                          .stream_name = "AIF2 Capture",
2830                          .channels_min = 1,
2831                          .channels_max = 2,
2832                          .rates = WM8915_RATES,
2833                          .formats = WM8915_FORMATS,
2834                  },
2835                 .ops = &wm8915_dai_ops,
2836         },
2837 };
2838
2839 static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2840                                       const struct i2c_device_id *id)
2841 {
2842         struct wm8915_priv *wm8915;
2843         int ret;
2844
2845         wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2846         if (wm8915 == NULL)
2847                 return -ENOMEM;
2848
2849         i2c_set_clientdata(i2c, wm8915);
2850
2851         if (dev_get_platdata(&i2c->dev))
2852                 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2853                        sizeof(wm8915->pdata));
2854
2855         if (wm8915->pdata.ldo_ena > 0) {
2856                 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2857                                        GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2858                 if (ret < 0) {
2859                         dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2860                                 wm8915->pdata.ldo_ena, ret);
2861                         goto err;
2862                 }
2863         }
2864
2865         ret = snd_soc_register_codec(&i2c->dev,
2866                                      &soc_codec_dev_wm8915, wm8915_dai,
2867                                      ARRAY_SIZE(wm8915_dai));
2868         if (ret < 0)
2869                 goto err_gpio;
2870
2871         return ret;
2872
2873 err_gpio:
2874         if (wm8915->pdata.ldo_ena > 0)
2875                 gpio_free(wm8915->pdata.ldo_ena);
2876 err:
2877         kfree(wm8915);
2878
2879         return ret;
2880 }
2881
2882 static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2883 {
2884         struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2885
2886         snd_soc_unregister_codec(&client->dev);
2887         if (wm8915->pdata.ldo_ena > 0)
2888                 gpio_free(wm8915->pdata.ldo_ena);
2889         kfree(i2c_get_clientdata(client));
2890         return 0;
2891 }
2892
2893 static const struct i2c_device_id wm8915_i2c_id[] = {
2894         { "wm8915", 0 },
2895         { }
2896 };
2897 MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2898
2899 static struct i2c_driver wm8915_i2c_driver = {
2900         .driver = {
2901                 .name = "wm8915",
2902                 .owner = THIS_MODULE,
2903         },
2904         .probe =    wm8915_i2c_probe,
2905         .remove =   __devexit_p(wm8915_i2c_remove),
2906         .id_table = wm8915_i2c_id,
2907 };
2908
2909 static int __init wm8915_modinit(void)
2910 {
2911         int ret;
2912
2913         ret = i2c_add_driver(&wm8915_i2c_driver);
2914         if (ret != 0) {
2915                 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2916                        ret);
2917         }
2918
2919         return ret;
2920 }
2921 module_init(wm8915_modinit);
2922
2923 static void __exit wm8915_exit(void)
2924 {
2925         i2c_del_driver(&wm8915_i2c_driver);
2926 }
2927 module_exit(wm8915_exit);
2928
2929 MODULE_DESCRIPTION("ASoC WM8915 driver");
2930 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2931 MODULE_LICENSE("GPL");