2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - TDM mode configuration.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
24 #include <linux/i2c.h>
25 #include <linux/platform_device.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/tlv.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
36 /* Register defaults at reset */
37 static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0001, /* R8 - Analogue DAC 0 */
48 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0010, /* R67 - DC Servo 0 */
107 0x00A4, /* R69 - DC Servo 2 */
128 0x0000, /* R90 - Analogue HP 0 */
132 0x0000, /* R94 - Analogue Lineout 0 */
136 0x0000, /* R98 - Charge Pump 0 */
142 0x0000, /* R104 - Class W 0 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R114 - Control Interface */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
164 0x0000, /* R126 - Interrupt Control */
167 0x0000, /* R129 - Control Interface Test 1 */
187 0x6810, /* R149 - Charge Pump Test 1 */
202 0x0028, /* R164 - Clock Rate Test 4 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
219 /* Reference counts */
224 struct snd_pcm_substream *master_substream;
225 struct snd_pcm_substream *slave_substream;
229 static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
232 u16 *cache = codec->reg_cache;
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
239 static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
241 struct i2c_msg xfer[2];
244 struct i2c_client *client = codec->control_data;
247 xfer[0].addr = client->addr;
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
256 xfer[1].buf = (u8 *)&data;
258 ret = i2c_transfer(client->adapter, xfer, 2);
260 pr_err("i2c_transfer returned %d\n", ret);
264 return (data >> 8) | ((data & 0xff) << 8);
267 static unsigned int wm8903_read(struct snd_soc_codec *codec,
271 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg);
278 return wm8903_read_reg_cache(codec, reg);
282 static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
285 u16 *cache = codec->reg_cache;
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
300 static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
305 wm8903_write_reg_cache(codec, reg, value);
307 /* Data format is 1 byte of address followed by 2 bytes of data */
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
318 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
321 struct i2c_client *i2c = codec->control_data;
325 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START);
335 /* Wait for it to complete. If we have the interrupt wired up then
336 * we could block waiting for an interrupt, though polling may still
337 * be desirable for diagnostic purposes.
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY);
345 dev_dbg(&i2c->dev, "Sequence complete\n");
347 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA);
354 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
358 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i);
363 static void wm8903_reset(struct snd_soc_codec *codec)
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
366 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults));
370 #define WM8903_OUTPUT_SHORT 0x8
371 #define WM8903_OUTPUT_OUT 0x4
372 #define WM8903_OUTPUT_INT 0x2
373 #define WM8903_OUTPUT_IN 0x1
375 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
378 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
385 * Event for headphone and line out amplifier power changes. Special
386 * power up/down sequences are required in order to maximise pop/click
389 static int wm8903_output_event(struct snd_soc_dapm_widget *w,
390 struct snd_kcontrol *kcontrol, int event)
392 struct snd_soc_codec *codec = w->codec;
398 case WM8903_POWER_MANAGEMENT_2:
399 reg = WM8903_ANALOGUE_HP_0;
401 case WM8903_POWER_MANAGEMENT_3:
402 reg = WM8903_ANALOGUE_LINEOUT_0;
406 return -EINVAL; /* Spurious warning from some compilers */
418 return -EINVAL; /* Spurious warning from some compilers */
421 if (event & SND_SOC_DAPM_PRE_PMU) {
422 val = wm8903_read(codec, reg);
424 /* Short the output */
425 val &= ~(WM8903_OUTPUT_SHORT << shift);
426 wm8903_write(codec, reg, val);
429 if (event & SND_SOC_DAPM_POST_PMU) {
430 val = wm8903_read(codec, reg);
432 val |= (WM8903_OUTPUT_IN << shift);
433 wm8903_write(codec, reg, val);
435 val |= (WM8903_OUTPUT_INT << shift);
436 wm8903_write(codec, reg, val);
438 /* Turn on the output ENA_OUTP */
439 val |= (WM8903_OUTPUT_OUT << shift);
440 wm8903_write(codec, reg, val);
442 /* Remove the short */
443 val |= (WM8903_OUTPUT_SHORT << shift);
444 wm8903_write(codec, reg, val);
447 if (event & SND_SOC_DAPM_PRE_PMD) {
448 val = wm8903_read(codec, reg);
450 /* Short the output */
451 val &= ~(WM8903_OUTPUT_SHORT << shift);
452 wm8903_write(codec, reg, val);
454 /* Then disable the intermediate and output stages */
455 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
456 WM8903_OUTPUT_IN) << shift);
457 wm8903_write(codec, reg, val);
464 * When used with DAC outputs only the WM8903 charge pump supports
465 * operation in class W mode, providing very low power consumption
466 * when used with digital sources. Enable and disable this mode
467 * automatically depending on the mixer configuration.
469 * All the relevant controls are simple switches.
471 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
474 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
475 struct snd_soc_codec *codec = widget->codec;
476 struct wm8903_priv *wm8903 = codec->private_data;
477 struct i2c_client *i2c = codec->control_data;
481 reg = wm8903_read(codec, WM8903_CLASS_W_0);
483 /* Turn it off if we're about to enable bypass */
484 if (ucontrol->value.integer.value[0]) {
485 if (wm8903->class_w_users == 0) {
486 dev_dbg(&i2c->dev, "Disabling Class W\n");
487 wm8903_write(codec, WM8903_CLASS_W_0, reg &
488 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
490 wm8903->class_w_users++;
493 /* Implement the change */
494 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
496 /* If we've just disabled the last bypass path turn Class W on */
497 if (!ucontrol->value.integer.value[0]) {
498 if (wm8903->class_w_users == 1) {
499 dev_dbg(&i2c->dev, "Enabling Class W\n");
500 wm8903_write(codec, WM8903_CLASS_W_0, reg |
501 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
503 wm8903->class_w_users--;
506 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
507 wm8903->class_w_users);
512 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
513 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
514 .info = snd_soc_info_volsw, \
515 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
516 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
519 /* ALSA can only do steps of .01dB */
520 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
522 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
524 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
525 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
526 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
527 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
528 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
530 static const char *drc_slope_text[] = {
531 "1", "1/2", "1/4", "1/8", "1/16", "0"
534 static const struct soc_enum drc_slope_r0 =
535 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
537 static const struct soc_enum drc_slope_r1 =
538 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
540 static const char *drc_attack_text[] = {
542 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
543 "46.4ms", "92.8ms", "185.6ms"
546 static const struct soc_enum drc_attack =
547 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
549 static const char *drc_decay_text[] = {
550 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
554 static const struct soc_enum drc_decay =
555 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
557 static const char *drc_ff_delay_text[] = {
558 "5 samples", "9 samples"
561 static const struct soc_enum drc_ff_delay =
562 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
564 static const char *drc_qr_decay_text[] = {
565 "0.725ms", "1.45ms", "5.8ms"
568 static const struct soc_enum drc_qr_decay =
569 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
571 static const char *drc_smoothing_text[] = {
572 "Low", "Medium", "High"
575 static const struct soc_enum drc_smoothing =
576 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
578 static const char *soft_mute_text[] = {
579 "Fast (fs/2)", "Slow (fs/32)"
582 static const struct soc_enum soft_mute =
583 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
585 static const char *mute_mode_text[] = {
589 static const struct soc_enum mute_mode =
590 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
592 static const char *dac_deemphasis_text[] = {
593 "Disabled", "32kHz", "44.1kHz", "48kHz"
596 static const struct soc_enum dac_deemphasis =
597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
599 static const char *companding_text[] = {
603 static const struct soc_enum dac_companding =
604 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
606 static const struct soc_enum adc_companding =
607 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
609 static const char *input_mode_text[] = {
610 "Single-Ended", "Differential Line", "Differential Mic"
613 static const struct soc_enum linput_mode_enum =
614 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
616 static const struct soc_enum rinput_mode_enum =
617 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
619 static const char *linput_mux_text[] = {
620 "IN1L", "IN2L", "IN3L"
623 static const struct soc_enum linput_enum =
624 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
626 static const struct soc_enum linput_inv_enum =
627 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
629 static const char *rinput_mux_text[] = {
630 "IN1R", "IN2R", "IN3R"
633 static const struct soc_enum rinput_enum =
634 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
636 static const struct soc_enum rinput_inv_enum =
637 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
640 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
642 /* Input PGAs - No TLV since the scale depends on PGA mode */
643 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
645 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
647 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
650 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
652 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
654 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
658 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
659 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
660 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
661 SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
663 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
664 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
665 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
666 SOC_ENUM("DRC Attack Rate", drc_attack),
667 SOC_ENUM("DRC Decay Rate", drc_decay),
668 SOC_ENUM("DRC FF Delay", drc_ff_delay),
669 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
670 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
671 SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
672 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
673 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
674 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
675 SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
676 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
678 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
679 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
680 SOC_ENUM("ADC Companding Mode", adc_companding),
681 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
684 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
685 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
686 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
687 SOC_ENUM("DAC Mute Mode", mute_mode),
688 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
689 SOC_ENUM("DAC De-emphasis", dac_deemphasis),
690 SOC_SINGLE("DAC Sloping Stopband Filter Switch",
691 WM8903_DAC_DIGITAL_1, 11, 1, 0),
692 SOC_ENUM("DAC Companding Mode", dac_companding),
693 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
696 SOC_DOUBLE_R("Headphone Switch",
697 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
699 SOC_DOUBLE_R("Headphone ZC Switch",
700 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
702 SOC_DOUBLE_R_TLV("Headphone Volume",
703 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
707 SOC_DOUBLE_R("Line Out Switch",
708 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
710 SOC_DOUBLE_R("Line Out ZC Switch",
711 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
713 SOC_DOUBLE_R_TLV("Line Out Volume",
714 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
718 SOC_DOUBLE_R("Speaker Switch",
719 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
720 SOC_DOUBLE_R("Speaker ZC Switch",
721 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
722 SOC_DOUBLE_R_TLV("Speaker Volume",
723 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
727 static const struct snd_kcontrol_new linput_mode_mux =
728 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
730 static const struct snd_kcontrol_new rinput_mode_mux =
731 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
733 static const struct snd_kcontrol_new linput_mux =
734 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
736 static const struct snd_kcontrol_new linput_inv_mux =
737 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
739 static const struct snd_kcontrol_new rinput_mux =
740 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
742 static const struct snd_kcontrol_new rinput_inv_mux =
743 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
745 static const struct snd_kcontrol_new left_output_mixer[] = {
746 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
747 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
748 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
749 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
752 static const struct snd_kcontrol_new right_output_mixer[] = {
753 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
754 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
755 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
756 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
759 static const struct snd_kcontrol_new left_speaker_mixer[] = {
760 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
761 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
762 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
763 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
767 static const struct snd_kcontrol_new right_speaker_mixer[] = {
768 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
769 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
770 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
772 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
776 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
777 SND_SOC_DAPM_INPUT("IN1L"),
778 SND_SOC_DAPM_INPUT("IN1R"),
779 SND_SOC_DAPM_INPUT("IN2L"),
780 SND_SOC_DAPM_INPUT("IN2R"),
781 SND_SOC_DAPM_INPUT("IN3L"),
782 SND_SOC_DAPM_INPUT("IN3R"),
784 SND_SOC_DAPM_OUTPUT("HPOUTL"),
785 SND_SOC_DAPM_OUTPUT("HPOUTR"),
786 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
787 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
788 SND_SOC_DAPM_OUTPUT("LOP"),
789 SND_SOC_DAPM_OUTPUT("LON"),
790 SND_SOC_DAPM_OUTPUT("ROP"),
791 SND_SOC_DAPM_OUTPUT("RON"),
793 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
795 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
796 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
798 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
800 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
801 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
803 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
805 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
806 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
808 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
809 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
811 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
812 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
814 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
815 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
816 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
817 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
819 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
820 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
821 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
822 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
824 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
825 1, 0, NULL, 0, wm8903_output_event,
826 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
827 SND_SOC_DAPM_PRE_PMD),
828 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
829 0, 0, NULL, 0, wm8903_output_event,
830 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
831 SND_SOC_DAPM_PRE_PMD),
833 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
834 NULL, 0, wm8903_output_event,
835 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
836 SND_SOC_DAPM_PRE_PMD),
837 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
838 NULL, 0, wm8903_output_event,
839 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
840 SND_SOC_DAPM_PRE_PMD),
842 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
844 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
847 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
848 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
849 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
852 static const struct snd_soc_dapm_route intercon[] = {
854 { "Left Input Mux", "IN1L", "IN1L" },
855 { "Left Input Mux", "IN2L", "IN2L" },
856 { "Left Input Mux", "IN3L", "IN3L" },
858 { "Left Input Inverting Mux", "IN1L", "IN1L" },
859 { "Left Input Inverting Mux", "IN2L", "IN2L" },
860 { "Left Input Inverting Mux", "IN3L", "IN3L" },
862 { "Right Input Mux", "IN1R", "IN1R" },
863 { "Right Input Mux", "IN2R", "IN2R" },
864 { "Right Input Mux", "IN3R", "IN3R" },
866 { "Right Input Inverting Mux", "IN1R", "IN1R" },
867 { "Right Input Inverting Mux", "IN2R", "IN2R" },
868 { "Right Input Inverting Mux", "IN3R", "IN3R" },
870 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
871 { "Left Input Mode Mux", "Differential Line",
873 { "Left Input Mode Mux", "Differential Line",
874 "Left Input Inverting Mux" },
875 { "Left Input Mode Mux", "Differential Mic",
877 { "Left Input Mode Mux", "Differential Mic",
878 "Left Input Inverting Mux" },
880 { "Right Input Mode Mux", "Single-Ended",
881 "Right Input Inverting Mux" },
882 { "Right Input Mode Mux", "Differential Line",
884 { "Right Input Mode Mux", "Differential Line",
885 "Right Input Inverting Mux" },
886 { "Right Input Mode Mux", "Differential Mic",
888 { "Right Input Mode Mux", "Differential Mic",
889 "Right Input Inverting Mux" },
891 { "Left Input PGA", NULL, "Left Input Mode Mux" },
892 { "Right Input PGA", NULL, "Right Input Mode Mux" },
894 { "ADCL", NULL, "Left Input PGA" },
895 { "ADCL", NULL, "CLK_DSP" },
896 { "ADCR", NULL, "Right Input PGA" },
897 { "ADCR", NULL, "CLK_DSP" },
899 { "DACL", NULL, "CLK_DSP" },
900 { "DACR", NULL, "CLK_DSP" },
902 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
903 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
904 { "Left Output Mixer", "DACL Switch", "DACL" },
905 { "Left Output Mixer", "DACR Switch", "DACR" },
907 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
908 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
909 { "Right Output Mixer", "DACL Switch", "DACL" },
910 { "Right Output Mixer", "DACR Switch", "DACR" },
912 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
913 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
914 { "Left Speaker Mixer", "DACL Switch", "DACL" },
915 { "Left Speaker Mixer", "DACR Switch", "DACR" },
917 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
918 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
919 { "Right Speaker Mixer", "DACL Switch", "DACL" },
920 { "Right Speaker Mixer", "DACR Switch", "DACR" },
922 { "Left Line Output PGA", NULL, "Left Output Mixer" },
923 { "Right Line Output PGA", NULL, "Right Output Mixer" },
925 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
926 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
928 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
929 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
931 { "HPOUTL", NULL, "Left Headphone Output PGA" },
932 { "HPOUTR", NULL, "Right Headphone Output PGA" },
934 { "LINEOUTL", NULL, "Left Line Output PGA" },
935 { "LINEOUTR", NULL, "Right Line Output PGA" },
937 { "LOP", NULL, "Left Speaker PGA" },
938 { "LON", NULL, "Left Speaker PGA" },
940 { "ROP", NULL, "Right Speaker PGA" },
941 { "RON", NULL, "Right Speaker PGA" },
943 { "Left Headphone Output PGA", NULL, "Charge Pump" },
944 { "Right Headphone Output PGA", NULL, "Charge Pump" },
945 { "Left Line Output PGA", NULL, "Charge Pump" },
946 { "Right Line Output PGA", NULL, "Charge Pump" },
949 static int wm8903_add_widgets(struct snd_soc_codec *codec)
951 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
952 ARRAY_SIZE(wm8903_dapm_widgets));
954 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
956 snd_soc_dapm_new_widgets(codec);
961 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
962 enum snd_soc_bias_level level)
964 struct i2c_client *i2c = codec->control_data;
968 case SND_SOC_BIAS_ON:
969 case SND_SOC_BIAS_PREPARE:
970 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
971 reg &= ~(WM8903_VMID_RES_MASK);
972 reg |= WM8903_VMID_RES_50K;
973 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
976 case SND_SOC_BIAS_STANDBY:
977 if (codec->bias_level == SND_SOC_BIAS_OFF) {
978 wm8903_write(codec, WM8903_CLOCK_RATES_2,
981 /* Change DC servo dither level in startup sequence */
982 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
983 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
984 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
986 wm8903_run_sequence(codec, 0);
987 wm8903_sync_reg_cache(codec, codec->reg_cache);
989 /* Enable low impedence charge pump output */
990 reg = wm8903_read(codec,
991 WM8903_CONTROL_INTERFACE_TEST_1);
992 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
993 reg | WM8903_TEST_KEY);
994 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
995 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
996 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
997 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1000 /* By default no bypass paths are enabled so
1001 * enable Class W support.
1003 dev_dbg(&i2c->dev, "Enabling Class W\n");
1004 wm8903_write(codec, WM8903_CLASS_W_0, reg |
1005 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1008 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1009 reg &= ~(WM8903_VMID_RES_MASK);
1010 reg |= WM8903_VMID_RES_250K;
1011 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1014 case SND_SOC_BIAS_OFF:
1015 wm8903_run_sequence(codec, 32);
1016 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1017 reg &= ~WM8903_CLK_SYS_ENA;
1018 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
1022 codec->bias_level = level;
1027 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1028 int clk_id, unsigned int freq, int dir)
1030 struct snd_soc_codec *codec = codec_dai->codec;
1031 struct wm8903_priv *wm8903 = codec->private_data;
1033 wm8903->sysclk = freq;
1038 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1041 struct snd_soc_codec *codec = codec_dai->codec;
1042 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1044 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1045 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1047 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1048 case SND_SOC_DAIFMT_CBS_CFS:
1050 case SND_SOC_DAIFMT_CBS_CFM:
1051 aif1 |= WM8903_LRCLK_DIR;
1053 case SND_SOC_DAIFMT_CBM_CFM:
1054 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1056 case SND_SOC_DAIFMT_CBM_CFS:
1057 aif1 |= WM8903_BCLK_DIR;
1063 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1064 case SND_SOC_DAIFMT_DSP_A:
1067 case SND_SOC_DAIFMT_DSP_B:
1068 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1070 case SND_SOC_DAIFMT_I2S:
1073 case SND_SOC_DAIFMT_RIGHT_J:
1076 case SND_SOC_DAIFMT_LEFT_J:
1082 /* Clock inversion */
1083 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1084 case SND_SOC_DAIFMT_DSP_A:
1085 case SND_SOC_DAIFMT_DSP_B:
1086 /* frame inversion not valid for DSP modes */
1087 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1088 case SND_SOC_DAIFMT_NB_NF:
1090 case SND_SOC_DAIFMT_IB_NF:
1091 aif1 |= WM8903_AIF_BCLK_INV;
1097 case SND_SOC_DAIFMT_I2S:
1098 case SND_SOC_DAIFMT_RIGHT_J:
1099 case SND_SOC_DAIFMT_LEFT_J:
1100 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1101 case SND_SOC_DAIFMT_NB_NF:
1103 case SND_SOC_DAIFMT_IB_IF:
1104 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1106 case SND_SOC_DAIFMT_IB_NF:
1107 aif1 |= WM8903_AIF_BCLK_INV;
1109 case SND_SOC_DAIFMT_NB_IF:
1110 aif1 |= WM8903_AIF_LRCLK_INV;
1120 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1125 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1127 struct snd_soc_codec *codec = codec_dai->codec;
1130 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1133 reg |= WM8903_DAC_MUTE;
1135 reg &= ~WM8903_DAC_MUTE;
1137 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1142 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1143 * for optimal performance so we list the lower rates first and match
1144 * on the last match we find. */
1150 } clk_sys_ratios[] = {
1151 { 64, 0x0, 0x0, 1 },
1152 { 68, 0x0, 0x1, 1 },
1153 { 125, 0x0, 0x2, 1 },
1154 { 128, 0x1, 0x0, 1 },
1155 { 136, 0x1, 0x1, 1 },
1156 { 192, 0x2, 0x0, 1 },
1157 { 204, 0x2, 0x1, 1 },
1159 { 64, 0x0, 0x0, 2 },
1160 { 68, 0x0, 0x1, 2 },
1161 { 125, 0x0, 0x2, 2 },
1162 { 128, 0x1, 0x0, 2 },
1163 { 136, 0x1, 0x1, 2 },
1164 { 192, 0x2, 0x0, 2 },
1165 { 204, 0x2, 0x1, 2 },
1167 { 250, 0x2, 0x2, 1 },
1168 { 256, 0x3, 0x0, 1 },
1169 { 272, 0x3, 0x1, 1 },
1170 { 384, 0x4, 0x0, 1 },
1171 { 408, 0x4, 0x1, 1 },
1172 { 375, 0x4, 0x2, 1 },
1173 { 512, 0x5, 0x0, 1 },
1174 { 544, 0x5, 0x1, 1 },
1175 { 500, 0x5, 0x2, 1 },
1176 { 768, 0x6, 0x0, 1 },
1177 { 816, 0x6, 0x1, 1 },
1178 { 750, 0x6, 0x2, 1 },
1179 { 1024, 0x7, 0x0, 1 },
1180 { 1088, 0x7, 0x1, 1 },
1181 { 1000, 0x7, 0x2, 1 },
1182 { 1408, 0x8, 0x0, 1 },
1183 { 1496, 0x8, 0x1, 1 },
1184 { 1536, 0x9, 0x0, 1 },
1185 { 1632, 0x9, 0x1, 1 },
1186 { 1500, 0x9, 0x2, 1 },
1188 { 250, 0x2, 0x2, 2 },
1189 { 256, 0x3, 0x0, 2 },
1190 { 272, 0x3, 0x1, 2 },
1191 { 384, 0x4, 0x0, 2 },
1192 { 408, 0x4, 0x1, 2 },
1193 { 375, 0x4, 0x2, 2 },
1194 { 512, 0x5, 0x0, 2 },
1195 { 544, 0x5, 0x1, 2 },
1196 { 500, 0x5, 0x2, 2 },
1197 { 768, 0x6, 0x0, 2 },
1198 { 816, 0x6, 0x1, 2 },
1199 { 750, 0x6, 0x2, 2 },
1200 { 1024, 0x7, 0x0, 2 },
1201 { 1088, 0x7, 0x1, 2 },
1202 { 1000, 0x7, 0x2, 2 },
1203 { 1408, 0x8, 0x0, 2 },
1204 { 1496, 0x8, 0x1, 2 },
1205 { 1536, 0x9, 0x0, 2 },
1206 { 1632, 0x9, 0x1, 2 },
1207 { 1500, 0x9, 0x2, 2 },
1210 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1238 /* Sample rates for DSP */
1242 } sample_rates[] = {
1257 static int wm8903_startup(struct snd_pcm_substream *substream,
1258 struct snd_soc_dai *dai)
1260 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1261 struct snd_soc_device *socdev = rtd->socdev;
1262 struct snd_soc_codec *codec = socdev->card->codec;
1263 struct wm8903_priv *wm8903 = codec->private_data;
1264 struct i2c_client *i2c = codec->control_data;
1265 struct snd_pcm_runtime *master_runtime;
1267 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1268 wm8903->playback_active++;
1270 wm8903->capture_active++;
1272 /* The DAI has shared clocks so if we already have a playback or
1273 * capture going then constrain this substream to match it.
1275 if (wm8903->master_substream) {
1276 master_runtime = wm8903->master_substream->runtime;
1278 dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
1279 master_runtime->sample_bits,
1280 master_runtime->rate);
1282 snd_pcm_hw_constraint_minmax(substream->runtime,
1283 SNDRV_PCM_HW_PARAM_RATE,
1284 master_runtime->rate,
1285 master_runtime->rate);
1287 snd_pcm_hw_constraint_minmax(substream->runtime,
1288 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1289 master_runtime->sample_bits,
1290 master_runtime->sample_bits);
1292 wm8903->slave_substream = substream;
1294 wm8903->master_substream = substream;
1299 static void wm8903_shutdown(struct snd_pcm_substream *substream,
1300 struct snd_soc_dai *dai)
1302 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1303 struct snd_soc_device *socdev = rtd->socdev;
1304 struct snd_soc_codec *codec = socdev->card->codec;
1305 struct wm8903_priv *wm8903 = codec->private_data;
1307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1308 wm8903->playback_active--;
1310 wm8903->capture_active--;
1312 if (wm8903->master_substream == substream)
1313 wm8903->master_substream = wm8903->slave_substream;
1315 wm8903->slave_substream = NULL;
1318 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1319 struct snd_pcm_hw_params *params,
1320 struct snd_soc_dai *dai)
1322 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1323 struct snd_soc_device *socdev = rtd->socdev;
1324 struct snd_soc_codec *codec = socdev->card->codec;
1325 struct wm8903_priv *wm8903 = codec->private_data;
1326 struct i2c_client *i2c = codec->control_data;
1327 int fs = params_rate(params);
1337 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1338 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1339 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1340 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1341 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1343 if (substream == wm8903->slave_substream) {
1344 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1348 /* Configure sample rate logic for DSP - choose nearest rate */
1350 best_val = abs(sample_rates[dsp_config].rate - fs);
1351 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1352 cur_val = abs(sample_rates[i].rate - fs);
1353 if (cur_val <= best_val) {
1359 /* Constraints should stop us hitting this but let's make sure */
1360 if (wm8903->capture_active)
1361 switch (sample_rates[dsp_config].rate) {
1364 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1372 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1373 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1374 clock1 |= sample_rates[dsp_config].value;
1376 aif1 &= ~WM8903_AIF_WL_MASK;
1378 switch (params_format(params)) {
1379 case SNDRV_PCM_FORMAT_S16_LE:
1382 case SNDRV_PCM_FORMAT_S20_3LE:
1386 case SNDRV_PCM_FORMAT_S24_LE:
1390 case SNDRV_PCM_FORMAT_S32_LE:
1398 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1399 wm8903->sysclk, fs);
1401 /* We may not have an MCLK which allows us to generate exactly
1402 * the clock we want, particularly with USB derived inputs, so
1406 best_val = abs((wm8903->sysclk /
1407 (clk_sys_ratios[0].mclk_div *
1408 clk_sys_ratios[0].div)) - fs);
1409 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1410 cur_val = abs((wm8903->sysclk /
1411 (clk_sys_ratios[i].mclk_div *
1412 clk_sys_ratios[i].div)) - fs);
1414 if (cur_val <= best_val) {
1420 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1421 clock0 |= WM8903_MCLKDIV2;
1422 clk_sys = wm8903->sysclk / 2;
1424 clock0 &= ~WM8903_MCLKDIV2;
1425 clk_sys = wm8903->sysclk;
1428 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1429 WM8903_CLK_SYS_MODE_MASK);
1430 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1431 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1433 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1434 clk_sys_ratios[clk_config].rate,
1435 clk_sys_ratios[clk_config].mode,
1436 clk_sys_ratios[clk_config].div);
1438 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1440 /* We may not get quite the right frequency if using
1441 * approximate clocks so look for the closest match that is
1442 * higher than the target (we need to ensure that there enough
1443 * BCLKs to clock out the samples).
1446 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1448 while (i < ARRAY_SIZE(bclk_divs)) {
1449 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1450 if (cur_val < 0) /* BCLK table is sorted */
1457 aif2 &= ~WM8903_BCLK_DIV_MASK;
1458 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1460 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1461 bclk_divs[bclk_div].ratio / 10, bclk,
1462 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1464 aif2 |= bclk_divs[bclk_div].div;
1467 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1468 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1469 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1470 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1471 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1476 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1477 SNDRV_PCM_RATE_11025 | \
1478 SNDRV_PCM_RATE_16000 | \
1479 SNDRV_PCM_RATE_22050 | \
1480 SNDRV_PCM_RATE_32000 | \
1481 SNDRV_PCM_RATE_44100 | \
1482 SNDRV_PCM_RATE_48000 | \
1483 SNDRV_PCM_RATE_88200 | \
1484 SNDRV_PCM_RATE_96000)
1486 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1487 SNDRV_PCM_RATE_11025 | \
1488 SNDRV_PCM_RATE_16000 | \
1489 SNDRV_PCM_RATE_22050 | \
1490 SNDRV_PCM_RATE_32000 | \
1491 SNDRV_PCM_RATE_44100 | \
1492 SNDRV_PCM_RATE_48000)
1494 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1495 SNDRV_PCM_FMTBIT_S20_3LE |\
1496 SNDRV_PCM_FMTBIT_S24_LE)
1498 static struct snd_soc_dai_ops wm8903_dai_ops = {
1499 .startup = wm8903_startup,
1500 .shutdown = wm8903_shutdown,
1501 .hw_params = wm8903_hw_params,
1502 .digital_mute = wm8903_digital_mute,
1503 .set_fmt = wm8903_set_dai_fmt,
1504 .set_sysclk = wm8903_set_dai_sysclk,
1507 struct snd_soc_dai wm8903_dai = {
1510 .stream_name = "Playback",
1513 .rates = WM8903_PLAYBACK_RATES,
1514 .formats = WM8903_FORMATS,
1517 .stream_name = "Capture",
1520 .rates = WM8903_CAPTURE_RATES,
1521 .formats = WM8903_FORMATS,
1523 .ops = &wm8903_dai_ops,
1524 .symmetric_rates = 1,
1526 EXPORT_SYMBOL_GPL(wm8903_dai);
1528 static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1530 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1531 struct snd_soc_codec *codec = socdev->card->codec;
1533 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1538 static int wm8903_resume(struct platform_device *pdev)
1540 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1541 struct snd_soc_codec *codec = socdev->card->codec;
1542 struct i2c_client *i2c = codec->control_data;
1544 u16 *reg_cache = codec->reg_cache;
1545 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1548 /* Bring the codec back up to standby first to minimise pop/clicks */
1549 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1550 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1552 /* Sync back everything else */
1554 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1555 if (tmp_cache[i] != reg_cache[i])
1556 wm8903_write(codec, i, tmp_cache[i]);
1558 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1564 static struct snd_soc_codec *wm8903_codec;
1566 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1567 const struct i2c_device_id *id)
1569 struct wm8903_priv *wm8903;
1570 struct snd_soc_codec *codec;
1574 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1578 codec = &wm8903->codec;
1580 mutex_init(&codec->mutex);
1581 INIT_LIST_HEAD(&codec->dapm_widgets);
1582 INIT_LIST_HEAD(&codec->dapm_paths);
1584 codec->dev = &i2c->dev;
1585 codec->name = "WM8903";
1586 codec->owner = THIS_MODULE;
1587 codec->read = wm8903_read;
1588 codec->write = wm8903_write;
1589 codec->hw_write = (hw_write_t)i2c_master_send;
1590 codec->bias_level = SND_SOC_BIAS_OFF;
1591 codec->set_bias_level = wm8903_set_bias_level;
1592 codec->dai = &wm8903_dai;
1594 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1595 codec->reg_cache = &wm8903->reg_cache[0];
1596 codec->private_data = wm8903;
1598 i2c_set_clientdata(i2c, codec);
1599 codec->control_data = i2c;
1601 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1602 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1604 "Device with ID register %x is not a WM8903\n", val);
1608 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1609 dev_info(&i2c->dev, "WM8903 revision %d\n",
1610 val & WM8903_CHIP_REV_MASK);
1612 wm8903_reset(codec);
1614 /* power on device */
1615 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1617 /* Latch volume update bits */
1618 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1619 val |= WM8903_ADCVU;
1620 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1621 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1623 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1624 val |= WM8903_DACVU;
1625 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1626 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1628 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1629 val |= WM8903_HPOUTVU;
1630 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1631 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1633 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1634 val |= WM8903_LINEOUTVU;
1635 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1636 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1638 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1639 val |= WM8903_SPKVU;
1640 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1641 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1643 /* Enable DAC soft mute by default */
1644 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1645 val |= WM8903_DAC_MUTEMODE;
1646 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1648 wm8903_dai.dev = &i2c->dev;
1649 wm8903_codec = codec;
1651 ret = snd_soc_register_codec(codec);
1653 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1657 ret = snd_soc_register_dai(&wm8903_dai);
1659 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1666 snd_soc_unregister_codec(codec);
1668 wm8903_codec = NULL;
1673 static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1675 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1677 snd_soc_unregister_dai(&wm8903_dai);
1678 snd_soc_unregister_codec(codec);
1680 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1682 kfree(codec->private_data);
1684 wm8903_codec = NULL;
1685 wm8903_dai.dev = NULL;
1690 /* i2c codec control layer */
1691 static const struct i2c_device_id wm8903_i2c_id[] = {
1695 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1697 static struct i2c_driver wm8903_i2c_driver = {
1700 .owner = THIS_MODULE,
1702 .probe = wm8903_i2c_probe,
1703 .remove = __devexit_p(wm8903_i2c_remove),
1704 .id_table = wm8903_i2c_id,
1707 static int wm8903_probe(struct platform_device *pdev)
1709 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1712 if (!wm8903_codec) {
1713 dev_err(&pdev->dev, "I2C device not yet probed\n");
1717 socdev->card->codec = wm8903_codec;
1720 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1722 dev_err(&pdev->dev, "failed to create pcms\n");
1726 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
1727 ARRAY_SIZE(wm8903_snd_controls));
1728 wm8903_add_widgets(socdev->card->codec);
1730 ret = snd_soc_init_card(socdev);
1732 dev_err(&pdev->dev, "wm8903: failed to register card\n");
1739 snd_soc_free_pcms(socdev);
1740 snd_soc_dapm_free(socdev);
1745 /* power down chip */
1746 static int wm8903_remove(struct platform_device *pdev)
1748 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1749 struct snd_soc_codec *codec = socdev->card->codec;
1751 if (codec->control_data)
1752 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1754 snd_soc_free_pcms(socdev);
1755 snd_soc_dapm_free(socdev);
1760 struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1761 .probe = wm8903_probe,
1762 .remove = wm8903_remove,
1763 .suspend = wm8903_suspend,
1764 .resume = wm8903_resume,
1766 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1768 static int __init wm8903_modinit(void)
1770 return i2c_add_driver(&wm8903_i2c_driver);
1772 module_init(wm8903_modinit);
1774 static void __exit wm8903_exit(void)
1776 i2c_del_driver(&wm8903_i2c_driver);
1778 module_exit(wm8903_exit);
1780 MODULE_DESCRIPTION("ASoC WM8903 driver");
1781 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1782 MODULE_LICENSE("GPL");