sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/soc-dapm.h>
  34 #include <sound/tlv.h>
  35 #include <sound/initval.h>
  36 #include <asm/div64.h>
  37
  38 #include "wm8580.h"
  39
  40 /* WM8580 register space */
  41 #define WM8580_PLLA1                         0x00
  42 #define WM8580_PLLA2                         0x01
  43 #define WM8580_PLLA3                         0x02
  44 #define WM8580_PLLA4                         0x03
  45 #define WM8580_PLLB1                         0x04
  46 #define WM8580_PLLB2                         0x05
  47 #define WM8580_PLLB3                         0x06
  48 #define WM8580_PLLB4                         0x07
  49 #define WM8580_CLKSEL                        0x08
  50 #define WM8580_PAIF1                         0x09
  51 #define WM8580_PAIF2                         0x0A
  52 #define WM8580_SAIF1                         0x0B
  53 #define WM8580_PAIF3                         0x0C
  54 #define WM8580_PAIF4                         0x0D
  55 #define WM8580_SAIF2                         0x0E
  56 #define WM8580_DAC_CONTROL1                  0x0F
  57 #define WM8580_DAC_CONTROL2                  0x10
  58 #define WM8580_DAC_CONTROL3                  0x11
  59 #define WM8580_DAC_CONTROL4                  0x12
  60 #define WM8580_DAC_CONTROL5                  0x13
  61 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  62 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  63 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  64 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  65 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  66 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  67 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  68 #define WM8580_ADC_CONTROL1                  0x1D
  69 #define WM8580_SPDTXCHAN0                    0x1E
  70 #define WM8580_SPDTXCHAN1                    0x1F
  71 #define WM8580_SPDTXCHAN2                    0x20
  72 #define WM8580_SPDTXCHAN3                    0x21
  73 #define WM8580_SPDTXCHAN4                    0x22
  74 #define WM8580_SPDTXCHAN5                    0x23
  75 #define WM8580_SPDMODE                       0x24
  76 #define WM8580_INTMASK                       0x25
  77 #define WM8580_GPO1                          0x26
  78 #define WM8580_GPO2                          0x27
  79 #define WM8580_GPO3                          0x28
  80 #define WM8580_GPO4                          0x29
  81 #define WM8580_GPO5                          0x2A
  82 #define WM8580_INTSTAT                       0x2B
  83 #define WM8580_SPDRXCHAN1                    0x2C
  84 #define WM8580_SPDRXCHAN2                    0x2D
  85 #define WM8580_SPDRXCHAN3                    0x2E
  86 #define WM8580_SPDRXCHAN4                    0x2F
  87 #define WM8580_SPDRXCHAN5                    0x30
  88 #define WM8580_SPDSTAT                       0x31
  89 #define WM8580_PWRDN1                        0x32
  90 #define WM8580_PWRDN2                        0x33
  91 #define WM8580_READBACK                      0x34
  92 #define WM8580_RESET                         0x35
  93
  94 #define WM8580_MAX_REGISTER                  0x35
  95
  96 /* PLLB4 (register 7h) */
  97 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
  98 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
  99 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 100 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 101
 102 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 103 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 104 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 105 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 106
 107 /* CLKSEL (register 8h) */
 108 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 109 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 110 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 111
 112 /* AIF control 1 (registers 9h-bh) */
 113 #define WM8580_AIF_RATE_MASK       0x7
 114 #define WM8580_AIF_RATE_128        0x0
 115 #define WM8580_AIF_RATE_192        0x1
 116 #define WM8580_AIF_RATE_256        0x2
 117 #define WM8580_AIF_RATE_384        0x3
 118 #define WM8580_AIF_RATE_512        0x4
 119 #define WM8580_AIF_RATE_768        0x5
 120 #define WM8580_AIF_RATE_1152       0x6
 121
 122 #define WM8580_AIF_BCLKSEL_MASK   0x18
 123 #define WM8580_AIF_BCLKSEL_64     0x00
 124 #define WM8580_AIF_BCLKSEL_128    0x08
 125 #define WM8580_AIF_BCLKSEL_256    0x10
 126 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 127
 128 #define WM8580_AIF_MS             0x20
 129
 130 #define WM8580_AIF_CLKSRC_MASK    0xc0
 131 #define WM8580_AIF_CLKSRC_PLLA    0x40
 132 #define WM8580_AIF_CLKSRC_PLLB    0x40
 133 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 134
 135 /* AIF control 2 (registers ch-eh) */
 136 #define WM8580_AIF_FMT_MASK    0x03
 137 #define WM8580_AIF_FMT_RIGHTJ  0x00
 138 #define WM8580_AIF_FMT_LEFTJ   0x01
 139 #define WM8580_AIF_FMT_I2S     0x02
 140 #define WM8580_AIF_FMT_DSP     0x03
 141
 142 #define WM8580_AIF_LENGTH_MASK   0x0c
 143 #define WM8580_AIF_LENGTH_16     0x00
 144 #define WM8580_AIF_LENGTH_20     0x04
 145 #define WM8580_AIF_LENGTH_24     0x08
 146 #define WM8580_AIF_LENGTH_32     0x0c
 147
 148 #define WM8580_AIF_LRP         0x10
 149 #define WM8580_AIF_BCP         0x20
 150
 151 /* Powerdown Register 1 (register 32h) */
 152 #define WM8580_PWRDN1_PWDN     0x001
 153 #define WM8580_PWRDN1_ALLDACPD 0x040
 154
 155 /* Powerdown Register 2 (register 33h) */
 156 #define WM8580_PWRDN2_OSSCPD   0x001
 157 #define WM8580_PWRDN2_PLLAPD   0x002
 158 #define WM8580_PWRDN2_PLLBPD   0x004
 159 #define WM8580_PWRDN2_SPDIFPD  0x008
 160 #define WM8580_PWRDN2_SPDIFTXD 0x010
 161 #define WM8580_PWRDN2_SPDIFRXD 0x020
 162
 163 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 164
 165 /*
 166  * wm8580 register cache
 167  * We can't read the WM8580 register space when we
 168  * are using 2 wire for device control, so we cache them instead.
 169  */
 170 static const u16 wm8580_reg[] = {
 171         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 172         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 173         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 174         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 175         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 176         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 177         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 178         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 179         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 180         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 181         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 182         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 183         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 184         0x0000, 0x0000 /*R53*/
 185 };
 186
 187 struct pll_state {
 188         unsigned int in;
 189         unsigned int out;
 190 };
 191
 192 #define WM8580_NUM_SUPPLIES 3
 193 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 194         "AVDD",
 195         "DVDD",
 196         "PVDD",
 197 };
 198
 199 /* codec private data */
 200 struct wm8580_priv {
 201         struct snd_soc_codec codec;
 202         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 203         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 204         struct pll_state a;
 205         struct pll_state b;
 206 };
 207
 208 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 209
 210 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 211                          struct snd_ctl_elem_value *ucontrol)
 212 {
 213         struct soc_mixer_control *mc =
 214                 (struct soc_mixer_control *)kcontrol->private_value;
 215         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 216         u16 *reg_cache = codec->reg_cache;
 217         unsigned int reg = mc->reg;
 218         unsigned int reg2 = mc->rreg;
 219         int ret;
 220
 221         /* Clear the register cache so we write without VU set */
 222         reg_cache[reg] = 0;
 223         reg_cache[reg2] = 0;
 224
 225         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 226         if (ret < 0)
 227                 return ret;
 228
 229         /* Now write again with the volume update bit set */
 230         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 231         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 232
 233         return 0;
 234 }
 235
 236 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 237                                     xinvert, tlv_array)                 \
 238 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 239         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 240                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 241         .tlv.p = (tlv_array), \
 242         .info = snd_soc_info_volsw_2r, \
 243         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 244         .private_value = (unsigned long)&(struct soc_mixer_control) \
 245                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 246                 .max = xmax, .invert = xinvert} }
 247
 248 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 249 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 250                             WM8580_DIGITAL_ATTENUATION_DACL1,
 251                             WM8580_DIGITAL_ATTENUATION_DACR1,
 252                             0, 0xff, 0, dac_tlv),
 253 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 254                             WM8580_DIGITAL_ATTENUATION_DACL2,
 255                             WM8580_DIGITAL_ATTENUATION_DACR2,
 256                             0, 0xff, 0, dac_tlv),
 257 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 258                             WM8580_DIGITAL_ATTENUATION_DACL3,
 259                             WM8580_DIGITAL_ATTENUATION_DACR3,
 260                             0, 0xff, 0, dac_tlv),
 261
 262 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 263 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 264 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 265
 266 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 267 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 268 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 269
 270 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 271 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 272 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 273 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 274
 275 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
 276 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 277 };
 278
 279 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 280 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 281 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 282 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 283
 284 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 285 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 286 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 287 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 288 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 289 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 290
 291 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 292
 293 SND_SOC_DAPM_INPUT("AINL"),
 294 SND_SOC_DAPM_INPUT("AINR"),
 295 };
 296
 297 static const struct snd_soc_dapm_route audio_map[] = {
 298         { "VOUT1L", NULL, "DAC1" },
 299         { "VOUT1R", NULL, "DAC1" },
 300
 301         { "VOUT2L", NULL, "DAC2" },
 302         { "VOUT2R", NULL, "DAC2" },
 303
 304         { "VOUT3L", NULL, "DAC3" },
 305         { "VOUT3R", NULL, "DAC3" },
 306
 307         { "ADC", NULL, "AINL" },
 308         { "ADC", NULL, "AINR" },
 309 };
 310
 311 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 312 {
 313         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 314                                   ARRAY_SIZE(wm8580_dapm_widgets));
 315
 316         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 317
 318         return 0;
 319 }
 320
 321 /* PLL divisors */
 322 struct _pll_div {
 323         u32 prescale:1;
 324         u32 postscale:1;
 325         u32 freqmode:2;
 326         u32 n:4;
 327         u32 k:24;
 328 };
 329
 330 /* The size in bits of the pll divide */
 331 #define FIXED_PLL_SIZE (1 << 22)
 332
 333 /* PLL rate to output rate divisions */
 334 static struct {
 335         unsigned int div;
 336         unsigned int freqmode;
 337         unsigned int postscale;
 338 } post_table[] = {
 339         {  2,  0, 0 },
 340         {  4,  0, 1 },
 341         {  4,  1, 0 },
 342         {  8,  1, 1 },
 343         {  8,  2, 0 },
 344         { 16,  2, 1 },
 345         { 12,  3, 0 },
 346         { 24,  3, 1 }
 347 };
 348
 349 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 350                        unsigned int source)
 351 {
 352         u64 Kpart;
 353         unsigned int K, Ndiv, Nmod;
 354         int i;
 355
 356         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 357
 358         /* Scale the output frequency up; the PLL should run in the
 359          * region of 90-100MHz.
 360          */
 361         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 362                 if (target * post_table[i].div >=  90000000 &&
 363                     target * post_table[i].div <= 100000000) {
 364                         pll_div->freqmode = post_table[i].freqmode;
 365                         pll_div->postscale = post_table[i].postscale;
 366                         target *= post_table[i].div;
 367                         break;
 368                 }
 369         }
 370
 371         if (i == ARRAY_SIZE(post_table)) {
 372                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 373                        "%u\n", target);
 374                 return -EINVAL;
 375         }
 376
 377         Ndiv = target / source;
 378
 379         if (Ndiv < 5) {
 380                 source /= 2;
 381                 pll_div->prescale = 1;
 382                 Ndiv = target / source;
 383         } else
 384                 pll_div->prescale = 0;
 385
 386         if ((Ndiv < 5) || (Ndiv > 13)) {
 387                 printk(KERN_ERR
 388                         "WM8580 N=%u outside supported range\n", Ndiv);
 389                 return -EINVAL;
 390         }
 391
 392         pll_div->n = Ndiv;
 393         Nmod = target % source;
 394         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 395
 396         do_div(Kpart, source);
 397
 398         K = Kpart & 0xFFFFFFFF;
 399
 400         pll_div->k = K;
 401
 402         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 403                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 404                  pll_div->postscale);
 405
 406         return 0;
 407 }
 408
 409 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 410                 int source, unsigned int freq_in, unsigned int freq_out)
 411 {
 412         int offset;
 413         struct snd_soc_codec *codec = codec_dai->codec;
 414         struct wm8580_priv *wm8580 = codec->private_data;
 415         struct pll_state *state;
 416         struct _pll_div pll_div;
 417         unsigned int reg;
 418         unsigned int pwr_mask;
 419         int ret;
 420
 421         /* GCC isn't able to work out the ifs below for initialising/using
 422          * pll_div so suppress warnings.
 423          */
 424         memset(&pll_div, 0, sizeof(pll_div));
 425
 426         switch (pll_id) {
 427         case WM8580_PLLA:
 428                 state = &wm8580->a;
 429                 offset = 0;
 430                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 431                 break;
 432         case WM8580_PLLB:
 433                 state = &wm8580->b;
 434                 offset = 4;
 435                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 436                 break;
 437         default:
 438                 return -ENODEV;
 439         }
 440
 441         if (freq_in && freq_out) {
 442                 ret = pll_factors(&pll_div, freq_out, freq_in);
 443                 if (ret != 0)
 444                         return ret;
 445         }
 446
 447         state->in = freq_in;
 448         state->out = freq_out;
 449
 450         /* Always disable the PLL - it is not safe to leave it running
 451          * while reprogramming it.
 452          */
 453         reg = snd_soc_read(codec, WM8580_PWRDN2);
 454         snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 455
 456         if (!freq_in || !freq_out)
 457                 return 0;
 458
 459         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 460         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 461         snd_soc_write(codec, WM8580_PLLA3 + offset,
 462                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 463
 464         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 465         reg &= ~0x1b;
 466         reg |= pll_div.prescale | pll_div.postscale << 1 |
 467                 pll_div.freqmode << 3;
 468
 469         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 470
 471         /* All done, turn it on */
 472         reg = snd_soc_read(codec, WM8580_PWRDN2);
 473         snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 474
 475         return 0;
 476 }
 477
 478 /*
 479  * Set PCM DAI bit size and sample rate.
 480  */
 481 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 482                                  struct snd_pcm_hw_params *params,
 483                                  struct snd_soc_dai *dai)
 484 {
 485         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 486         struct snd_soc_device *socdev = rtd->socdev;
 487         struct snd_soc_codec *codec = socdev->card->codec;
 488         u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->id);
 489
 490         paifb &= ~WM8580_AIF_LENGTH_MASK;
 491         /* bit size */
 492         switch (params_format(params)) {
 493         case SNDRV_PCM_FORMAT_S16_LE:
 494                 break;
 495         case SNDRV_PCM_FORMAT_S20_3LE:
 496                 paifb |= WM8580_AIF_LENGTH_20;
 497                 break;
 498         case SNDRV_PCM_FORMAT_S24_LE:
 499                 paifb |= WM8580_AIF_LENGTH_24;
 500                 break;
 501         case SNDRV_PCM_FORMAT_S32_LE:
 502                 paifb |= WM8580_AIF_LENGTH_24;
 503                 break;
 504         default:
 505                 return -EINVAL;
 506         }
 507
 508         snd_soc_write(codec, WM8580_PAIF3 + dai->id, paifb);
 509         return 0;
 510 }
 511
 512 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 513                                       unsigned int fmt)
 514 {
 515         struct snd_soc_codec *codec = codec_dai->codec;
 516         unsigned int aifa;
 517         unsigned int aifb;
 518         int can_invert_lrclk;
 519
 520         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
 521         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->id);
 522
 523         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 524
 525         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 526         case SND_SOC_DAIFMT_CBS_CFS:
 527                 aifa &= ~WM8580_AIF_MS;
 528                 break;
 529         case SND_SOC_DAIFMT_CBM_CFM:
 530                 aifa |= WM8580_AIF_MS;
 531                 break;
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 537         case SND_SOC_DAIFMT_I2S:
 538                 can_invert_lrclk = 1;
 539                 aifb |= WM8580_AIF_FMT_I2S;
 540                 break;
 541         case SND_SOC_DAIFMT_RIGHT_J:
 542                 can_invert_lrclk = 1;
 543                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 544                 break;
 545         case SND_SOC_DAIFMT_LEFT_J:
 546                 can_invert_lrclk = 1;
 547                 aifb |= WM8580_AIF_FMT_LEFTJ;
 548                 break;
 549         case SND_SOC_DAIFMT_DSP_A:
 550                 can_invert_lrclk = 0;
 551                 aifb |= WM8580_AIF_FMT_DSP;
 552                 break;
 553         case SND_SOC_DAIFMT_DSP_B:
 554                 can_invert_lrclk = 0;
 555                 aifb |= WM8580_AIF_FMT_DSP;
 556                 aifb |= WM8580_AIF_LRP;
 557                 break;
 558         default:
 559                 return -EINVAL;
 560         }
 561
 562         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 563         case SND_SOC_DAIFMT_NB_NF:
 564                 break;
 565
 566         case SND_SOC_DAIFMT_IB_IF:
 567                 if (!can_invert_lrclk)
 568                         return -EINVAL;
 569                 aifb |= WM8580_AIF_BCP;
 570                 aifb |= WM8580_AIF_LRP;
 571                 break;
 572
 573         case SND_SOC_DAIFMT_IB_NF:
 574                 aifb |= WM8580_AIF_BCP;
 575                 break;
 576
 577         case SND_SOC_DAIFMT_NB_IF:
 578                 if (!can_invert_lrclk)
 579                         return -EINVAL;
 580                 aifb |= WM8580_AIF_LRP;
 581                 break;
 582
 583         default:
 584                 return -EINVAL;
 585         }
 586
 587         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
 588         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
 589
 590         return 0;
 591 }
 592
 593 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 594                                  int div_id, int div)
 595 {
 596         struct snd_soc_codec *codec = codec_dai->codec;
 597         unsigned int reg;
 598
 599         switch (div_id) {
 600         case WM8580_MCLK:
 601                 reg = snd_soc_read(codec, WM8580_PLLB4);
 602                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 603
 604                 switch (div) {
 605                 case WM8580_CLKSRC_MCLK:
 606                         /* Input */
 607                         break;
 608
 609                 case WM8580_CLKSRC_PLLA:
 610                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 611                         break;
 612                 case WM8580_CLKSRC_PLLB:
 613                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 614                         break;
 615
 616                 case WM8580_CLKSRC_OSC:
 617                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 618                         break;
 619
 620                 default:
 621                         return -EINVAL;
 622                 }
 623                 snd_soc_write(codec, WM8580_PLLB4, reg);
 624                 break;
 625
 626         case WM8580_DAC_CLKSEL:
 627                 reg = snd_soc_read(codec, WM8580_CLKSEL);
 628                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
 629
 630                 switch (div) {
 631                 case WM8580_CLKSRC_MCLK:
 632                         break;
 633
 634                 case WM8580_CLKSRC_PLLA:
 635                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
 636                         break;
 637
 638                 case WM8580_CLKSRC_PLLB:
 639                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
 640                         break;
 641
 642                 default:
 643                         return -EINVAL;
 644                 }
 645                 snd_soc_write(codec, WM8580_CLKSEL, reg);
 646                 break;
 647
 648         case WM8580_CLKOUTSRC:
 649                 reg = snd_soc_read(codec, WM8580_PLLB4);
 650                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 651
 652                 switch (div) {
 653                 case WM8580_CLKSRC_NONE:
 654                         break;
 655
 656                 case WM8580_CLKSRC_PLLA:
 657                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 658                         break;
 659
 660                 case WM8580_CLKSRC_PLLB:
 661                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 662                         break;
 663
 664                 case WM8580_CLKSRC_OSC:
 665                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 666                         break;
 667
 668                 default:
 669                         return -EINVAL;
 670                 }
 671                 snd_soc_write(codec, WM8580_PLLB4, reg);
 672                 break;
 673
 674         default:
 675                 return -EINVAL;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 682 {
 683         struct snd_soc_codec *codec = codec_dai->codec;
 684         unsigned int reg;
 685
 686         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 687
 688         if (mute)
 689                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 690         else
 691                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 692
 693         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 694
 695         return 0;
 696 }
 697
 698 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 699         enum snd_soc_bias_level level)
 700 {
 701         u16 reg;
 702         switch (level) {
 703         case SND_SOC_BIAS_ON:
 704         case SND_SOC_BIAS_PREPARE:
 705                 break;
 706
 707         case SND_SOC_BIAS_STANDBY:
 708                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 709                         /* Power up and get individual control of the DACs */
 710                         reg = snd_soc_read(codec, WM8580_PWRDN1);
 711                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 712                         snd_soc_write(codec, WM8580_PWRDN1, reg);
 713
 714                         /* Make VMID high impedence */
 715                         reg = snd_soc_read(codec,  WM8580_ADC_CONTROL1);
 716                         reg &= ~0x100;
 717                         snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
 718                 }
 719                 break;
 720
 721         case SND_SOC_BIAS_OFF:
 722                 reg = snd_soc_read(codec, WM8580_PWRDN1);
 723                 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 724                 break;
 725         }
 726         codec->bias_level = level;
 727         return 0;
 728 }
 729
 730 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 731                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 732
 733 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 734         .hw_params      = wm8580_paif_hw_params,
 735         .set_fmt        = wm8580_set_paif_dai_fmt,
 736         .set_clkdiv     = wm8580_set_dai_clkdiv,
 737         .set_pll        = wm8580_set_dai_pll,
 738         .digital_mute   = wm8580_digital_mute,
 739 };
 740
 741 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 742         .hw_params      = wm8580_paif_hw_params,
 743         .set_fmt        = wm8580_set_paif_dai_fmt,
 744         .set_clkdiv     = wm8580_set_dai_clkdiv,
 745         .set_pll        = wm8580_set_dai_pll,
 746 };
 747
 748 struct snd_soc_dai wm8580_dai[] = {
 749         {
 750                 .name = "WM8580 PAIFRX",
 751                 .id = 0,
 752                 .playback = {
 753                         .stream_name = "Playback",
 754                         .channels_min = 1,
 755                         .channels_max = 6,
 756                         .rates = SNDRV_PCM_RATE_8000_192000,
 757                         .formats = WM8580_FORMATS,
 758                 },
 759                 .ops = &wm8580_dai_ops_playback,
 760         },
 761         {
 762                 .name = "WM8580 PAIFTX",
 763                 .id = 1,
 764                 .capture = {
 765                         .stream_name = "Capture",
 766                         .channels_min = 2,
 767                         .channels_max = 2,
 768                         .rates = SNDRV_PCM_RATE_8000_192000,
 769                         .formats = WM8580_FORMATS,
 770                 },
 771                 .ops = &wm8580_dai_ops_capture,
 772         },
 773 };
 774 EXPORT_SYMBOL_GPL(wm8580_dai);
 775
 776 static struct snd_soc_codec *wm8580_codec;
 777
 778 static int wm8580_probe(struct platform_device *pdev)
 779 {
 780         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 781         struct snd_soc_codec *codec;
 782         int ret = 0;
 783
 784         if (wm8580_codec == NULL) {
 785                 dev_err(&pdev->dev, "Codec device not registered\n");
 786                 return -ENODEV;
 787         }
 788
 789         socdev->card->codec = wm8580_codec;
 790         codec = wm8580_codec;
 791
 792         /* register pcms */
 793         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 794         if (ret < 0) {
 795                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 796                 goto pcm_err;
 797         }
 798
 799         snd_soc_add_controls(codec, wm8580_snd_controls,
 800                              ARRAY_SIZE(wm8580_snd_controls));
 801         wm8580_add_widgets(codec);
 802
 803         return ret;
 804
 805 pcm_err:
 806         return ret;
 807 }
 808
 809 /* power down chip */
 810 static int wm8580_remove(struct platform_device *pdev)
 811 {
 812         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 813
 814         snd_soc_free_pcms(socdev);
 815         snd_soc_dapm_free(socdev);
 816
 817         return 0;
 818 }
 819
 820 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
 821         .probe =        wm8580_probe,
 822         .remove =       wm8580_remove,
 823 };
 824 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
 825
 826 static int wm8580_register(struct wm8580_priv *wm8580,
 827                            enum snd_soc_control_type control)
 828 {
 829         int ret, i;
 830         struct snd_soc_codec *codec = &wm8580->codec;
 831
 832         if (wm8580_codec) {
 833                 dev_err(codec->dev, "Another WM8580 is registered\n");
 834                 ret = -EINVAL;
 835                 goto err;
 836         }
 837
 838         mutex_init(&codec->mutex);
 839         INIT_LIST_HEAD(&codec->dapm_widgets);
 840         INIT_LIST_HEAD(&codec->dapm_paths);
 841
 842         codec->private_data = wm8580;
 843         codec->name = "WM8580";
 844         codec->owner = THIS_MODULE;
 845         codec->bias_level = SND_SOC_BIAS_OFF;
 846         codec->set_bias_level = wm8580_set_bias_level;
 847         codec->dai = wm8580_dai;
 848         codec->num_dai = ARRAY_SIZE(wm8580_dai);
 849         codec->reg_cache_size = ARRAY_SIZE(wm8580->reg_cache);
 850         codec->reg_cache = &wm8580->reg_cache;
 851
 852         memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
 853
 854         ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
 855         if (ret < 0) {
 856                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 857                 goto err;
 858         }
 859
 860         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 861                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 862
 863         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 864                                  wm8580->supplies);
 865         if (ret != 0) {
 866                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 867                 goto err;
 868         }
 869
 870         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 871                                     wm8580->supplies);
 872         if (ret != 0) {
 873                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 874                 goto err_regulator_get;
 875         }
 876
 877         /* Get the codec into a known state */
 878         ret = snd_soc_write(codec, WM8580_RESET, 0);
 879         if (ret != 0) {
 880                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 881                 goto err_regulator_enable;
 882         }
 883
 884         for (i = 0; i < ARRAY_SIZE(wm8580_dai); i++)
 885                 wm8580_dai[i].dev = codec->dev;
 886
 887         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 888
 889         wm8580_codec = codec;
 890
 891         ret = snd_soc_register_codec(codec);
 892         if (ret != 0) {
 893                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
 894                 goto err_regulator_enable;
 895         }
 896
 897         ret = snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 898         if (ret != 0) {
 899                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
 900                 goto err_codec;
 901         }
 902
 903         return 0;
 904
 905 err_codec:
 906         snd_soc_unregister_codec(codec);
 907 err_regulator_enable:
 908         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 909 err_regulator_get:
 910         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 911 err:
 912         kfree(wm8580);
 913         return ret;
 914 }
 915
 916 static void wm8580_unregister(struct wm8580_priv *wm8580)
 917 {
 918         wm8580_set_bias_level(&wm8580->codec, SND_SOC_BIAS_OFF);
 919         snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 920         snd_soc_unregister_codec(&wm8580->codec);
 921         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 922         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 923         kfree(wm8580);
 924         wm8580_codec = NULL;
 925 }
 926
 927 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 928 static int wm8580_i2c_probe(struct i2c_client *i2c,
 929                             const struct i2c_device_id *id)
 930 {
 931         struct wm8580_priv *wm8580;
 932         struct snd_soc_codec *codec;
 933
 934         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 935         if (wm8580 == NULL)
 936                 return -ENOMEM;
 937
 938         codec = &wm8580->codec;
 939
 940         i2c_set_clientdata(i2c, wm8580);
 941         codec->control_data = i2c;
 942
 943         codec->dev = &i2c->dev;
 944
 945         return wm8580_register(wm8580, SND_SOC_I2C);
 946 }
 947
 948 static int wm8580_i2c_remove(struct i2c_client *client)
 949 {
 950         struct wm8580_priv *wm8580 = i2c_get_clientdata(client);
 951         wm8580_unregister(wm8580);
 952         return 0;
 953 }
 954
 955 static const struct i2c_device_id wm8580_i2c_id[] = {
 956         { "wm8580", 0 },
 957         { }
 958 };
 959 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 960
 961 static struct i2c_driver wm8580_i2c_driver = {
 962         .driver = {
 963                 .name = "wm8580",
 964                 .owner = THIS_MODULE,
 965         },
 966         .probe =    wm8580_i2c_probe,
 967         .remove =   wm8580_i2c_remove,
 968         .id_table = wm8580_i2c_id,
 969 };
 970 #endif
 971
 972 static int __init wm8580_modinit(void)
 973 {
 974         int ret;
 975
 976 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 977         ret = i2c_add_driver(&wm8580_i2c_driver);
 978         if (ret != 0) {
 979                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 980         }
 981 #endif
 982
 983         return 0;
 984 }
 985 module_init(wm8580_modinit);
 986
 987 static void __exit wm8580_exit(void)
 988 {
 989 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 990         i2c_del_driver(&wm8580_i2c_driver);
 991 #endif
 992 }
 993 module_exit(wm8580_exit);
 994
 995 MODULE_DESCRIPTION("ASoC WM8580 driver");
 996 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 997 MODULE_LICENSE("GPL");