2 * ALSA SoC TWL4030 codec driver
4 * Author: Steve Sakoman, <steve@sakoman.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
41 * twl4030 register cache & default register settings
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x93, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
121 * read twl4030 register cache
123 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
126 u8 *cache = codec->reg_cache;
132 * write twl4030 register cache
134 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
137 u8 *cache = codec->reg_cache;
139 if (reg >= TWL4030_CACHEREGNUM)
145 * write to the twl4030 register space
147 static int twl4030_write(struct snd_soc_codec *codec,
148 unsigned int reg, unsigned int value)
150 twl4030_write_reg_cache(codec, reg, value);
151 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
154 static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
158 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
159 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
160 mode & ~TWL4030_CODECPDZ);
162 /* REVISIT: this delay is present in TI sample drivers */
163 /* but there seems to be no TRM requirement for it */
167 static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
171 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
172 twl4030_write(codec, TWL4030_REG_CODEC_MODE,
173 mode | TWL4030_CODECPDZ);
175 /* REVISIT: this delay is present in TI sample drivers */
176 /* but there seems to be no TRM requirement for it */
180 static void twl4030_init_chip(struct snd_soc_codec *codec)
184 /* clear CODECPDZ prior to setting register defaults */
185 twl4030_clear_codecpdz(codec);
187 /* set all audio section registers to reasonable defaults */
188 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
189 twl4030_write(codec, i, twl4030_reg[i]);
194 static const char *twl4030_earpiece_texts[] =
195 {"Off", "DACL1", "DACL2", "Invalid",
198 static const struct soc_enum twl4030_earpiece_enum =
199 SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
200 ARRAY_SIZE(twl4030_earpiece_texts),
201 twl4030_earpiece_texts);
203 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
204 SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
207 static const char *twl4030_predrivel_texts[] =
208 {"Off", "DACL1", "DACL2", "Invalid",
211 static const struct soc_enum twl4030_predrivel_enum =
212 SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
213 ARRAY_SIZE(twl4030_predrivel_texts),
214 twl4030_predrivel_texts);
216 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
217 SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
220 static const char *twl4030_predriver_texts[] =
221 {"Off", "DACR1", "DACR2", "Invalid",
224 static const struct soc_enum twl4030_predriver_enum =
225 SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
226 ARRAY_SIZE(twl4030_predriver_texts),
227 twl4030_predriver_texts);
229 static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
230 SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
232 static int outmixer_event(struct snd_soc_dapm_widget *w,
233 struct snd_kcontrol *kcontrol, int event)
235 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
240 case TWL4030_REG_PREDL_CTL:
241 case TWL4030_REG_PREDR_CTL:
242 case TWL4030_REG_EAR_CTL:
243 val = w->value >> e->shift_l;
246 "Invalid MUX setting for register 0x%02x (%d)\n",
257 * Some of the gain controls in TWL (mostly those which are associated with
258 * the outputs) are implemented in an interesting way:
259 * 0x0 : Power down (mute)
263 * Inverting not going to help with these.
264 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
266 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
267 xinvert, tlv_array) \
268 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
269 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
270 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
271 .tlv.p = (tlv_array), \
272 .info = snd_soc_info_volsw, \
273 .get = snd_soc_get_volsw_twl4030, \
274 .put = snd_soc_put_volsw_twl4030, \
275 .private_value = (unsigned long)&(struct soc_mixer_control) \
276 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
277 .max = xmax, .invert = xinvert} }
278 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
279 xinvert, tlv_array) \
280 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
281 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
282 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
283 .tlv.p = (tlv_array), \
284 .info = snd_soc_info_volsw_2r, \
285 .get = snd_soc_get_volsw_r2_twl4030,\
286 .put = snd_soc_put_volsw_r2_twl4030, \
287 .private_value = (unsigned long)&(struct soc_mixer_control) \
288 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
289 .max = xmax, .invert = xinvert} }
290 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
291 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
294 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_value *ucontrol)
297 struct soc_mixer_control *mc =
298 (struct soc_mixer_control *)kcontrol->private_value;
299 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
300 unsigned int reg = mc->reg;
301 unsigned int shift = mc->shift;
302 unsigned int rshift = mc->rshift;
304 int mask = (1 << fls(max)) - 1;
306 ucontrol->value.integer.value[0] =
307 (snd_soc_read(codec, reg) >> shift) & mask;
308 if (ucontrol->value.integer.value[0])
309 ucontrol->value.integer.value[0] =
310 max + 1 - ucontrol->value.integer.value[0];
312 if (shift != rshift) {
313 ucontrol->value.integer.value[1] =
314 (snd_soc_read(codec, reg) >> rshift) & mask;
315 if (ucontrol->value.integer.value[1])
316 ucontrol->value.integer.value[1] =
317 max + 1 - ucontrol->value.integer.value[1];
323 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
324 struct snd_ctl_elem_value *ucontrol)
326 struct soc_mixer_control *mc =
327 (struct soc_mixer_control *)kcontrol->private_value;
328 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
329 unsigned int reg = mc->reg;
330 unsigned int shift = mc->shift;
331 unsigned int rshift = mc->rshift;
333 int mask = (1 << fls(max)) - 1;
334 unsigned short val, val2, val_mask;
336 val = (ucontrol->value.integer.value[0] & mask);
338 val_mask = mask << shift;
342 if (shift != rshift) {
343 val2 = (ucontrol->value.integer.value[1] & mask);
344 val_mask |= mask << rshift;
346 val2 = max + 1 - val2;
347 val |= val2 << rshift;
349 return snd_soc_update_bits(codec, reg, val_mask, val);
352 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
355 struct soc_mixer_control *mc =
356 (struct soc_mixer_control *)kcontrol->private_value;
357 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
358 unsigned int reg = mc->reg;
359 unsigned int reg2 = mc->rreg;
360 unsigned int shift = mc->shift;
362 int mask = (1<<fls(max))-1;
364 ucontrol->value.integer.value[0] =
365 (snd_soc_read(codec, reg) >> shift) & mask;
366 ucontrol->value.integer.value[1] =
367 (snd_soc_read(codec, reg2) >> shift) & mask;
369 if (ucontrol->value.integer.value[0])
370 ucontrol->value.integer.value[0] =
371 max + 1 - ucontrol->value.integer.value[0];
372 if (ucontrol->value.integer.value[1])
373 ucontrol->value.integer.value[1] =
374 max + 1 - ucontrol->value.integer.value[1];
379 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
382 struct soc_mixer_control *mc =
383 (struct soc_mixer_control *)kcontrol->private_value;
384 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
385 unsigned int reg = mc->reg;
386 unsigned int reg2 = mc->rreg;
387 unsigned int shift = mc->shift;
389 int mask = (1 << fls(max)) - 1;
391 unsigned short val, val2, val_mask;
393 val_mask = mask << shift;
394 val = (ucontrol->value.integer.value[0] & mask);
395 val2 = (ucontrol->value.integer.value[1] & mask);
400 val2 = max + 1 - val2;
403 val2 = val2 << shift;
405 err = snd_soc_update_bits(codec, reg, val_mask, val);
409 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
413 static int twl4030_get_left_input(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
416 struct snd_soc_codec *codec = kcontrol->private_data;
417 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
420 /* one bit must be set a time */
421 reg &= TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
422 | TWL4030_MAINMIC_EN;
425 while ((reg & 1) == 0) {
431 ucontrol->value.integer.value[0] = result;
435 static int twl4030_put_left_input(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
438 struct snd_soc_codec *codec = kcontrol->private_data;
439 int value = ucontrol->value.integer.value[0];
440 u8 anamicl, micbias, avadc_ctl;
442 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
443 anamicl &= ~(TWL4030_CKMIC_EN | TWL4030_AUXL_EN | TWL4030_HSMIC_EN
444 | TWL4030_MAINMIC_EN);
445 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
446 micbias &= ~(TWL4030_HSMICBIAS_EN | TWL4030_MICBIAS1_EN);
447 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
451 anamicl |= TWL4030_MAINMIC_EN;
452 micbias |= TWL4030_MICBIAS1_EN;
455 anamicl |= TWL4030_HSMIC_EN;
456 micbias |= TWL4030_HSMICBIAS_EN;
459 anamicl |= TWL4030_AUXL_EN;
462 anamicl |= TWL4030_CKMIC_EN;
468 /* If some input is selected, enable amp and ADC */
470 anamicl |= TWL4030_MICAMPL_EN;
471 avadc_ctl |= TWL4030_ADCL_EN;
473 anamicl &= ~TWL4030_MICAMPL_EN;
474 avadc_ctl &= ~TWL4030_ADCL_EN;
477 twl4030_write(codec, TWL4030_REG_ANAMICL, anamicl);
478 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
479 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
484 static int twl4030_get_right_input(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
487 struct snd_soc_codec *codec = kcontrol->private_data;
488 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
491 reg &= TWL4030_SUBMIC_EN|TWL4030_AUXR_EN;
493 case TWL4030_SUBMIC_EN:
496 case TWL4030_AUXR_EN:
503 ucontrol->value.integer.value[0] = value;
507 static int twl4030_put_right_input(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
510 struct snd_soc_codec *codec = kcontrol->private_data;
511 int value = ucontrol->value.integer.value[0];
512 u8 anamicr, micbias, avadc_ctl;
514 anamicr = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICR);
515 anamicr &= ~(TWL4030_SUBMIC_EN|TWL4030_AUXR_EN);
516 micbias = twl4030_read_reg_cache(codec, TWL4030_REG_MICBIAS_CTL);
517 micbias &= ~TWL4030_MICBIAS2_EN;
518 avadc_ctl = twl4030_read_reg_cache(codec, TWL4030_REG_AVADC_CTL);
522 anamicr |= TWL4030_SUBMIC_EN;
523 micbias |= TWL4030_MICBIAS2_EN;
526 anamicr |= TWL4030_AUXR_EN;
533 anamicr |= TWL4030_MICAMPR_EN;
534 avadc_ctl |= TWL4030_ADCR_EN;
536 anamicr &= ~TWL4030_MICAMPR_EN;
537 avadc_ctl &= ~TWL4030_ADCR_EN;
540 twl4030_write(codec, TWL4030_REG_ANAMICR, anamicr);
541 twl4030_write(codec, TWL4030_REG_MICBIAS_CTL, micbias);
542 twl4030_write(codec, TWL4030_REG_AVADC_CTL, avadc_ctl);
547 static const char *twl4030_left_in_sel[] = {
555 static const char *twl4030_right_in_sel[] = {
561 static const struct soc_enum twl4030_left_input_mux =
562 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_left_in_sel),
563 twl4030_left_in_sel);
565 static const struct soc_enum twl4030_right_input_mux =
566 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl4030_right_in_sel),
567 twl4030_right_in_sel);
570 * FGAIN volume control:
571 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
573 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
576 * CGAIN volume control:
577 * 0 dB to 12 dB in 6 dB steps
578 * value 2 and 3 means 12 dB
580 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
583 * Analog playback gain
584 * -24 dB to 12 dB in 2 dB steps
586 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
589 * Gain controls tied to outputs
590 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
592 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
595 * Capture gain after the ADCs
596 * from 0 dB to 31 dB in 1 dB steps
598 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
601 * Gain control for input amplifiers
602 * 0 dB to 30 dB in 6 dB steps
604 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
606 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
607 /* Common playback gain controls */
608 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
609 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
610 0, 0x3f, 0, digital_fine_tlv),
611 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
612 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
613 0, 0x3f, 0, digital_fine_tlv),
615 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
616 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
617 6, 0x2, 0, digital_coarse_tlv),
618 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
619 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
620 6, 0x2, 0, digital_coarse_tlv),
622 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
623 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
624 3, 0x12, 1, analog_tlv),
625 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
626 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
627 3, 0x12, 1, analog_tlv),
628 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
629 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
631 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
632 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
635 /* Separate output gain controls */
636 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
637 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
638 4, 3, 0, output_tvl),
640 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
641 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
643 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
644 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
645 4, 3, 0, output_tvl),
647 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
648 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
650 /* Common capture gain controls */
651 SOC_DOUBLE_R_TLV("Capture Volume",
652 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
653 0, 0x1f, 0, digital_capture_tlv),
655 SOC_DOUBLE_TLV("Input Boost Volume", TWL4030_REG_ANAMIC_GAIN,
656 0, 3, 5, 0, input_gain_tlv),
658 /* Input source controls */
659 SOC_ENUM_EXT("Left Input Source", twl4030_left_input_mux,
660 twl4030_get_left_input, twl4030_put_left_input),
661 SOC_ENUM_EXT("Right Input Source", twl4030_right_input_mux,
662 twl4030_get_right_input, twl4030_put_right_input),
665 /* add non dapm controls */
666 static int twl4030_add_controls(struct snd_soc_codec *codec)
670 for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
671 err = snd_ctl_add(codec->card,
672 snd_soc_cnew(&twl4030_snd_controls[i],
681 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
682 SND_SOC_DAPM_INPUT("INL"),
683 SND_SOC_DAPM_INPUT("INR"),
685 SND_SOC_DAPM_OUTPUT("OUTL"),
686 SND_SOC_DAPM_OUTPUT("OUTR"),
687 SND_SOC_DAPM_OUTPUT("EARPIECE"),
688 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
689 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
692 SND_SOC_DAPM_DAC("DACR1", "Right Front Playback",
693 TWL4030_REG_AVDAC_CTL, 0, 0),
694 SND_SOC_DAPM_DAC("DACL1", "Left Front Playback",
695 TWL4030_REG_AVDAC_CTL, 1, 0),
696 SND_SOC_DAPM_DAC("DACR2", "Right Rear Playback",
697 TWL4030_REG_AVDAC_CTL, 2, 0),
698 SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
699 TWL4030_REG_AVDAC_CTL, 3, 0),
702 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
704 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
706 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
708 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
711 /* Output MUX controls */
713 SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
714 &twl4030_dapm_earpiece_control, outmixer_event,
715 SND_SOC_DAPM_PRE_REG),
717 SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
718 &twl4030_dapm_predrivel_control, outmixer_event,
719 SND_SOC_DAPM_PRE_REG),
720 SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
721 &twl4030_dapm_predriver_control, outmixer_event,
722 SND_SOC_DAPM_PRE_REG),
724 SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
725 SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
728 static const struct snd_soc_dapm_route intercon[] = {
729 {"ARXL1_APGA", NULL, "DACL1"},
730 {"ARXR1_APGA", NULL, "DACR1"},
731 {"ARXL2_APGA", NULL, "DACL2"},
732 {"ARXR2_APGA", NULL, "DACR2"},
734 /* Internal playback routings */
736 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
737 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
738 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
740 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
741 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
742 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
744 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
745 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
746 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
749 {"OUTL", NULL, "ARXL2_APGA"},
750 {"OUTR", NULL, "ARXR2_APGA"},
751 {"EARPIECE", NULL, "Earpiece Mux"},
752 {"PREDRIVEL", NULL, "PredriveL Mux"},
753 {"PREDRIVER", NULL, "PredriveR Mux"},
756 {"ADCL", NULL, "INL"},
757 {"ADCR", NULL, "INR"},
760 static int twl4030_add_widgets(struct snd_soc_codec *codec)
762 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
763 ARRAY_SIZE(twl4030_dapm_widgets));
765 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
767 snd_soc_dapm_new_widgets(codec);
771 static void twl4030_power_up(struct snd_soc_codec *codec)
773 u8 anamicl, regmisc1, byte, popn, hsgain;
776 /* set CODECPDZ to turn on codec */
777 twl4030_set_codecpdz(codec);
779 /* initiate offset cancellation */
780 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
781 twl4030_write(codec, TWL4030_REG_ANAMICL,
782 anamicl | TWL4030_CNCL_OFFSET_START);
784 /* wait for offset cancellation to complete */
786 /* this takes a little while, so don't slam i2c */
788 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
789 TWL4030_REG_ANAMICL);
790 } while ((i++ < 100) &&
791 ((byte & TWL4030_CNCL_OFFSET_START) ==
792 TWL4030_CNCL_OFFSET_START));
794 /* anti-pop when changing analog gain */
795 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
796 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
797 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
799 /* toggle CODECPDZ as per TRM */
800 twl4030_clear_codecpdz(codec);
801 twl4030_set_codecpdz(codec);
803 /* program anti-pop with bias ramp delay */
804 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
805 popn &= TWL4030_RAMP_DELAY;
806 popn |= TWL4030_RAMP_DELAY_645MS;
807 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
808 popn |= TWL4030_VMID_EN;
809 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
811 /* enable output stage and gain setting */
812 hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
813 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
815 /* enable anti-pop ramp */
816 popn |= TWL4030_RAMP_EN;
817 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
820 static void twl4030_power_down(struct snd_soc_codec *codec)
824 /* disable anti-pop ramp */
825 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
826 popn &= ~TWL4030_RAMP_EN;
827 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
829 /* disable output stage and gain setting */
830 hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
831 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
833 /* disable bias out */
834 popn &= ~TWL4030_VMID_EN;
835 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
838 twl4030_clear_codecpdz(codec);
841 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
842 enum snd_soc_bias_level level)
845 case SND_SOC_BIAS_ON:
846 twl4030_power_up(codec);
848 case SND_SOC_BIAS_PREPARE:
849 /* TODO: develop a twl4030_prepare function */
851 case SND_SOC_BIAS_STANDBY:
852 /* TODO: develop a twl4030_standby function */
853 twl4030_power_down(codec);
855 case SND_SOC_BIAS_OFF:
856 twl4030_power_down(codec);
859 codec->bias_level = level;
864 static int twl4030_hw_params(struct snd_pcm_substream *substream,
865 struct snd_pcm_hw_params *params,
866 struct snd_soc_dai *dai)
868 struct snd_soc_pcm_runtime *rtd = substream->private_data;
869 struct snd_soc_device *socdev = rtd->socdev;
870 struct snd_soc_codec *codec = socdev->codec;
871 u8 mode, old_mode, format, old_format;
875 old_mode = twl4030_read_reg_cache(codec,
876 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
877 mode = old_mode & ~TWL4030_APLL_RATE;
879 switch (params_rate(params)) {
881 mode |= TWL4030_APLL_RATE_8000;
884 mode |= TWL4030_APLL_RATE_11025;
887 mode |= TWL4030_APLL_RATE_12000;
890 mode |= TWL4030_APLL_RATE_16000;
893 mode |= TWL4030_APLL_RATE_22050;
896 mode |= TWL4030_APLL_RATE_24000;
899 mode |= TWL4030_APLL_RATE_32000;
902 mode |= TWL4030_APLL_RATE_44100;
905 mode |= TWL4030_APLL_RATE_48000;
908 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
909 params_rate(params));
913 if (mode != old_mode) {
914 /* change rate and set CODECPDZ */
915 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
916 twl4030_set_codecpdz(codec);
920 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
922 format &= ~TWL4030_DATA_WIDTH;
923 switch (params_format(params)) {
924 case SNDRV_PCM_FORMAT_S16_LE:
925 format |= TWL4030_DATA_WIDTH_16S_16W;
927 case SNDRV_PCM_FORMAT_S24_LE:
928 format |= TWL4030_DATA_WIDTH_32S_24W;
931 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
932 params_format(params));
936 if (format != old_format) {
938 /* clear CODECPDZ before changing format (codec requirement) */
939 twl4030_clear_codecpdz(codec);
942 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
944 /* set CODECPDZ afterwards */
945 twl4030_set_codecpdz(codec);
950 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
951 int clk_id, unsigned int freq, int dir)
953 struct snd_soc_codec *codec = codec_dai->codec;
958 infreq = TWL4030_APLL_INFREQ_19200KHZ;
961 infreq = TWL4030_APLL_INFREQ_26000KHZ;
964 infreq = TWL4030_APLL_INFREQ_38400KHZ;
967 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
972 infreq |= TWL4030_APLL_EN;
973 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
978 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
981 struct snd_soc_codec *codec = codec_dai->codec;
982 u8 old_format, format;
985 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
988 /* set master/slave audio interface */
989 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
990 case SND_SOC_DAIFMT_CBM_CFM:
991 format &= ~(TWL4030_AIF_SLAVE_EN);
992 format &= ~(TWL4030_CLK256FS_EN);
994 case SND_SOC_DAIFMT_CBS_CFS:
995 format |= TWL4030_AIF_SLAVE_EN;
996 format |= TWL4030_CLK256FS_EN;
1002 /* interface format */
1003 format &= ~TWL4030_AIF_FORMAT;
1004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1005 case SND_SOC_DAIFMT_I2S:
1006 format |= TWL4030_AIF_FORMAT_CODEC;
1012 if (format != old_format) {
1014 /* clear CODECPDZ before changing format (codec requirement) */
1015 twl4030_clear_codecpdz(codec);
1018 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1020 /* set CODECPDZ afterwards */
1021 twl4030_set_codecpdz(codec);
1027 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1028 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1030 struct snd_soc_dai twl4030_dai = {
1033 .stream_name = "Playback",
1036 .rates = TWL4030_RATES,
1037 .formats = TWL4030_FORMATS,},
1039 .stream_name = "Capture",
1042 .rates = TWL4030_RATES,
1043 .formats = TWL4030_FORMATS,},
1045 .hw_params = twl4030_hw_params,
1046 .set_sysclk = twl4030_set_dai_sysclk,
1047 .set_fmt = twl4030_set_dai_fmt,
1050 EXPORT_SYMBOL_GPL(twl4030_dai);
1052 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1054 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1055 struct snd_soc_codec *codec = socdev->codec;
1057 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1062 static int twl4030_resume(struct platform_device *pdev)
1064 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1065 struct snd_soc_codec *codec = socdev->codec;
1067 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1068 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1073 * initialize the driver
1074 * register the mixer and dsp interfaces with the kernel
1077 static int twl4030_init(struct snd_soc_device *socdev)
1079 struct snd_soc_codec *codec = socdev->codec;
1082 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1084 codec->name = "twl4030";
1085 codec->owner = THIS_MODULE;
1086 codec->read = twl4030_read_reg_cache;
1087 codec->write = twl4030_write;
1088 codec->set_bias_level = twl4030_set_bias_level;
1089 codec->dai = &twl4030_dai;
1091 codec->reg_cache_size = sizeof(twl4030_reg);
1092 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1094 if (codec->reg_cache == NULL)
1098 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1100 printk(KERN_ERR "twl4030: failed to create pcms\n");
1104 twl4030_init_chip(codec);
1106 /* power on device */
1107 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1109 twl4030_add_controls(codec);
1110 twl4030_add_widgets(codec);
1112 ret = snd_soc_init_card(socdev);
1114 printk(KERN_ERR "twl4030: failed to register card\n");
1121 snd_soc_free_pcms(socdev);
1122 snd_soc_dapm_free(socdev);
1124 kfree(codec->reg_cache);
1128 static struct snd_soc_device *twl4030_socdev;
1130 static int twl4030_probe(struct platform_device *pdev)
1132 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1133 struct snd_soc_codec *codec;
1135 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1139 socdev->codec = codec;
1140 mutex_init(&codec->mutex);
1141 INIT_LIST_HEAD(&codec->dapm_widgets);
1142 INIT_LIST_HEAD(&codec->dapm_paths);
1144 twl4030_socdev = socdev;
1145 twl4030_init(socdev);
1150 static int twl4030_remove(struct platform_device *pdev)
1152 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1153 struct snd_soc_codec *codec = socdev->codec;
1155 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
1161 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1162 .probe = twl4030_probe,
1163 .remove = twl4030_remove,
1164 .suspend = twl4030_suspend,
1165 .resume = twl4030_resume,
1167 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1169 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1170 MODULE_AUTHOR("Steve Sakoman");
1171 MODULE_LICENSE("GPL");