sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/soc-dapm.h>
  40 #include <sound/initval.h>
  41 #include <sound/tlv.h>
  42
  43 #include <sound/tlv320dac33-plat.h>
  44 #include "tlv320dac33.h"
  45
  46 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  47                                                  * 6144 stereo */
  48 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  49
  50 #define NSAMPLE_MAX             5700
  51
  52 #define MODE7_LTHR              10
  53 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / us))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         unsigned int nsample_min;       /* nsample should not be lower than
 104                                          * this */
 105         unsigned int nsample_max;       /* nsample should not be higher than
 106                                          * this */
 107         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 108         unsigned int nsample;           /* burst read amount from host */
 109         int mode1_latency;              /* latency caused by the i2c writes in
 110                                          * us */
 111         int auto_fifo_config;           /* Configure the FIFO based on the
 112                                          * period size */
 113         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 114         unsigned int burst_rate;        /* Interface speed in Burst modes */
 115
 116         int keep_bclk;                  /* Keep the BCLK continuously running
 117                                          * in FIFO modes */
 118         spinlock_t lock;
 119         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 120         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 121
 122         unsigned int mode1_us_burst;    /* Time to burst read n number of
 123                                          * samples */
 124         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 125
 126         unsigned int uthr;
 127
 128         enum dac33_state state;
 129         enum snd_soc_control_type control_type;
 130         void *control_data;
 131 };
 132
 133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 148 0x00, 0x00,             /* 0x38 - 0x39 */
 149 /* Registers 0x3a - 0x3f are reserved  */
 150             0x00, 0x00, /* 0x3a - 0x3b */
 151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 152
 153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 154 0x00, 0x80,             /* 0x44 - 0x45 */
 155 /* Registers 0x46 - 0x47 are reserved  */
 156             0x80, 0x80, /* 0x46 - 0x47 */
 157
 158 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 159 /* Registers 0x4b - 0x7c are reserved  */
 160                   0x00, /* 0x4b        */
 161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 173 0x00,                   /* 0x7c        */
 174
 175       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 176 };
 177
 178 /* Register read and write */
 179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 180                                                 unsigned reg)
 181 {
 182         u8 *cache = codec->reg_cache;
 183         if (reg >= DAC33_CACHEREGNUM)
 184                 return 0;
 185
 186         return cache[reg];
 187 }
 188
 189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 190                                          u8 reg, u8 value)
 191 {
 192         u8 *cache = codec->reg_cache;
 193         if (reg >= DAC33_CACHEREGNUM)
 194                 return;
 195
 196         cache[reg] = value;
 197 }
 198
 199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 200                       u8 *value)
 201 {
 202         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 203         int val;
 204
 205         *value = reg & 0xff;
 206
 207         /* If powered off, return the cached value */
 208         if (dac33->chip_power) {
 209                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 210                 if (val < 0) {
 211                         dev_err(codec->dev, "Read failed (%d)\n", val);
 212                         value[0] = dac33_read_reg_cache(codec, reg);
 213                 } else {
 214                         value[0] = val;
 215                         dac33_write_reg_cache(codec, reg, val);
 216                 }
 217         } else {
 218                 value[0] = dac33_read_reg_cache(codec, reg);
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 225                        unsigned int value)
 226 {
 227         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 228         u8 data[2];
 229         int ret = 0;
 230
 231         /*
 232          * data is
 233          *   D15..D8 dac33 register offset
 234          *   D7...D0 register data
 235          */
 236         data[0] = reg & 0xff;
 237         data[1] = value & 0xff;
 238
 239         dac33_write_reg_cache(codec, data[0], data[1]);
 240         if (dac33->chip_power) {
 241                 ret = codec->hw_write(codec->control_data, data, 2);
 242                 if (ret != 2)
 243                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 244                 else
 245                         ret = 0;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 252                        unsigned int value)
 253 {
 254         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 255         int ret;
 256
 257         mutex_lock(&dac33->mutex);
 258         ret = dac33_write(codec, reg, value);
 259         mutex_unlock(&dac33->mutex);
 260
 261         return ret;
 262 }
 263
 264 #define DAC33_I2C_ADDR_AUTOINC  0x80
 265 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 266                        unsigned int value)
 267 {
 268         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 269         u8 data[3];
 270         int ret = 0;
 271
 272         /*
 273          * data is
 274          *   D23..D16 dac33 register offset
 275          *   D15..D8  register data MSB
 276          *   D7...D0  register data LSB
 277          */
 278         data[0] = reg & 0xff;
 279         data[1] = (value >> 8) & 0xff;
 280         data[2] = value & 0xff;
 281
 282         dac33_write_reg_cache(codec, data[0], data[1]);
 283         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 284
 285         if (dac33->chip_power) {
 286                 /* We need to set autoincrement mode for 16 bit writes */
 287                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 288                 ret = codec->hw_write(codec->control_data, data, 3);
 289                 if (ret != 3)
 290                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 291                 else
 292                         ret = 0;
 293         }
 294
 295         return ret;
 296 }
 297
 298 static void dac33_init_chip(struct snd_soc_codec *codec)
 299 {
 300         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 301
 302         if (unlikely(!dac33->chip_power))
 303                 return;
 304
 305         /* 44-46: DAC Control Registers */
 306         /* A : DAC sample rate Fsref/1.5 */
 307         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 308         /* B : DAC src=normal, not muted */
 309         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 310                                              DAC33_DACSRCL_LEFT);
 311         /* C : (defaults) */
 312         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 313
 314         /* 73 : volume soft stepping control,
 315          clock source = internal osc (?) */
 316         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 317
 318         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
 319
 320         /* Restore only selected registers (gains mostly) */
 321         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 322                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 323         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 324                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 325
 326         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 327                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 328         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 329                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 330 }
 331
 332 static inline void dac33_read_id(struct snd_soc_codec *codec)
 333 {
 334         u8 reg;
 335
 336         dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
 337         dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
 338         dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
 339 }
 340
 341 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 342 {
 343         u8 reg;
 344
 345         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 346         if (power)
 347                 reg |= DAC33_PDNALLB;
 348         else
 349                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 350                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 351         dac33_write(codec, DAC33_PWR_CTRL, reg);
 352 }
 353
 354 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 355 {
 356         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 357         int ret = 0;
 358
 359         mutex_lock(&dac33->mutex);
 360
 361         /* Safety check */
 362         if (unlikely(power == dac33->chip_power)) {
 363                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 364                         power ? "ON" : "OFF");
 365                 goto exit;
 366         }
 367
 368         if (power) {
 369                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 370                                           dac33->supplies);
 371                 if (ret != 0) {
 372                         dev_err(codec->dev,
 373                                 "Failed to enable supplies: %d\n", ret);
 374                                 goto exit;
 375                 }
 376
 377                 if (dac33->power_gpio >= 0)
 378                         gpio_set_value(dac33->power_gpio, 1);
 379
 380                 dac33->chip_power = 1;
 381         } else {
 382                 dac33_soft_power(codec, 0);
 383                 if (dac33->power_gpio >= 0)
 384                         gpio_set_value(dac33->power_gpio, 0);
 385
 386                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 387                                              dac33->supplies);
 388                 if (ret != 0) {
 389                         dev_err(codec->dev,
 390                                 "Failed to disable supplies: %d\n", ret);
 391                         goto exit;
 392                 }
 393
 394                 dac33->chip_power = 0;
 395         }
 396
 397 exit:
 398         mutex_unlock(&dac33->mutex);
 399         return ret;
 400 }
 401
 402 static int playback_event(struct snd_soc_dapm_widget *w,
 403                 struct snd_kcontrol *kcontrol, int event)
 404 {
 405         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 406
 407         switch (event) {
 408         case SND_SOC_DAPM_PRE_PMU:
 409                 if (likely(dac33->substream)) {
 410                         dac33_calculate_times(dac33->substream);
 411                         dac33_prepare_chip(dac33->substream);
 412                 }
 413                 break;
 414         }
 415         return 0;
 416 }
 417
 418 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 419                          struct snd_ctl_elem_value *ucontrol)
 420 {
 421         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 422         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 423
 424         ucontrol->value.integer.value[0] = dac33->nsample;
 425
 426         return 0;
 427 }
 428
 429 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 430                          struct snd_ctl_elem_value *ucontrol)
 431 {
 432         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 433         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 434         int ret = 0;
 435
 436         if (dac33->nsample == ucontrol->value.integer.value[0])
 437                 return 0;
 438
 439         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 440             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 441                 ret = -EINVAL;
 442         } else {
 443                 dac33->nsample = ucontrol->value.integer.value[0];
 444                 /* Re calculate the burst time */
 445                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 446                                                       dac33->nsample);
 447         }
 448
 449         return ret;
 450 }
 451
 452 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
 453                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 457
 458         ucontrol->value.integer.value[0] = dac33->uthr;
 459
 460         return 0;
 461 }
 462
 463 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
 464                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 468         int ret = 0;
 469
 470         if (dac33->substream)
 471                 return -EBUSY;
 472
 473         if (dac33->uthr == ucontrol->value.integer.value[0])
 474                 return 0;
 475
 476         if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
 477             ucontrol->value.integer.value[0] > MODE7_UTHR)
 478                 ret = -EINVAL;
 479         else
 480                 dac33->uthr = ucontrol->value.integer.value[0];
 481
 482         return ret;
 483 }
 484
 485 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 486                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 490
 491         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 492
 493         return 0;
 494 }
 495
 496 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 497                          struct snd_ctl_elem_value *ucontrol)
 498 {
 499         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 500         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 501         int ret = 0;
 502
 503         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 504                 return 0;
 505         /* Do not allow changes while stream is running*/
 506         if (codec->active)
 507                 return -EPERM;
 508
 509         if (ucontrol->value.integer.value[0] < 0 ||
 510             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 511                 ret = -EINVAL;
 512         else
 513                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 514
 515         return ret;
 516 }
 517
 518 /* Codec operation modes */
 519 static const char *dac33_fifo_mode_texts[] = {
 520         "Bypass", "Mode 1", "Mode 7"
 521 };
 522
 523 static const struct soc_enum dac33_fifo_mode_enum =
 524         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 525                             dac33_fifo_mode_texts);
 526
 527 /* L/R Line Output Gain */
 528 static const char *lr_lineout_gain_texts[] = {
 529         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 530         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 531 };
 532
 533 static const struct soc_enum l_lineout_gain_enum =
 534         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 535                         ARRAY_SIZE(lr_lineout_gain_texts),
 536                         lr_lineout_gain_texts);
 537
 538 static const struct soc_enum r_lineout_gain_enum =
 539         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 540                         ARRAY_SIZE(lr_lineout_gain_texts),
 541                         lr_lineout_gain_texts);
 542
 543 /*
 544  * DACL/R digital volume control:
 545  * from 0 dB to -63.5 in 0.5 dB steps
 546  * Need to be inverted later on:
 547  * 0x00 == 0 dB
 548  * 0x7f == -63.5 dB
 549  */
 550 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 551
 552 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 553         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 554                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 555                 0, 0x7f, 1, dac_digivol_tlv),
 556         SOC_DOUBLE_R("DAC Digital Playback Switch",
 557                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 558         SOC_DOUBLE_R("Line to Line Out Volume",
 559                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 560         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 561         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 562 };
 563
 564 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 565         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 566                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 567 };
 568
 569 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
 570         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 571                 dac33_get_nsample, dac33_set_nsample),
 572         SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
 573                  dac33_get_uthr, dac33_set_uthr),
 574 };
 575
 576 /* Analog bypass */
 577 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 578         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 579
 580 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 581         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 582
 583 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 584         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 585         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 586
 587         SND_SOC_DAPM_INPUT("LINEL"),
 588         SND_SOC_DAPM_INPUT("LINER"),
 589
 590         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 591         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 592
 593         /* Analog bypass */
 594         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 595                                 &dac33_dapm_abypassl_control),
 596         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 597                                 &dac33_dapm_abypassr_control),
 598
 599         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 600                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 601         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 602                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 603
 604         SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
 605 };
 606
 607 static const struct snd_soc_dapm_route audio_map[] = {
 608         /* Analog bypass */
 609         {"Analog Left Bypass", "Switch", "LINEL"},
 610         {"Analog Right Bypass", "Switch", "LINER"},
 611
 612         {"Output Left Amp Power", NULL, "DACL"},
 613         {"Output Right Amp Power", NULL, "DACR"},
 614
 615         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 616         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 617
 618         /* output */
 619         {"LEFT_LO", NULL, "Output Left Amp Power"},
 620         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 621 };
 622
 623 static int dac33_add_widgets(struct snd_soc_codec *codec)
 624 {
 625         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
 626                                   ARRAY_SIZE(dac33_dapm_widgets));
 627
 628         /* set up audio path interconnects */
 629         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 630
 631         return 0;
 632 }
 633
 634 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 635                                 enum snd_soc_bias_level level)
 636 {
 637         int ret;
 638
 639         switch (level) {
 640         case SND_SOC_BIAS_ON:
 641                 dac33_soft_power(codec, 1);
 642                 break;
 643         case SND_SOC_BIAS_PREPARE:
 644                 break;
 645         case SND_SOC_BIAS_STANDBY:
 646                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 647                         /* Coming from OFF, switch on the codec */
 648                         ret = dac33_hard_power(codec, 1);
 649                         if (ret != 0)
 650                                 return ret;
 651
 652                         dac33_init_chip(codec);
 653                 }
 654                 break;
 655         case SND_SOC_BIAS_OFF:
 656                 /* Do not power off, when the codec is already off */
 657                 if (codec->bias_level == SND_SOC_BIAS_OFF)
 658                         return 0;
 659                 ret = dac33_hard_power(codec, 0);
 660                 if (ret != 0)
 661                         return ret;
 662                 break;
 663         }
 664         codec->bias_level = level;
 665
 666         return 0;
 667 }
 668
 669 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 670 {
 671         struct snd_soc_codec *codec = dac33->codec;
 672         unsigned int delay;
 673
 674         switch (dac33->fifo_mode) {
 675         case DAC33_FIFO_MODE1:
 676                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 677                         DAC33_THRREG(dac33->nsample));
 678
 679                 /* Take the timestamps */
 680                 spin_lock_irq(&dac33->lock);
 681                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 682                 dac33->t_stamp1 = dac33->t_stamp2;
 683                 spin_unlock_irq(&dac33->lock);
 684
 685                 dac33_write16(codec, DAC33_PREFILL_MSB,
 686                                 DAC33_THRREG(dac33->alarm_threshold));
 687                 /* Enable Alarm Threshold IRQ with a delay */
 688                 delay = SAMPLES_TO_US(dac33->burst_rate,
 689                                      dac33->alarm_threshold) + 1000;
 690                 usleep_range(delay, delay + 500);
 691                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 692                 break;
 693         case DAC33_FIFO_MODE7:
 694                 /* Take the timestamp */
 695                 spin_lock_irq(&dac33->lock);
 696                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 697                 /* Move back the timestamp with drain time */
 698                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 699                 spin_unlock_irq(&dac33->lock);
 700
 701                 dac33_write16(codec, DAC33_PREFILL_MSB,
 702                                 DAC33_THRREG(MODE7_LTHR));
 703
 704                 /* Enable Upper Threshold IRQ */
 705                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 706                 break;
 707         default:
 708                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 709                                                         dac33->fifo_mode);
 710                 break;
 711         }
 712 }
 713
 714 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 715 {
 716         struct snd_soc_codec *codec = dac33->codec;
 717
 718         switch (dac33->fifo_mode) {
 719         case DAC33_FIFO_MODE1:
 720                 /* Take the timestamp */
 721                 spin_lock_irq(&dac33->lock);
 722                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 723                 spin_unlock_irq(&dac33->lock);
 724
 725                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 726                                 DAC33_THRREG(dac33->nsample));
 727                 break;
 728         case DAC33_FIFO_MODE7:
 729                 /* At the moment we are not using interrupts in mode7 */
 730                 break;
 731         default:
 732                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 733                                                         dac33->fifo_mode);
 734                 break;
 735         }
 736 }
 737
 738 static void dac33_work(struct work_struct *work)
 739 {
 740         struct snd_soc_codec *codec;
 741         struct tlv320dac33_priv *dac33;
 742         u8 reg;
 743
 744         dac33 = container_of(work, struct tlv320dac33_priv, work);
 745         codec = dac33->codec;
 746
 747         mutex_lock(&dac33->mutex);
 748         switch (dac33->state) {
 749         case DAC33_PREFILL:
 750                 dac33->state = DAC33_PLAYBACK;
 751                 dac33_prefill_handler(dac33);
 752                 break;
 753         case DAC33_PLAYBACK:
 754                 dac33_playback_handler(dac33);
 755                 break;
 756         case DAC33_IDLE:
 757                 break;
 758         case DAC33_FLUSH:
 759                 dac33->state = DAC33_IDLE;
 760                 /* Mask all interrupts from dac33 */
 761                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 762
 763                 /* flush fifo */
 764                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 765                 reg |= DAC33_FIFOFLUSH;
 766                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 767                 break;
 768         }
 769         mutex_unlock(&dac33->mutex);
 770 }
 771
 772 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 773 {
 774         struct snd_soc_codec *codec = dev;
 775         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 776
 777         spin_lock(&dac33->lock);
 778         dac33->t_stamp1 = ktime_to_us(ktime_get());
 779         spin_unlock(&dac33->lock);
 780
 781         /* Do not schedule the workqueue in Mode7 */
 782         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 783                 queue_work(dac33->dac33_wq, &dac33->work);
 784
 785         return IRQ_HANDLED;
 786 }
 787
 788 static void dac33_oscwait(struct snd_soc_codec *codec)
 789 {
 790         int timeout = 60;
 791         u8 reg;
 792
 793         do {
 794                 usleep_range(1000, 2000);
 795                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 796         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 797         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 798                 dev_err(codec->dev,
 799                         "internal oscillator calibration failed\n");
 800 }
 801
 802 static int dac33_startup(struct snd_pcm_substream *substream,
 803                            struct snd_soc_dai *dai)
 804 {
 805         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 806         struct snd_soc_codec *codec = rtd->codec;
 807         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 808
 809         /* Stream started, save the substream pointer */
 810         dac33->substream = substream;
 811
 812         return 0;
 813 }
 814
 815 static void dac33_shutdown(struct snd_pcm_substream *substream,
 816                              struct snd_soc_dai *dai)
 817 {
 818         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 819         struct snd_soc_codec *codec = rtd->codec;
 820         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 821
 822         dac33->substream = NULL;
 823
 824         /* Reset the nSample restrictions */
 825         dac33->nsample_min = 0;
 826         dac33->nsample_max = NSAMPLE_MAX;
 827 }
 828
 829 static int dac33_hw_params(struct snd_pcm_substream *substream,
 830                            struct snd_pcm_hw_params *params,
 831                            struct snd_soc_dai *dai)
 832 {
 833         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 834         struct snd_soc_codec *codec = rtd->codec;
 835
 836         /* Check parameters for validity */
 837         switch (params_rate(params)) {
 838         case 44100:
 839         case 48000:
 840                 break;
 841         default:
 842                 dev_err(codec->dev, "unsupported rate %d\n",
 843                         params_rate(params));
 844                 return -EINVAL;
 845         }
 846
 847         switch (params_format(params)) {
 848         case SNDRV_PCM_FORMAT_S16_LE:
 849                 break;
 850         default:
 851                 dev_err(codec->dev, "unsupported format %d\n",
 852                         params_format(params));
 853                 return -EINVAL;
 854         }
 855
 856         return 0;
 857 }
 858
 859 #define CALC_OSCSET(rate, refclk) ( \
 860         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 861 #define CALC_RATIOSET(rate, refclk) ( \
 862         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 863
 864 /*
 865  * tlv320dac33 is strict on the sequence of the register writes, if the register
 866  * writes happens in different order, than dac33 might end up in unknown state.
 867  * Use the known, working sequence of register writes to initialize the dac33.
 868  */
 869 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 870 {
 871         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 872         struct snd_soc_codec *codec = rtd->codec;
 873         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 874         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 875         u8 aictrl_a, aictrl_b, fifoctrl_a;
 876
 877         switch (substream->runtime->rate) {
 878         case 44100:
 879         case 48000:
 880                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 881                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 882                                          dac33->refclk);
 883                 break;
 884         default:
 885                 dev_err(codec->dev, "unsupported rate %d\n",
 886                         substream->runtime->rate);
 887                 return -EINVAL;
 888         }
 889
 890
 891         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 892         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 893         /* Read FIFO control A, and clear FIFO flush bit */
 894         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 895         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 896
 897         fifoctrl_a &= ~DAC33_WIDTH;
 898         switch (substream->runtime->format) {
 899         case SNDRV_PCM_FORMAT_S16_LE:
 900                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 901                 fifoctrl_a |= DAC33_WIDTH;
 902                 break;
 903         default:
 904                 dev_err(codec->dev, "unsupported format %d\n",
 905                         substream->runtime->format);
 906                 return -EINVAL;
 907         }
 908
 909         mutex_lock(&dac33->mutex);
 910
 911         if (!dac33->chip_power) {
 912                 /*
 913                  * Chip is not powered yet.
 914                  * Do the init in the dac33_set_bias_level later.
 915                  */
 916                 mutex_unlock(&dac33->mutex);
 917                 return 0;
 918         }
 919
 920         dac33_soft_power(codec, 0);
 921         dac33_soft_power(codec, 1);
 922
 923         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 924         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 925
 926         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 927         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 928
 929         /* calib time: 128 is a nice number ;) */
 930         dac33_write(codec, DAC33_CALIB_TIME, 128);
 931
 932         /* adjustment treshold & step */
 933         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 934                                                  DAC33_ADJSTEP(1));
 935
 936         /* div=4 / gain=1 / div */
 937         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 938
 939         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 940         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 941         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 942
 943         dac33_oscwait(codec);
 944
 945         if (dac33->fifo_mode) {
 946                 /* Generic for all FIFO modes */
 947                 /* 50-51 : ASRC Control registers */
 948                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 949                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 950
 951                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 952                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 953
 954                 /* Set interrupts to high active */
 955                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 956         } else {
 957                 /* FIFO bypass mode */
 958                 /* 50-51 : ASRC Control registers */
 959                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 960                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 961         }
 962
 963         /* Interrupt behaviour configuration */
 964         switch (dac33->fifo_mode) {
 965         case DAC33_FIFO_MODE1:
 966                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 967                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 968                 break;
 969         case DAC33_FIFO_MODE7:
 970                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 971                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 972                 break;
 973         default:
 974                 /* in FIFO bypass mode, the interrupts are not used */
 975                 break;
 976         }
 977
 978         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 979
 980         switch (dac33->fifo_mode) {
 981         case DAC33_FIFO_MODE1:
 982                 /*
 983                  * For mode1:
 984                  * Disable the FIFO bypass (Enable the use of FIFO)
 985                  * Select nSample mode
 986                  * BCLK is only running when data is needed by DAC33
 987                  */
 988                 fifoctrl_a &= ~DAC33_FBYPAS;
 989                 fifoctrl_a &= ~DAC33_FAUTO;
 990                 if (dac33->keep_bclk)
 991                         aictrl_b |= DAC33_BCLKON;
 992                 else
 993                         aictrl_b &= ~DAC33_BCLKON;
 994                 break;
 995         case DAC33_FIFO_MODE7:
 996                 /*
 997                  * For mode1:
 998                  * Disable the FIFO bypass (Enable the use of FIFO)
 999                  * Select Threshold mode
1000                  * BCLK is only running when data is needed by DAC33
1001                  */
1002                 fifoctrl_a &= ~DAC33_FBYPAS;
1003                 fifoctrl_a |= DAC33_FAUTO;
1004                 if (dac33->keep_bclk)
1005                         aictrl_b |= DAC33_BCLKON;
1006                 else
1007                         aictrl_b &= ~DAC33_BCLKON;
1008                 break;
1009         default:
1010                 /*
1011                  * For FIFO bypass mode:
1012                  * Enable the FIFO bypass (Disable the FIFO use)
1013                  * Set the BCLK as continous
1014                  */
1015                 fifoctrl_a |= DAC33_FBYPAS;
1016                 aictrl_b |= DAC33_BCLKON;
1017                 break;
1018         }
1019
1020         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1021         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1022         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1023
1024         /*
1025          * BCLK divide ratio
1026          * 0: 1.5
1027          * 1: 1
1028          * 2: 2
1029          * ...
1030          * 254: 254
1031          * 255: 255
1032          */
1033         if (dac33->fifo_mode)
1034                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1035                                                         dac33->burst_bclkdiv);
1036         else
1037                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1038
1039         switch (dac33->fifo_mode) {
1040         case DAC33_FIFO_MODE1:
1041                 dac33_write16(codec, DAC33_ATHR_MSB,
1042                               DAC33_THRREG(dac33->alarm_threshold));
1043                 break;
1044         case DAC33_FIFO_MODE7:
1045                 /*
1046                  * Configure the threshold levels, and leave 10 sample space
1047                  * at the bottom, and also at the top of the FIFO
1048                  */
1049                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1050                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1051                 break;
1052         default:
1053                 break;
1054         }
1055
1056         mutex_unlock(&dac33->mutex);
1057
1058         return 0;
1059 }
1060
1061 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1062 {
1063         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1064         struct snd_soc_codec *codec = rtd->codec;
1065         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1066         unsigned int period_size = substream->runtime->period_size;
1067         unsigned int rate = substream->runtime->rate;
1068         unsigned int nsample_limit;
1069
1070         /* In bypass mode we don't need to calculate */
1071         if (!dac33->fifo_mode)
1072                 return;
1073
1074         switch (dac33->fifo_mode) {
1075         case DAC33_FIFO_MODE1:
1076                 /* Number of samples under i2c latency */
1077                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1078                                                 dac33->mode1_latency);
1079                 if (dac33->auto_fifo_config) {
1080                         if (period_size <= dac33->alarm_threshold)
1081                                 /*
1082                                  * Configure nSamaple to number of periods,
1083                                  * which covers the latency requironment.
1084                                  */
1085                                 dac33->nsample = period_size *
1086                                        ((dac33->alarm_threshold / period_size) +
1087                                        (dac33->alarm_threshold % period_size ?
1088                                        1 : 0));
1089                         else
1090                                 dac33->nsample = period_size;
1091                 } else {
1092                         /* nSample time shall not be shorter than i2c latency */
1093                         dac33->nsample_min = dac33->alarm_threshold;
1094                         /*
1095                          * nSample should not be bigger than alsa buffer minus
1096                          * size of one period to avoid overruns
1097                          */
1098                         dac33->nsample_max = substream->runtime->buffer_size -
1099                                                 period_size;
1100                         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1101                                         dac33->alarm_threshold;
1102                         if (dac33->nsample_max > nsample_limit)
1103                                 dac33->nsample_max = nsample_limit;
1104
1105                         /* Correct the nSample if it is outside of the ranges */
1106                         if (dac33->nsample < dac33->nsample_min)
1107                                 dac33->nsample = dac33->nsample_min;
1108                         if (dac33->nsample > dac33->nsample_max)
1109                                 dac33->nsample = dac33->nsample_max;
1110                 }
1111
1112                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1113                                                       dac33->nsample);
1114                 dac33->t_stamp1 = 0;
1115                 dac33->t_stamp2 = 0;
1116                 break;
1117         case DAC33_FIFO_MODE7:
1118                 if (dac33->auto_fifo_config) {
1119                         dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1120                                         period_size,
1121                                         rate,
1122                                         dac33->burst_rate) + 9;
1123                         if (dac33->uthr > MODE7_UTHR)
1124                                 dac33->uthr = MODE7_UTHR;
1125                         if (dac33->uthr < (MODE7_LTHR + 10))
1126                                 dac33->uthr = (MODE7_LTHR + 10);
1127                 }
1128                 dac33->mode7_us_to_lthr =
1129                                 SAMPLES_TO_US(substream->runtime->rate,
1130                                         dac33->uthr - MODE7_LTHR + 1);
1131                 dac33->t_stamp1 = 0;
1132                 break;
1133         default:
1134                 break;
1135         }
1136
1137 }
1138
1139 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1140                              struct snd_soc_dai *dai)
1141 {
1142         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1143         struct snd_soc_codec *codec = rtd->codec;
1144         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1145         int ret = 0;
1146
1147         switch (cmd) {
1148         case SNDRV_PCM_TRIGGER_START:
1149         case SNDRV_PCM_TRIGGER_RESUME:
1150         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1151                 if (dac33->fifo_mode) {
1152                         dac33->state = DAC33_PREFILL;
1153                         queue_work(dac33->dac33_wq, &dac33->work);
1154                 }
1155                 break;
1156         case SNDRV_PCM_TRIGGER_STOP:
1157         case SNDRV_PCM_TRIGGER_SUSPEND:
1158         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1159                 if (dac33->fifo_mode) {
1160                         dac33->state = DAC33_FLUSH;
1161                         queue_work(dac33->dac33_wq, &dac33->work);
1162                 }
1163                 break;
1164         default:
1165                 ret = -EINVAL;
1166         }
1167
1168         return ret;
1169 }
1170
1171 static snd_pcm_sframes_t dac33_dai_delay(
1172                         struct snd_pcm_substream *substream,
1173                         struct snd_soc_dai *dai)
1174 {
1175         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1176         struct snd_soc_codec *codec = rtd->codec;
1177         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1178         unsigned long long t0, t1, t_now;
1179         unsigned int time_delta, uthr;
1180         int samples_out, samples_in, samples;
1181         snd_pcm_sframes_t delay = 0;
1182
1183         switch (dac33->fifo_mode) {
1184         case DAC33_FIFO_BYPASS:
1185                 break;
1186         case DAC33_FIFO_MODE1:
1187                 spin_lock(&dac33->lock);
1188                 t0 = dac33->t_stamp1;
1189                 t1 = dac33->t_stamp2;
1190                 spin_unlock(&dac33->lock);
1191                 t_now = ktime_to_us(ktime_get());
1192
1193                 /* We have not started to fill the FIFO yet, delay is 0 */
1194                 if (!t1)
1195                         goto out;
1196
1197                 if (t0 > t1) {
1198                         /*
1199                          * Phase 1:
1200                          * After Alarm threshold, and before nSample write
1201                          */
1202                         time_delta = t_now - t0;
1203                         samples_out = time_delta ? US_TO_SAMPLES(
1204                                                 substream->runtime->rate,
1205                                                 time_delta) : 0;
1206
1207                         if (likely(dac33->alarm_threshold > samples_out))
1208                                 delay = dac33->alarm_threshold - samples_out;
1209                         else
1210                                 delay = 0;
1211                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1212                         /*
1213                          * Phase 2:
1214                          * After nSample write (during burst operation)
1215                          */
1216                         time_delta = t_now - t0;
1217                         samples_out = time_delta ? US_TO_SAMPLES(
1218                                                 substream->runtime->rate,
1219                                                 time_delta) : 0;
1220
1221                         time_delta = t_now - t1;
1222                         samples_in = time_delta ? US_TO_SAMPLES(
1223                                                 dac33->burst_rate,
1224                                                 time_delta) : 0;
1225
1226                         samples = dac33->alarm_threshold;
1227                         samples += (samples_in - samples_out);
1228
1229                         if (likely(samples > 0))
1230                                 delay = samples;
1231                         else
1232                                 delay = 0;
1233                 } else {
1234                         /*
1235                          * Phase 3:
1236                          * After burst operation, before next alarm threshold
1237                          */
1238                         time_delta = t_now - t0;
1239                         samples_out = time_delta ? US_TO_SAMPLES(
1240                                                 substream->runtime->rate,
1241                                                 time_delta) : 0;
1242
1243                         samples_in = dac33->nsample;
1244                         samples = dac33->alarm_threshold;
1245                         samples += (samples_in - samples_out);
1246
1247                         if (likely(samples > 0))
1248                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1249                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1250                         else
1251                                 delay = 0;
1252                 }
1253                 break;
1254         case DAC33_FIFO_MODE7:
1255                 spin_lock(&dac33->lock);
1256                 t0 = dac33->t_stamp1;
1257                 uthr = dac33->uthr;
1258                 spin_unlock(&dac33->lock);
1259                 t_now = ktime_to_us(ktime_get());
1260
1261                 /* We have not started to fill the FIFO yet, delay is 0 */
1262                 if (!t0)
1263                         goto out;
1264
1265                 if (t_now <= t0) {
1266                         /*
1267                          * Either the timestamps are messed or equal. Report
1268                          * maximum delay
1269                          */
1270                         delay = uthr;
1271                         goto out;
1272                 }
1273
1274                 time_delta = t_now - t0;
1275                 if (time_delta <= dac33->mode7_us_to_lthr) {
1276                         /*
1277                         * Phase 1:
1278                         * After burst (draining phase)
1279                         */
1280                         samples_out = US_TO_SAMPLES(
1281                                         substream->runtime->rate,
1282                                         time_delta);
1283
1284                         if (likely(uthr > samples_out))
1285                                 delay = uthr - samples_out;
1286                         else
1287                                 delay = 0;
1288                 } else {
1289                         /*
1290                         * Phase 2:
1291                         * During burst operation
1292                         */
1293                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1294
1295                         samples_out = US_TO_SAMPLES(
1296                                         substream->runtime->rate,
1297                                         time_delta);
1298                         samples_in = US_TO_SAMPLES(
1299                                         dac33->burst_rate,
1300                                         time_delta);
1301                         delay = MODE7_LTHR + samples_in - samples_out;
1302
1303                         if (unlikely(delay > uthr))
1304                                 delay = uthr;
1305                 }
1306                 break;
1307         default:
1308                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1309                                                         dac33->fifo_mode);
1310                 break;
1311         }
1312 out:
1313         return delay;
1314 }
1315
1316 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1317                 int clk_id, unsigned int freq, int dir)
1318 {
1319         struct snd_soc_codec *codec = codec_dai->codec;
1320         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1321         u8 ioc_reg, asrcb_reg;
1322
1323         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1324         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1325         switch (clk_id) {
1326         case TLV320DAC33_MCLK:
1327                 ioc_reg |= DAC33_REFSEL;
1328                 asrcb_reg |= DAC33_SRCREFSEL;
1329                 break;
1330         case TLV320DAC33_SLEEPCLK:
1331                 ioc_reg &= ~DAC33_REFSEL;
1332                 asrcb_reg &= ~DAC33_SRCREFSEL;
1333                 break;
1334         default:
1335                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1336                 break;
1337         }
1338         dac33->refclk = freq;
1339
1340         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1341         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1342
1343         return 0;
1344 }
1345
1346 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1347                              unsigned int fmt)
1348 {
1349         struct snd_soc_codec *codec = codec_dai->codec;
1350         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1351         u8 aictrl_a, aictrl_b;
1352
1353         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1354         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1355         /* set master/slave audio interface */
1356         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1357         case SND_SOC_DAIFMT_CBM_CFM:
1358                 /* Codec Master */
1359                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1360                 break;
1361         case SND_SOC_DAIFMT_CBS_CFS:
1362                 /* Codec Slave */
1363                 if (dac33->fifo_mode) {
1364                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1365                         return -EINVAL;
1366                 } else
1367                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1368                 break;
1369         default:
1370                 return -EINVAL;
1371         }
1372
1373         aictrl_a &= ~DAC33_AFMT_MASK;
1374         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1375         case SND_SOC_DAIFMT_I2S:
1376                 aictrl_a |= DAC33_AFMT_I2S;
1377                 break;
1378         case SND_SOC_DAIFMT_DSP_A:
1379                 aictrl_a |= DAC33_AFMT_DSP;
1380                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1381                 aictrl_b |= DAC33_DATA_DELAY(0);
1382                 break;
1383         case SND_SOC_DAIFMT_RIGHT_J:
1384                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1385                 break;
1386         case SND_SOC_DAIFMT_LEFT_J:
1387                 aictrl_a |= DAC33_AFMT_LEFT_J;
1388                 break;
1389         default:
1390                 dev_err(codec->dev, "Unsupported format (%u)\n",
1391                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1392                 return -EINVAL;
1393         }
1394
1395         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1396         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1397
1398         return 0;
1399 }
1400
1401 static int dac33_soc_probe(struct snd_soc_codec *codec)
1402 {
1403         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1404         int ret = 0;
1405
1406         codec->control_data = dac33->control_data;
1407         codec->hw_write = (hw_write_t) i2c_master_send;
1408         codec->idle_bias_off = 1;
1409         dac33->codec = codec;
1410
1411         /* Read the tlv320dac33 ID registers */
1412         ret = dac33_hard_power(codec, 1);
1413         if (ret != 0) {
1414                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1415                 goto err_power;
1416         }
1417         dac33_read_id(codec);
1418         dac33_hard_power(codec, 0);
1419
1420         /* Check if the IRQ number is valid and request it */
1421         if (dac33->irq >= 0) {
1422                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1423                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1424                                   codec->name, codec);
1425                 if (ret < 0) {
1426                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1427                                                 dac33->irq, ret);
1428                         dac33->irq = -1;
1429                 }
1430                 if (dac33->irq != -1) {
1431                         /* Setup work queue */
1432                         dac33->dac33_wq =
1433                                 create_singlethread_workqueue("tlv320dac33");
1434                         if (dac33->dac33_wq == NULL) {
1435                                 free_irq(dac33->irq, codec);
1436                                 return -ENOMEM;
1437                         }
1438
1439                         INIT_WORK(&dac33->work, dac33_work);
1440                 }
1441         }
1442
1443         snd_soc_add_controls(codec, dac33_snd_controls,
1444                              ARRAY_SIZE(dac33_snd_controls));
1445         /* Only add the FIFO controls, if we have valid IRQ number */
1446         if (dac33->irq >= 0) {
1447                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1448                                      ARRAY_SIZE(dac33_mode_snd_controls));
1449                 /* FIFO usage controls only, if autoio config is not selected */
1450                 if (!dac33->auto_fifo_config)
1451                         snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1452                                         ARRAY_SIZE(dac33_fifo_snd_controls));
1453         }
1454         dac33_add_widgets(codec);
1455
1456 err_power:
1457         return ret;
1458 }
1459
1460 static int dac33_soc_remove(struct snd_soc_codec *codec)
1461 {
1462         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1463
1464         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1465
1466         if (dac33->irq >= 0) {
1467                 free_irq(dac33->irq, dac33->codec);
1468                 destroy_workqueue(dac33->dac33_wq);
1469         }
1470         return 0;
1471 }
1472
1473 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1474 {
1475         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1476
1477         return 0;
1478 }
1479
1480 static int dac33_soc_resume(struct snd_soc_codec *codec)
1481 {
1482         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1483
1484         return 0;
1485 }
1486
1487 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1488         .read = dac33_read_reg_cache,
1489         .write = dac33_write_locked,
1490         .set_bias_level = dac33_set_bias_level,
1491         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1492         .reg_word_size = sizeof(u8),
1493         .reg_cache_default = dac33_reg,
1494         .probe = dac33_soc_probe,
1495         .remove = dac33_soc_remove,
1496         .suspend = dac33_soc_suspend,
1497         .resume = dac33_soc_resume,
1498 };
1499
1500 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1501                          SNDRV_PCM_RATE_48000)
1502 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1503
1504 static struct snd_soc_dai_ops dac33_dai_ops = {
1505         .startup        = dac33_startup,
1506         .shutdown       = dac33_shutdown,
1507         .hw_params      = dac33_hw_params,
1508         .trigger        = dac33_pcm_trigger,
1509         .delay          = dac33_dai_delay,
1510         .set_sysclk     = dac33_set_dai_sysclk,
1511         .set_fmt        = dac33_set_dai_fmt,
1512 };
1513
1514 static struct snd_soc_dai_driver dac33_dai = {
1515         .name = "tlv320dac33-hifi",
1516         .playback = {
1517                 .stream_name = "Playback",
1518                 .channels_min = 2,
1519                 .channels_max = 2,
1520                 .rates = DAC33_RATES,
1521                 .formats = DAC33_FORMATS,},
1522         .ops = &dac33_dai_ops,
1523 };
1524
1525 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1526                                      const struct i2c_device_id *id)
1527 {
1528         struct tlv320dac33_platform_data *pdata;
1529         struct tlv320dac33_priv *dac33;
1530         int ret, i;
1531
1532         if (client->dev.platform_data == NULL) {
1533                 dev_err(&client->dev, "Platform data not set\n");
1534                 return -ENODEV;
1535         }
1536         pdata = client->dev.platform_data;
1537
1538         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1539         if (dac33 == NULL)
1540                 return -ENOMEM;
1541
1542         dac33->control_data = client;
1543         mutex_init(&dac33->mutex);
1544         spin_lock_init(&dac33->lock);
1545
1546         i2c_set_clientdata(client, dac33);
1547
1548         dac33->power_gpio = pdata->power_gpio;
1549         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1550         /* Pre calculate the burst rate */
1551         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1552         dac33->keep_bclk = pdata->keep_bclk;
1553         dac33->auto_fifo_config = pdata->auto_fifo_config;
1554         dac33->mode1_latency = pdata->mode1_latency;
1555         if (!dac33->mode1_latency)
1556                 dac33->mode1_latency = 10000; /* 10ms */
1557         dac33->irq = client->irq;
1558         dac33->nsample = NSAMPLE_MAX;
1559         dac33->nsample_max = NSAMPLE_MAX;
1560         dac33->uthr = MODE7_UTHR;
1561         /* Disable FIFO use by default */
1562         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1563
1564         /* Check if the reset GPIO number is valid and request it */
1565         if (dac33->power_gpio >= 0) {
1566                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1567                 if (ret < 0) {
1568                         dev_err(&client->dev,
1569                                 "Failed to request reset GPIO (%d)\n",
1570                                 dac33->power_gpio);
1571                         goto err_gpio;
1572                 }
1573                 gpio_direction_output(dac33->power_gpio, 0);
1574         }
1575
1576         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1577                 dac33->supplies[i].supply = dac33_supply_names[i];
1578
1579         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1580                                  dac33->supplies);
1581
1582         if (ret != 0) {
1583                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1584                 goto err_get;
1585         }
1586
1587         ret = snd_soc_register_codec(&client->dev,
1588                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1589         if (ret < 0)
1590                 goto err_register;
1591
1592         return ret;
1593 err_register:
1594         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1595 err_get:
1596         if (dac33->power_gpio >= 0)
1597                 gpio_free(dac33->power_gpio);
1598 err_gpio:
1599         kfree(dac33);
1600         return ret;
1601 }
1602
1603 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1604 {
1605         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1606
1607         if (unlikely(dac33->chip_power))
1608                 dac33_hard_power(dac33->codec, 0);
1609
1610         if (dac33->power_gpio >= 0)
1611                 gpio_free(dac33->power_gpio);
1612
1613         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1614
1615         snd_soc_unregister_codec(&client->dev);
1616         kfree(dac33);
1617
1618         return 0;
1619 }
1620
1621 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1622         {
1623                 .name = "tlv320dac33",
1624                 .driver_data = 0,
1625         },
1626         { },
1627 };
1628
1629 static struct i2c_driver tlv320dac33_i2c_driver = {
1630         .driver = {
1631                 .name = "tlv320dac33-codec",
1632                 .owner = THIS_MODULE,
1633         },
1634         .probe          = dac33_i2c_probe,
1635         .remove         = __devexit_p(dac33_i2c_remove),
1636         .id_table       = tlv320dac33_i2c_id,
1637 };
1638
1639 static int __init dac33_module_init(void)
1640 {
1641         int r;
1642         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1643         if (r < 0) {
1644                 printk(KERN_ERR "DAC33: driver registration failed\n");
1645                 return r;
1646         }
1647         return 0;
1648 }
1649 module_init(dac33_module_init);
1650
1651 static void __exit dac33_module_exit(void)
1652 {
1653         i2c_del_driver(&tlv320dac33_i2c_driver);
1654 }
1655 module_exit(dac33_module_exit);
1656
1657
1658 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1659 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1660 MODULE_LICENSE("GPL");