2 * Au12x0/Au1550 PSC ALSA ASoC audio support.
4 * (c) 2007-2009 MSC Vertriebsges.m.b.H.,
5 * Manuel Lauss <manuel.lauss@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Au1xxx-PSC AC97 glue.
13 * NOTE: all of these drivers can only work with a SINGLE instance
14 * of a PSC. Multiple independent audio devices are impossible
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/mutex.h>
23 #include <linux/suspend.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/initval.h>
27 #include <sound/soc.h>
28 #include <asm/mach-au1x00/au1000.h>
29 #include <asm/mach-au1x00/au1xxx_psc.h>
33 /* how often to retry failed codec register reads/writes */
34 #define AC97_RW_RETRIES 5
37 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
40 SNDRV_PCM_RATE_8000_48000
43 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)
45 #define AC97PCR_START(stype) \
46 ((stype) == PCM_TX ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
47 #define AC97PCR_STOP(stype) \
48 ((stype) == PCM_TX ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
49 #define AC97PCR_CLRFIFO(stype) \
50 ((stype) == PCM_TX ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
52 #define AC97STAT_BUSY(stype) \
53 ((stype) == PCM_TX ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
55 /* instance data. There can be only one, MacLeod!!!! */
56 static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
58 /* AC97 controller reads codec register */
59 static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
63 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
64 unsigned short retry, tmo;
67 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
70 retry = AC97_RW_RETRIES;
72 mutex_lock(&pscdata->lock);
74 au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
79 while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD))
83 data = au_readl(AC97_CDC(pscdata));
85 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
88 mutex_unlock(&pscdata->lock);
90 if (reg != ((data >> 16) & 0x7f))
91 tmo = 1; /* wrong register, try again */
93 } while (--retry && !tmo);
95 return retry ? data & 0xffff : 0xffff;
98 /* AC97 controller writes to codec register */
99 static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
103 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
104 unsigned int tmo, retry;
106 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
109 retry = AC97_RW_RETRIES;
111 mutex_lock(&pscdata->lock);
113 au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
118 while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD))
122 au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
125 mutex_unlock(&pscdata->lock);
126 } while (--retry && !tmo);
129 /* AC97 controller asserts a warm reset */
130 static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
133 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
135 au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
138 au_writel(0, AC97_RST(pscdata));
142 static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
145 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
148 /* disable PSC during cold reset */
149 au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
151 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
154 /* issue cold reset */
155 au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
158 au_writel(0, AC97_RST(pscdata));
162 au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
165 /* wait for PSC to indicate it's ready */
167 while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
171 printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
175 /* enable the ac97 function */
176 au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
179 /* wait for AC97 core to become ready */
181 while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
184 printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
187 /* AC97 controller operations */
188 struct snd_ac97_bus_ops soc_ac97_ops = {
189 .read = au1xpsc_ac97_read,
190 .write = au1xpsc_ac97_write,
191 .reset = au1xpsc_ac97_cold_reset,
192 .warm_reset = au1xpsc_ac97_warm_reset,
194 EXPORT_SYMBOL_GPL(soc_ac97_ops);
196 static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
197 struct snd_pcm_hw_params *params,
198 struct snd_soc_dai *dai)
201 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
202 unsigned long r, ro, stat;
203 int chans, stype = SUBSTREAM_TYPE(substream);
205 chans = params_channels(params);
207 r = ro = au_readl(AC97_CFG(pscdata));
208 stat = au_readl(AC97_STAT(pscdata));
210 /* already active? */
211 if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
212 /* reject parameters not currently set up */
213 if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
214 (pscdata->rate != params_rate(params)))
218 /* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
219 r &= ~PSC_AC97CFG_LEN_MASK;
220 r |= PSC_AC97CFG_SET_LEN(params->msbits);
222 /* channels: enable slots for front L/R channel */
223 if (stype == PCM_TX) {
224 r &= ~PSC_AC97CFG_TXSLOT_MASK;
225 r |= PSC_AC97CFG_TXSLOT_ENA(3);
226 r |= PSC_AC97CFG_TXSLOT_ENA(4);
228 r &= ~PSC_AC97CFG_RXSLOT_MASK;
229 r |= PSC_AC97CFG_RXSLOT_ENA(3);
230 r |= PSC_AC97CFG_RXSLOT_ENA(4);
233 /* do we need to poke the hardware? */
237 /* ac97 engine is about to be disabled */
238 mutex_lock(&pscdata->lock);
240 /* disable AC97 device controller first... */
241 au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
244 /* ...wait for it... */
245 while (au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)
246 asm volatile ("nop");
248 /* ...write config... */
249 au_writel(r, AC97_CFG(pscdata));
252 /* ...enable the AC97 controller again... */
253 au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
256 /* ...and wait for ready bit */
257 while (!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR))
258 asm volatile ("nop");
260 mutex_unlock(&pscdata->lock);
263 pscdata->rate = params_rate(params);
270 static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
271 int cmd, struct snd_soc_dai *dai)
274 struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
275 int ret, stype = SUBSTREAM_TYPE(substream);
280 case SNDRV_PCM_TRIGGER_START:
281 case SNDRV_PCM_TRIGGER_RESUME:
282 au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
284 au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
287 case SNDRV_PCM_TRIGGER_STOP:
288 case SNDRV_PCM_TRIGGER_SUSPEND:
289 au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
292 while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
293 asm volatile ("nop");
295 au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
305 static int au1xpsc_ac97_probe(struct platform_device *pdev,
306 struct snd_soc_dai *dai)
312 if (au1xpsc_ac97_workdata)
315 au1xpsc_ac97_workdata =
316 kzalloc(sizeof(struct au1xpsc_audio_data), GFP_KERNEL);
317 if (!au1xpsc_ac97_workdata)
320 mutex_init(&au1xpsc_ac97_workdata->lock);
322 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
329 au1xpsc_ac97_workdata->ioarea =
330 request_mem_region(r->start, r->end - r->start + 1,
332 if (!au1xpsc_ac97_workdata->ioarea)
335 au1xpsc_ac97_workdata->mmio = ioremap(r->start, 0xffff);
336 if (!au1xpsc_ac97_workdata->mmio)
339 /* configuration: max dma trigger threshold, enable ac97 */
340 au1xpsc_ac97_workdata->cfg = PSC_AC97CFG_RT_FIFO8 |
341 PSC_AC97CFG_TT_FIFO8 |
342 PSC_AC97CFG_DE_ENABLE;
344 /* preserve PSC clock source set up by platform (dev.platform_data
345 * is already occupied by soc layer)
347 sel = au_readl(PSC_SEL(au1xpsc_ac97_workdata)) & PSC_SEL_CLK_MASK;
348 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
350 au_writel(0, PSC_SEL(au1xpsc_ac97_workdata));
352 au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(au1xpsc_ac97_workdata));
354 /* next up: cold reset. Dont check for PSC-ready now since
355 * there may not be any codec clock yet.
361 release_resource(au1xpsc_ac97_workdata->ioarea);
362 kfree(au1xpsc_ac97_workdata->ioarea);
364 kfree(au1xpsc_ac97_workdata);
365 au1xpsc_ac97_workdata = NULL;
369 static void au1xpsc_ac97_remove(struct platform_device *pdev,
370 struct snd_soc_dai *dai)
372 /* disable PSC completely */
373 au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
375 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
378 iounmap(au1xpsc_ac97_workdata->mmio);
379 release_resource(au1xpsc_ac97_workdata->ioarea);
380 kfree(au1xpsc_ac97_workdata->ioarea);
381 kfree(au1xpsc_ac97_workdata);
382 au1xpsc_ac97_workdata = NULL;
385 static int au1xpsc_ac97_suspend(struct snd_soc_dai *dai)
387 /* save interesting registers and disable PSC */
388 au1xpsc_ac97_workdata->pm[0] =
389 au_readl(PSC_SEL(au1xpsc_ac97_workdata));
391 au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
393 au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata));
399 static int au1xpsc_ac97_resume(struct snd_soc_dai *dai)
401 /* restore PSC clock config */
402 au_writel(au1xpsc_ac97_workdata->pm[0] | PSC_SEL_PS_AC97MODE,
403 PSC_SEL(au1xpsc_ac97_workdata));
406 /* after this point the ac97 core will cold-reset the codec.
407 * During cold-reset the PSC is reinitialized and the last
408 * configuration set up in hw_params() is restored.
413 static struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
414 .trigger = au1xpsc_ac97_trigger,
415 .hw_params = au1xpsc_ac97_hw_params,
418 struct snd_soc_dai au1xpsc_ac97_dai = {
419 .name = "au1xpsc_ac97",
421 .probe = au1xpsc_ac97_probe,
422 .remove = au1xpsc_ac97_remove,
423 .suspend = au1xpsc_ac97_suspend,
424 .resume = au1xpsc_ac97_resume,
427 .formats = AC97_FMTS,
433 .formats = AC97_FMTS,
437 .ops = &au1xpsc_ac97_dai_ops,
439 EXPORT_SYMBOL_GPL(au1xpsc_ac97_dai);
441 static int __init au1xpsc_ac97_init(void)
443 au1xpsc_ac97_workdata = NULL;
444 return snd_soc_register_dai(&au1xpsc_ac97_dai);
447 static void __exit au1xpsc_ac97_exit(void)
449 snd_soc_unregister_dai(&au1xpsc_ac97_dai);
452 module_init(au1xpsc_ac97_init);
453 module_exit(au1xpsc_ac97_exit);
455 MODULE_LICENSE("GPL");
456 MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
457 MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");