sound/soc/atmel/atmel_ssc_dai.c

   1 /*
   2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
   3  *
   4  * Copyright (C) 2005 SAN People
   5  * Copyright (C) 2008 Atmel
   6  *
   7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
   8  *         ATMEL CORP.
   9  *
  10  * Based on at91-ssc.c by
  11  * Frank Mandarino <fmandarino@endrelia.com>
  12  * Based on pxa2xx Platform drivers by
  13  * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/module.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/device.h>
  34 #include <linux/delay.h>
  35 #include <linux/clk.h>
  36 #include <linux/atmel_pdc.h>
  37
  38 #include <linux/atmel-ssc.h>
  39 #include <sound/core.h>
  40 #include <sound/pcm.h>
  41 #include <sound/pcm_params.h>
  42 #include <sound/initval.h>
  43 #include <sound/soc.h>
  44
  45 #include <mach/hardware.h>
  46
  47 #include "atmel-pcm.h"
  48 #include "atmel_ssc_dai.h"
  49
  50
  51 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
  52 #define NUM_SSC_DEVICES         1
  53 #else
  54 #define NUM_SSC_DEVICES         3
  55 #endif
  56
  57 /*
  58  * SSC PDC registers required by the PCM DMA engine.
  59  */
  60 static struct atmel_pdc_regs pdc_tx_reg = {
  61         .xpr            = ATMEL_PDC_TPR,
  62         .xcr            = ATMEL_PDC_TCR,
  63         .xnpr           = ATMEL_PDC_TNPR,
  64         .xncr           = ATMEL_PDC_TNCR,
  65 };
  66
  67 static struct atmel_pdc_regs pdc_rx_reg = {
  68         .xpr            = ATMEL_PDC_RPR,
  69         .xcr            = ATMEL_PDC_RCR,
  70         .xnpr           = ATMEL_PDC_RNPR,
  71         .xncr           = ATMEL_PDC_RNCR,
  72 };
  73
  74 /*
  75  * SSC & PDC status bits for transmit and receive.
  76  */
  77 static struct atmel_ssc_mask ssc_tx_mask = {
  78         .ssc_enable     = SSC_BIT(CR_TXEN),
  79         .ssc_disable    = SSC_BIT(CR_TXDIS),
  80         .ssc_endx       = SSC_BIT(SR_ENDTX),
  81         .ssc_endbuf     = SSC_BIT(SR_TXBUFE),
  82         .pdc_enable     = ATMEL_PDC_TXTEN,
  83         .pdc_disable    = ATMEL_PDC_TXTDIS,
  84 };
  85
  86 static struct atmel_ssc_mask ssc_rx_mask = {
  87         .ssc_enable     = SSC_BIT(CR_RXEN),
  88         .ssc_disable    = SSC_BIT(CR_RXDIS),
  89         .ssc_endx       = SSC_BIT(SR_ENDRX),
  90         .ssc_endbuf     = SSC_BIT(SR_RXBUFF),
  91         .pdc_enable     = ATMEL_PDC_RXTEN,
  92         .pdc_disable    = ATMEL_PDC_RXTDIS,
  93 };
  94
  95
  96 /*
  97  * DMA parameters.
  98  */
  99 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
 100         {{
 101         .name           = "SSC0 PCM out",
 102         .pdc            = &pdc_tx_reg,
 103         .mask           = &ssc_tx_mask,
 104         },
 105         {
 106         .name           = "SSC0 PCM in",
 107         .pdc            = &pdc_rx_reg,
 108         .mask           = &ssc_rx_mask,
 109         } },
 110 #if NUM_SSC_DEVICES == 3
 111         {{
 112         .name           = "SSC1 PCM out",
 113         .pdc            = &pdc_tx_reg,
 114         .mask           = &ssc_tx_mask,
 115         },
 116         {
 117         .name           = "SSC1 PCM in",
 118         .pdc            = &pdc_rx_reg,
 119         .mask           = &ssc_rx_mask,
 120         } },
 121         {{
 122         .name           = "SSC2 PCM out",
 123         .pdc            = &pdc_tx_reg,
 124         .mask           = &ssc_tx_mask,
 125         },
 126         {
 127         .name           = "SSC2 PCM in",
 128         .pdc            = &pdc_rx_reg,
 129         .mask           = &ssc_rx_mask,
 130         } },
 131 #endif
 132 };
 133
 134
 135 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
 136         {
 137         .name           = "ssc0",
 138         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
 139         .dir_mask       = SSC_DIR_MASK_UNUSED,
 140         .initialized    = 0,
 141         },
 142 #if NUM_SSC_DEVICES == 3
 143         {
 144         .name           = "ssc1",
 145         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
 146         .dir_mask       = SSC_DIR_MASK_UNUSED,
 147         .initialized    = 0,
 148         },
 149         {
 150         .name           = "ssc2",
 151         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
 152         .dir_mask       = SSC_DIR_MASK_UNUSED,
 153         .initialized    = 0,
 154         },
 155 #endif
 156 };
 157
 158
 159 /*
 160  * SSC interrupt handler.  Passes PDC interrupts to the DMA
 161  * interrupt handler in the PCM driver.
 162  */
 163 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
 164 {
 165         struct atmel_ssc_info *ssc_p = dev_id;
 166         struct atmel_pcm_dma_params *dma_params;
 167         u32 ssc_sr;
 168         u32 ssc_substream_mask;
 169         int i;
 170
 171         ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
 172                         & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
 173
 174         /*
 175          * Loop through the substreams attached to this SSC.  If
 176          * a DMA-related interrupt occurred on that substream, call
 177          * the DMA interrupt handler function, if one has been
 178          * registered in the dma_params structure by the PCM driver.
 179          */
 180         for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
 181                 dma_params = ssc_p->dma_params[i];
 182
 183                 if ((dma_params != NULL) &&
 184                         (dma_params->dma_intr_handler != NULL)) {
 185                         ssc_substream_mask = (dma_params->mask->ssc_endx |
 186                                         dma_params->mask->ssc_endbuf);
 187                         if (ssc_sr & ssc_substream_mask) {
 188                                 dma_params->dma_intr_handler(ssc_sr,
 189                                                 dma_params->
 190                                                 substream);
 191                         }
 192                 }
 193         }
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198
 199 /*-------------------------------------------------------------------------*\
 200  * DAI functions
 201 \*-------------------------------------------------------------------------*/
 202 /*
 203  * Startup.  Only that one substream allowed in each direction.
 204  */
 205 static int atmel_ssc_startup(struct snd_pcm_substream *substream)
 206 {
 207         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 208         struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
 209         int dir_mask;
 210
 211         pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
 212                 ssc_readl(ssc_p->ssc->regs, SR));
 213
 214         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 215                 dir_mask = SSC_DIR_MASK_PLAYBACK;
 216         else
 217                 dir_mask = SSC_DIR_MASK_CAPTURE;
 218
 219         spin_lock_irq(&ssc_p->lock);
 220         if (ssc_p->dir_mask & dir_mask) {
 221                 spin_unlock_irq(&ssc_p->lock);
 222                 return -EBUSY;
 223         }
 224         ssc_p->dir_mask |= dir_mask;
 225         spin_unlock_irq(&ssc_p->lock);
 226
 227         return 0;
 228 }
 229
 230 /*
 231  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
 232  * are no other substreams open.
 233  */
 234 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream)
 235 {
 236         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 237         struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
 238         struct atmel_pcm_dma_params *dma_params;
 239         int dir, dir_mask;
 240
 241         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 242                 dir = 0;
 243         else
 244                 dir = 1;
 245
 246         dma_params = ssc_p->dma_params[dir];
 247
 248         if (dma_params != NULL) {
 249                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 250                 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
 251                         (dir ? "receive" : "transmit"),
 252                         ssc_readl(ssc_p->ssc->regs, SR));
 253
 254                 dma_params->ssc = NULL;
 255                 dma_params->substream = NULL;
 256                 ssc_p->dma_params[dir] = NULL;
 257         }
 258
 259         dir_mask = 1 << dir;
 260
 261         spin_lock_irq(&ssc_p->lock);
 262         ssc_p->dir_mask &= ~dir_mask;
 263         if (!ssc_p->dir_mask) {
 264                 if (ssc_p->initialized) {
 265                         /* Shutdown the SSC clock. */
 266                         pr_debug("atmel_ssc_dau: Stopping clock\n");
 267                         clk_disable(ssc_p->ssc->clk);
 268
 269                         free_irq(ssc_p->ssc->irq, ssc_p);
 270                         ssc_p->initialized = 0;
 271                 }
 272
 273                 /* Reset the SSC */
 274                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 275                 /* Clear the SSC dividers */
 276                 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
 277         }
 278         spin_unlock_irq(&ssc_p->lock);
 279 }
 280
 281
 282 /*
 283  * Record the DAI format for use in hw_params().
 284  */
 285 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 286                 unsigned int fmt)
 287 {
 288         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 289
 290         ssc_p->daifmt = fmt;
 291         return 0;
 292 }
 293
 294 /*
 295  * Record SSC clock dividers for use in hw_params().
 296  */
 297 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
 298         int div_id, int div)
 299 {
 300         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 301
 302         switch (div_id) {
 303         case ATMEL_SSC_CMR_DIV:
 304                 /*
 305                  * The same master clock divider is used for both
 306                  * transmit and receive, so if a value has already
 307                  * been set, it must match this value.
 308                  */
 309                 if (ssc_p->cmr_div == 0)
 310                         ssc_p->cmr_div = div;
 311                 else
 312                         if (div != ssc_p->cmr_div)
 313                                 return -EBUSY;
 314                 break;
 315
 316         case ATMEL_SSC_TCMR_PERIOD:
 317                 ssc_p->tcmr_period = div;
 318                 break;
 319
 320         case ATMEL_SSC_RCMR_PERIOD:
 321                 ssc_p->rcmr_period = div;
 322                 break;
 323
 324         default:
 325                 return -EINVAL;
 326         }
 327
 328         return 0;
 329 }
 330
 331 /*
 332  * Configure the SSC.
 333  */
 334 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
 335         struct snd_pcm_hw_params *params)
 336 {
 337         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 338         int id = rtd->dai->cpu_dai->id;
 339         struct atmel_ssc_info *ssc_p = &ssc_info[id];
 340         struct atmel_pcm_dma_params *dma_params;
 341         int dir, channels, bits;
 342         u32 tfmr, rfmr, tcmr, rcmr;
 343         int start_event;
 344         int ret;
 345
 346         /*
 347          * Currently, there is only one set of dma params for
 348          * each direction.  If more are added, this code will
 349          * have to be changed to select the proper set.
 350          */
 351         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 352                 dir = 0;
 353         else
 354                 dir = 1;
 355
 356         dma_params = &ssc_dma_params[id][dir];
 357         dma_params->ssc = ssc_p->ssc;
 358         dma_params->substream = substream;
 359
 360         ssc_p->dma_params[dir] = dma_params;
 361
 362         /*
 363          * The cpu_dai->dma_data field is only used to communicate the
 364          * appropriate DMA parameters to the pcm driver hw_params()
 365          * function.  It should not be used for other purposes
 366          * as it is common to all substreams.
 367          */
 368         rtd->dai->cpu_dai->dma_data = dma_params;
 369
 370         channels = params_channels(params);
 371
 372         /*
 373          * Determine sample size in bits and the PDC increment.
 374          */
 375         switch (params_format(params)) {
 376         case SNDRV_PCM_FORMAT_S8:
 377                 bits = 8;
 378                 dma_params->pdc_xfer_size = 1;
 379                 break;
 380         case SNDRV_PCM_FORMAT_S16_LE:
 381                 bits = 16;
 382                 dma_params->pdc_xfer_size = 2;
 383                 break;
 384         case SNDRV_PCM_FORMAT_S24_LE:
 385                 bits = 24;
 386                 dma_params->pdc_xfer_size = 4;
 387                 break;
 388         case SNDRV_PCM_FORMAT_S32_LE:
 389                 bits = 32;
 390                 dma_params->pdc_xfer_size = 4;
 391                 break;
 392         default:
 393                 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
 394                 return -EINVAL;
 395         }
 396
 397         /*
 398          * The SSC only supports up to 16-bit samples in I2S format, due
 399          * to the size of the Frame Mode Register FSLEN field.
 400          */
 401         if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
 402                 && bits > 16) {
 403                 printk(KERN_WARNING
 404                                 "atmel_ssc_dai: sample size %d"
 405                                 "is too large for I2S\n", bits);
 406                 return -EINVAL;
 407         }
 408
 409         /*
 410          * Compute SSC register settings.
 411          */
 412         switch (ssc_p->daifmt
 413                 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
 414
 415         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
 416                 /*
 417                  * I2S format, SSC provides BCLK and LRC clocks.
 418                  *
 419                  * The SSC transmit and receive clocks are generated
 420                  * from the MCK divider, and the BCLK signal
 421                  * is output on the SSC TK line.
 422                  */
 423                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 424                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 425                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 426                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 427                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 428                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 429
 430                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 431                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
 432                         | SSC_BF(RFMR_FSLEN, (bits - 1))
 433                         | SSC_BF(RFMR_DATNB, (channels - 1))
 434                         | SSC_BIT(RFMR_MSBF)
 435                         | SSC_BF(RFMR_LOOP, 0)
 436                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 437
 438                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 439                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 440                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 441                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 442                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 443                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 444
 445                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 446                         | SSC_BF(TFMR_FSDEN, 0)
 447                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
 448                         | SSC_BF(TFMR_FSLEN, (bits - 1))
 449                         | SSC_BF(TFMR_DATNB, (channels - 1))
 450                         | SSC_BIT(TFMR_MSBF)
 451                         | SSC_BF(TFMR_DATDEF, 0)
 452                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 453                 break;
 454
 455         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
 456                 /*
 457                  * I2S format, CODEC supplies BCLK and LRC clocks.
 458                  *
 459                  * The SSC transmit clock is obtained from the BCLK signal on
 460                  * on the TK line, and the SSC receive clock is
 461                  * generated from the transmit clock.
 462                  *
 463                  *  For single channel data, one sample is transferred
 464                  * on the falling edge of the LRC clock.
 465                  * For two channel data, one sample is
 466                  * transferred on both edges of the LRC clock.
 467                  */
 468                 start_event = ((channels == 1)
 469                                 ? SSC_START_FALLING_RF
 470                                 : SSC_START_EDGE_RF);
 471
 472                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
 473                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 474                         | SSC_BF(RCMR_START, start_event)
 475                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 476                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 477                         | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
 478
 479                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 480                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 481                         | SSC_BF(RFMR_FSLEN, 0)
 482                         | SSC_BF(RFMR_DATNB, 0)
 483                         | SSC_BIT(RFMR_MSBF)
 484                         | SSC_BF(RFMR_LOOP, 0)
 485                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 486
 487                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
 488                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 489                         | SSC_BF(TCMR_START, start_event)
 490                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 491                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 492                         | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
 493
 494                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 495                         | SSC_BF(TFMR_FSDEN, 0)
 496                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 497                         | SSC_BF(TFMR_FSLEN, 0)
 498                         | SSC_BF(TFMR_DATNB, 0)
 499                         | SSC_BIT(TFMR_MSBF)
 500                         | SSC_BF(TFMR_DATDEF, 0)
 501                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 502                 break;
 503
 504         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
 505                 /*
 506                  * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
 507                  *
 508                  * The SSC transmit and receive clocks are generated from the
 509                  * MCK divider, and the BCLK signal is output
 510                  * on the SSC TK line.
 511                  */
 512                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 513                         | SSC_BF(RCMR_STTDLY, 1)
 514                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
 515                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 516                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 517                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 518
 519                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 520                         | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
 521                         | SSC_BF(RFMR_FSLEN, 0)
 522                         | SSC_BF(RFMR_DATNB, (channels - 1))
 523                         | SSC_BIT(RFMR_MSBF)
 524                         | SSC_BF(RFMR_LOOP, 0)
 525                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 526
 527                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 528                         | SSC_BF(TCMR_STTDLY, 1)
 529                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
 530                         | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
 531                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 532                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 533
 534                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 535                         | SSC_BF(TFMR_FSDEN, 0)
 536                         | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
 537                         | SSC_BF(TFMR_FSLEN, 0)
 538                         | SSC_BF(TFMR_DATNB, (channels - 1))
 539                         | SSC_BIT(TFMR_MSBF)
 540                         | SSC_BF(TFMR_DATDEF, 0)
 541                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 542                 break;
 543
 544         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
 545         default:
 546                 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
 547                         ssc_p->daifmt);
 548                 return -EINVAL;
 549                 break;
 550         }
 551         pr_debug("atmel_ssc_hw_params: "
 552                         "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
 553                         rcmr, rfmr, tcmr, tfmr);
 554
 555         if (!ssc_p->initialized) {
 556
 557                 /* Enable PMC peripheral clock for this SSC */
 558                 pr_debug("atmel_ssc_dai: Starting clock\n");
 559                 clk_enable(ssc_p->ssc->clk);
 560
 561                 /* Reset the SSC and its PDC registers */
 562                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 563
 564                 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
 565                 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
 566                 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
 567                 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
 568
 569                 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
 570                 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
 571                 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
 572                 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
 573
 574                 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
 575                                 ssc_p->name, ssc_p);
 576                 if (ret < 0) {
 577                         printk(KERN_WARNING
 578                                         "atmel_ssc_dai: request_irq failure\n");
 579                         pr_debug("Atmel_ssc_dai: Stoping clock\n");
 580                         clk_disable(ssc_p->ssc->clk);
 581                         return ret;
 582                 }
 583
 584                 ssc_p->initialized = 1;
 585         }
 586
 587         /* set SSC clock mode register */
 588         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
 589
 590         /* set receive clock mode and format */
 591         ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
 592         ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
 593
 594         /* set transmit clock mode and format */
 595         ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
 596         ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
 597
 598         pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
 599         return 0;
 600 }
 601
 602
 603 static int atmel_ssc_prepare(struct snd_pcm_substream *substream)
 604 {
 605         struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
 606         struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
 607         struct atmel_pcm_dma_params *dma_params;
 608         int dir;
 609
 610         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 611                 dir = 0;
 612         else
 613                 dir = 1;
 614
 615         dma_params = ssc_p->dma_params[dir];
 616
 617         ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
 618
 619         pr_debug("%s enabled SSC_SR=0x%08x\n",
 620                         dir ? "receive" : "transmit",
 621                         ssc_readl(ssc_p->ssc->regs, SR));
 622         return 0;
 623 }
 624
 625
 626 #ifdef CONFIG_PM
 627 static int atmel_ssc_suspend(struct platform_device *pdev,
 628                             struct snd_soc_dai *cpu_dai)
 629 {
 630         struct atmel_ssc_info *ssc_p;
 631
 632         if (!cpu_dai->active)
 633                 return 0;
 634
 635         ssc_p = &ssc_info[cpu_dai->id];
 636
 637         /* Save the status register before disabling transmit and receive */
 638         ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
 639         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
 640
 641         /* Save the current interrupt mask, then disable unmasked interrupts */
 642         ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
 643         ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
 644
 645         ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
 646         ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
 647         ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
 648         ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
 649         ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
 650
 651         return 0;
 652 }
 653
 654
 655
 656 static int atmel_ssc_resume(struct platform_device *pdev,
 657                            struct snd_soc_dai *cpu_dai)
 658 {
 659         struct atmel_ssc_info *ssc_p;
 660         u32 cr;
 661
 662         if (!cpu_dai->active)
 663                 return 0;
 664
 665         ssc_p = &ssc_info[cpu_dai->id];
 666
 667         /* restore SSC register settings */
 668         ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
 669         ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
 670         ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
 671         ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
 672         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
 673
 674         /* re-enable interrupts */
 675         ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
 676
 677         /* Re-enable recieve and transmit as appropriate */
 678         cr = 0;
 679         cr |=
 680             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
 681         cr |=
 682             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
 683         ssc_writel(ssc_p->ssc->regs, CR, cr);
 684
 685         return 0;
 686 }
 687 #else /* CONFIG_PM */
 688 #  define atmel_ssc_suspend     NULL
 689 #  define atmel_ssc_resume      NULL
 690 #endif /* CONFIG_PM */
 691
 692
 693 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
 694
 695 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
 696                           SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 697
 698 struct snd_soc_dai atmel_ssc_dai[NUM_SSC_DEVICES] = {
 699         {       .name = "atmel-ssc0",
 700                 .id = 0,
 701                 .type = SND_SOC_DAI_PCM,
 702                 .suspend = atmel_ssc_suspend,
 703                 .resume = atmel_ssc_resume,
 704                 .playback = {
 705                         .channels_min = 1,
 706                         .channels_max = 2,
 707                         .rates = ATMEL_SSC_RATES,
 708                         .formats = ATMEL_SSC_FORMATS,},
 709                 .capture = {
 710                         .channels_min = 1,
 711                         .channels_max = 2,
 712                         .rates = ATMEL_SSC_RATES,
 713                         .formats = ATMEL_SSC_FORMATS,},
 714                 .ops = {
 715                         .startup = atmel_ssc_startup,
 716                         .shutdown = atmel_ssc_shutdown,
 717                         .prepare = atmel_ssc_prepare,
 718                         .hw_params = atmel_ssc_hw_params,},
 719                 .dai_ops = {
 720                         .set_fmt = atmel_ssc_set_dai_fmt,
 721                         .set_clkdiv = atmel_ssc_set_dai_clkdiv,},
 722                 .private_data = &ssc_info[0],
 723         },
 724 #if NUM_SSC_DEVICES == 3
 725         {       .name = "atmel-ssc1",
 726                 .id = 1,
 727                 .type = SND_SOC_DAI_PCM,
 728                 .suspend = atmel_ssc_suspend,
 729                 .resume = atmel_ssc_resume,
 730                 .playback = {
 731                         .channels_min = 1,
 732                         .channels_max = 2,
 733                         .rates = ATMEL_SSC_RATES,
 734                         .formats = ATMEL_SSC_FORMATS,},
 735                 .capture = {
 736                         .channels_min = 1,
 737                         .channels_max = 2,
 738                         .rates = ATMEL_SSC_RATES,
 739                         .formats = ATMEL_SSC_FORMATS,},
 740                 .ops = {
 741                         .startup = atmel_ssc_startup,
 742                         .shutdown = atmel_ssc_shutdown,
 743                         .prepare = atmel_ssc_prepare,
 744                         .hw_params = atmel_ssc_hw_params,},
 745                 .dai_ops = {
 746                         .set_fmt = atmel_ssc_set_dai_fmt,
 747                         .set_clkdiv = atmel_ssc_set_dai_clkdiv,},
 748                 .private_data = &ssc_info[1],
 749         },
 750         {       .name = "atmel-ssc2",
 751                 .id = 2,
 752                 .type = SND_SOC_DAI_PCM,
 753                 .suspend = atmel_ssc_suspend,
 754                 .resume = atmel_ssc_resume,
 755                 .playback = {
 756                         .channels_min = 1,
 757                         .channels_max = 2,
 758                         .rates = ATMEL_SSC_RATES,
 759                         .formats = ATMEL_SSC_FORMATS,},
 760                 .capture = {
 761                         .channels_min = 1,
 762                         .channels_max = 2,
 763                         .rates = ATMEL_SSC_RATES,
 764                         .formats = ATMEL_SSC_FORMATS,},
 765                 .ops = {
 766                         .startup = atmel_ssc_startup,
 767                         .shutdown = atmel_ssc_shutdown,
 768                         .prepare = atmel_ssc_prepare,
 769                         .hw_params = atmel_ssc_hw_params,},
 770                 .dai_ops = {
 771                         .set_fmt = atmel_ssc_set_dai_fmt,
 772                         .set_clkdiv = atmel_ssc_set_dai_clkdiv,},
 773                 .private_data = &ssc_info[2],
 774         },
 775 #endif
 776 };
 777 EXPORT_SYMBOL_GPL(atmel_ssc_dai);
 778
 779 /* Module information */
 780 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
 781 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
 782 MODULE_LICENSE("GPL");