sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <sound/driver.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/firmware.h>
  31 #include <linux/moduleparam.h>
  32
  33 #include <sound/core.h>
  34 #include <sound/control.h>
  35 #include <sound/pcm.h>
  36 #include <sound/info.h>
  37 #include <sound/asoundef.h>
  38 #include <sound/rawmidi.h>
  39 #include <sound/hwdep.h>
  40 #include <sound/initval.h>
  41 #include <sound/hdsp.h>
  42
  43 #include <asm/byteorder.h>
  44 #include <asm/current.h>
  45 #include <asm/io.h>
  46
  47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  50
  51 module_param_array(index, int, NULL, 0444);
  52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  53 module_param_array(id, charp, NULL, 0444);
  54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  55 module_param_array(enable, bool, NULL, 0444);
  56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  58 MODULE_DESCRIPTION("RME Hammerfall DSP");
  59 MODULE_LICENSE("GPL");
  60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  61                 "{RME HDSP-9652},"
  62                 "{RME HDSP-9632}}");
  63
  64 #define HDSP_MAX_CHANNELS        26
  65 #define HDSP_MAX_DS_CHANNELS     14
  66 #define HDSP_MAX_QS_CHANNELS     8
  67 #define DIGIFACE_SS_CHANNELS     26
  68 #define DIGIFACE_DS_CHANNELS     14
  69 #define MULTIFACE_SS_CHANNELS    18
  70 #define MULTIFACE_DS_CHANNELS    14
  71 #define H9652_SS_CHANNELS        26
  72 #define H9652_DS_CHANNELS        14
  73 /* This does not include possible Analog Extension Boards
  74    AEBs are detected at card initialization
  75 */
  76 #define H9632_SS_CHANNELS        12
  77 #define H9632_DS_CHANNELS        8
  78 #define H9632_QS_CHANNELS        4
  79
  80 /* Write registers. These are defined as byte-offsets from the iobase value.
  81  */
  82 #define HDSP_resetPointer               0
  83 #define HDSP_outputBufferAddress        32
  84 #define HDSP_inputBufferAddress         36
  85 #define HDSP_controlRegister            64
  86 #define HDSP_interruptConfirmation      96
  87 #define HDSP_outputEnable               128
  88 #define HDSP_control2Reg                256
  89 #define HDSP_midiDataOut0               352
  90 #define HDSP_midiDataOut1               356
  91 #define HDSP_fifoData                   368
  92 #define HDSP_inputEnable                384
  93
  94 /* Read registers. These are defined as byte-offsets from the iobase value
  95  */
  96
  97 #define HDSP_statusRegister    0
  98 #define HDSP_timecode        128
  99 #define HDSP_status2Register 192
 100 #define HDSP_midiDataOut0    352
 101 #define HDSP_midiDataOut1    356
 102 #define HDSP_midiDataIn0     360
 103 #define HDSP_midiDataIn1     364
 104 #define HDSP_midiStatusOut0  384
 105 #define HDSP_midiStatusOut1  388
 106 #define HDSP_midiStatusIn0   392
 107 #define HDSP_midiStatusIn1   396
 108 #define HDSP_fifoStatus      400
 109
 110 /* the meters are regular i/o-mapped registers, but offset
 111    considerably from the rest. the peak registers are reset
 112    when read; the least-significant 4 bits are full-scale counters;
 113    the actual peak value is in the most-significant 24 bits.
 114 */
 115
 116 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 117 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 118 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 119 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 120 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 121
 122
 123 /* This is for H9652 cards
 124    Peak values are read downward from the base
 125    Rms values are read upward
 126    There are rms values for the outputs too
 127    26*3 values are read in ss mode
 128    14*3 in ds mode, with no gap between values
 129 */
 130 #define HDSP_9652_peakBase      7164
 131 #define HDSP_9652_rmsBase       4096
 132
 133 /* c.f. the hdsp_9632_meters_t struct */
 134 #define HDSP_9632_metersBase    4096
 135
 136 #define HDSP_IO_EXTENT     7168
 137
 138 /* control2 register bits */
 139
 140 #define HDSP_TMS                0x01
 141 #define HDSP_TCK                0x02
 142 #define HDSP_TDI                0x04
 143 #define HDSP_JTAG               0x08
 144 #define HDSP_PWDN               0x10
 145 #define HDSP_PROGRAM            0x020
 146 #define HDSP_CONFIG_MODE_0      0x040
 147 #define HDSP_CONFIG_MODE_1      0x080
 148 #define HDSP_VERSION_BIT        0x100
 149 #define HDSP_BIGENDIAN_MODE     0x200
 150 #define HDSP_RD_MULTIPLE        0x400
 151 #define HDSP_9652_ENABLE_MIXER  0x800
 152 #define HDSP_TDO                0x10000000
 153
 154 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 155 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 156
 157 /* Control Register bits */
 158
 159 #define HDSP_Start                (1<<0)  /* start engine */
 160 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 161 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 162 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 163 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 164 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 165 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 166 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 167 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 168 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 169 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 170 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 171 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 172 #define HDSP_SyncRef2             (1<<13)
 173 #define HDSP_SPDIFInputSelect0    (1<<14)
 174 #define HDSP_SPDIFInputSelect1    (1<<15)
 175 #define HDSP_SyncRef0             (1<<16)
 176 #define HDSP_SyncRef1             (1<<17)
 177 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 178 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 179 #define HDSP_Midi0InterruptEnable (1<<22)
 180 #define HDSP_Midi1InterruptEnable (1<<23)
 181 #define HDSP_LineOut              (1<<24)
 182 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 183 #define HDSP_ADGain1              (1<<26)
 184 #define HDSP_DAGain0              (1<<27)
 185 #define HDSP_DAGain1              (1<<28)
 186 #define HDSP_PhoneGain0           (1<<29)
 187 #define HDSP_PhoneGain1           (1<<30)
 188 #define HDSP_QuadSpeed            (1<<31)
 189
 190 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 191 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 192 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 193 #define HDSP_ADGainLowGain     0
 194
 195 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 196 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 197 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 198 #define HDSP_DAGainMinus10dBV    0
 199
 200 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 201 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 202 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 203 #define HDSP_PhoneGainMinus12dB  0
 204
 205 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 206 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 207
 208 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 209 #define HDSP_SPDIFInputADAT1    0
 210 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 211 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 212 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 213
 214 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 215 #define HDSP_SyncRef_ADAT1       0
 216 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 217 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 218 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 219 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 220 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 221
 222 /* Sample Clock Sources */
 223
 224 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 225 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 226 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 227 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 228 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 229 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 230 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 231 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 232 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 233 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 234
 235 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 236
 237 #define HDSP_SYNC_FROM_WORD      0
 238 #define HDSP_SYNC_FROM_SPDIF     1
 239 #define HDSP_SYNC_FROM_ADAT1     2
 240 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 241 #define HDSP_SYNC_FROM_ADAT2     4
 242 #define HDSP_SYNC_FROM_ADAT3     5
 243
 244 /* SyncCheck status */
 245
 246 #define HDSP_SYNC_CHECK_NO_LOCK 0
 247 #define HDSP_SYNC_CHECK_LOCK    1
 248 #define HDSP_SYNC_CHECK_SYNC    2
 249
 250 /* AutoSync references - used by "autosync_ref" control switch */
 251
 252 #define HDSP_AUTOSYNC_FROM_WORD      0
 253 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 254 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 255 #define HDSP_AUTOSYNC_FROM_NONE      3
 256 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 257 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 258 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 259
 260 /* Possible sources of S/PDIF input */
 261
 262 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 263 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 264 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 265 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 266
 267 #define HDSP_Frequency32KHz    HDSP_Frequency0
 268 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 269 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 270 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 271 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 272 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 273 /* For H9632 cards */
 274 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 275 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 276 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 277
 278 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 279 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 280
 281 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 282 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 283
 284 /* Status Register bits */
 285
 286 #define HDSP_audioIRQPending    (1<<0)
 287 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 288 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 289 #define HDSP_Lock1              (1<<2)
 290 #define HDSP_Lock0              (1<<3)
 291 #define HDSP_SPDIFSync          (1<<4)
 292 #define HDSP_TimecodeLock       (1<<5)
 293 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 294 #define HDSP_Sync2              (1<<16)
 295 #define HDSP_Sync1              (1<<17)
 296 #define HDSP_Sync0              (1<<18)
 297 #define HDSP_DoubleSpeedStatus  (1<<19)
 298 #define HDSP_ConfigError        (1<<20)
 299 #define HDSP_DllError           (1<<21)
 300 #define HDSP_spdifFrequency0    (1<<22)
 301 #define HDSP_spdifFrequency1    (1<<23)
 302 #define HDSP_spdifFrequency2    (1<<24)
 303 #define HDSP_SPDIFErrorFlag     (1<<25)
 304 #define HDSP_BufferID           (1<<26)
 305 #define HDSP_TimecodeSync       (1<<27)
 306 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 307 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 308 #define HDSP_midi0IRQPending    (1<<30)
 309 #define HDSP_midi1IRQPending    (1<<31)
 310
 311 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 312
 313 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 314 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 315 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 316
 317 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 318 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 319 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 320
 321 /* This is for H9632 cards */
 322 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
 323 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 324 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 325
 326 /* Status2 Register bits */
 327
 328 #define HDSP_version0     (1<<0)
 329 #define HDSP_version1     (1<<1)
 330 #define HDSP_version2     (1<<2)
 331 #define HDSP_wc_lock      (1<<3)
 332 #define HDSP_wc_sync      (1<<4)
 333 #define HDSP_inp_freq0    (1<<5)
 334 #define HDSP_inp_freq1    (1<<6)
 335 #define HDSP_inp_freq2    (1<<7)
 336 #define HDSP_SelSyncRef0  (1<<8)
 337 #define HDSP_SelSyncRef1  (1<<9)
 338 #define HDSP_SelSyncRef2  (1<<10)
 339
 340 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 341
 342 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 343 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 344 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 345 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 346 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 347 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 348 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 349 /* FIXME : more values for 9632 cards ? */
 350
 351 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 352 #define HDSP_SelSyncRef_ADAT1      0
 353 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 354 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 355 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 356 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 357 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 358
 359 /* Card state flags */
 360
 361 #define HDSP_InitializationComplete  (1<<0)
 362 #define HDSP_FirmwareLoaded          (1<<1)
 363 #define HDSP_FirmwareCached          (1<<2)
 364
 365 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 366
 367 #define HDSP_LONG_WAIT   5000
 368 #define HDSP_SHORT_WAIT  30
 369
 370 #define UNITY_GAIN                       32768
 371 #define MINUS_INFINITY_GAIN              0
 372
 373 /* the size of a substream (1 mono data stream) */
 374
 375 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 376 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 377
 378 /* the size of the area we need to allocate for DMA transfers. the
 379    size is the same regardless of the number of channels - the
 380    Multiface still uses the same memory area.
 381
 382    Note that we allocate 1 more channel than is apparently needed
 383    because the h/w seems to write 1 byte beyond the end of the last
 384    page. Sigh.
 385 */
 386
 387 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 388 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 389
 390 /* use hotplug firmeare loader? */
 391 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
 392 #ifndef HDSP_USE_HWDEP_LOADER
 393 #define HDSP_FW_LOADER
 394 #endif
 395 #endif
 396
 397 typedef struct _hdsp             hdsp_t;
 398 typedef struct _hdsp_midi        hdsp_midi_t;
 399 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
 400
 401 struct _hdsp_9632_meters {
 402     u32 input_peak[16];
 403     u32 playback_peak[16];
 404     u32 output_peak[16];
 405     u32 xxx_peak[16];
 406     u32 padding[64];
 407     u32 input_rms_low[16];
 408     u32 playback_rms_low[16];
 409     u32 output_rms_low[16];
 410     u32 xxx_rms_low[16];
 411     u32 input_rms_high[16];
 412     u32 playback_rms_high[16];
 413     u32 output_rms_high[16];
 414     u32 xxx_rms_high[16];
 415 };
 416
 417 struct _hdsp_midi {
 418     hdsp_t                  *hdsp;
 419     int                      id;
 420     snd_rawmidi_t           *rmidi;
 421     snd_rawmidi_substream_t *input;
 422     snd_rawmidi_substream_t *output;
 423     char                     istimer; /* timer in use */
 424     struct timer_list        timer;
 425     spinlock_t               lock;
 426     int                      pending;
 427 };
 428
 429 struct _hdsp {
 430         spinlock_t            lock;
 431         snd_pcm_substream_t  *capture_substream;
 432         snd_pcm_substream_t  *playback_substream;
 433         hdsp_midi_t           midi[2];
 434         struct tasklet_struct midi_tasklet;
 435         int                   use_midi_tasklet;
 436         int                   precise_ptr;
 437         u32                   control_register;      /* cached value */
 438         u32                   control2_register;     /* cached value */
 439         u32                   creg_spdif;
 440         u32                   creg_spdif_stream;
 441         int                   clock_source_locked;
 442         char                 *card_name;             /* digiface/multiface */
 443         HDSP_IO_Type          io_type;               /* ditto, but for code use */
 444         unsigned short        firmware_rev;
 445         unsigned short        state;                 /* stores state bits */
 446         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
 447         size_t                period_bytes;          /* guess what this is */
 448         unsigned char         max_channels;
 449         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 450         unsigned char         ds_in_channels;
 451         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 452         unsigned char         qs_out_channels;
 453         unsigned char         ds_out_channels;
 454         unsigned char         ss_out_channels;
 455
 456         struct snd_dma_buffer capture_dma_buf;
 457         struct snd_dma_buffer playback_dma_buf;
 458         unsigned char        *capture_buffer;       /* suitably aligned address */
 459         unsigned char        *playback_buffer;      /* suitably aligned address */
 460
 461         pid_t                 capture_pid;
 462         pid_t                 playback_pid;
 463         int                   running;
 464         int                   system_sample_rate;
 465         char                 *channel_map;
 466         int                   dev;
 467         int                   irq;
 468         unsigned long         port;
 469         void __iomem         *iobase;
 470         snd_card_t           *card;
 471         snd_pcm_t            *pcm;
 472         snd_hwdep_t          *hwdep;
 473         struct pci_dev       *pci;
 474         snd_kcontrol_t       *spdif_ctl;
 475         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 476 };
 477
 478 /* These tables map the ALSA channels 1..N to the channels that we
 479    need to use in order to find the relevant channel buffer. RME
 480    refer to this kind of mapping as between "the ADAT channel and
 481    the DMA channel." We index it using the logical audio channel,
 482    and the value is the DMA channel (i.e. channel buffer number)
 483    where the data for that channel can be read/written from/to.
 484 */
 485
 486 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 487         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 488         18, 19, 20, 21, 22, 23, 24, 25
 489 };
 490
 491 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 492         /* Analog */
 493         0, 1, 2, 3, 4, 5, 6, 7,
 494         /* ADAT 2 */
 495         16, 17, 18, 19, 20, 21, 22, 23,
 496         /* SPDIF */
 497         24, 25,
 498         -1, -1, -1, -1, -1, -1, -1, -1
 499 };
 500
 501 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 502         /* ADAT channels are remapped */
 503         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 504         /* channels 12 and 13 are S/PDIF */
 505         24, 25,
 506         /* others don't exist */
 507         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 508 };
 509
 510 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 511         /* ADAT channels */
 512         0, 1, 2, 3, 4, 5, 6, 7,
 513         /* SPDIF */
 514         8, 9,
 515         /* Analog */
 516         10, 11,
 517         /* AO4S-192 and AI4S-192 extension boards */
 518         12, 13, 14, 15,
 519         /* others don't exist */
 520         -1, -1, -1, -1, -1, -1, -1, -1,
 521         -1, -1
 522 };
 523
 524 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 525         /* ADAT */
 526         1, 3, 5, 7,
 527         /* SPDIF */
 528         8, 9,
 529         /* Analog */
 530         10, 11,
 531         /* AO4S-192 and AI4S-192 extension boards */
 532         12, 13, 14, 15,
 533         /* others don't exist */
 534         -1, -1, -1, -1, -1, -1, -1, -1,
 535         -1, -1, -1, -1, -1, -1
 536 };
 537
 538 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 539         /* ADAT is disabled in this mode */
 540         /* SPDIF */
 541         8, 9,
 542         /* Analog */
 543         10, 11,
 544         /* AO4S-192 and AI4S-192 extension boards */
 545         12, 13, 14, 15,
 546         /* others don't exist */
 547         -1, -1, -1, -1, -1, -1, -1, -1,
 548         -1, -1, -1, -1, -1, -1, -1, -1,
 549         -1, -1
 550 };
 551
 552 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 553 {
 554         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 555         dmab->dev.dev = snd_dma_pci_data(pci);
 556         if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
 557                 if (dmab->bytes >= size)
 558                         return 0;
 559         }
 560         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 561                                 size, dmab) < 0)
 562                 return -ENOMEM;
 563         return 0;
 564 }
 565
 566 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 567 {
 568         if (dmab->area) {
 569                 dmab->dev.dev = NULL; /* make it anonymous */
 570                 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
 571         }
 572 }
 573
 574
 575 static struct pci_device_id snd_hdsp_ids[] = {
 576         {
 577                 .vendor = PCI_VENDOR_ID_XILINX,
 578                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 579                 .subvendor = PCI_ANY_ID,
 580                 .subdevice = PCI_ANY_ID,
 581         }, /* RME Hammerfall-DSP */
 582         { 0, },
 583 };
 584
 585 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 586
 587 /* prototypes */
 588 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
 589 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
 590 static int snd_hdsp_enable_io (hdsp_t *hdsp);
 591 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
 592 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
 593 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
 594 static int hdsp_autosync_ref(hdsp_t *hdsp);
 595 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
 596 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
 597
 598 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
 599 {
 600         switch (hdsp->firmware_rev) {
 601         case 0xa:
 602                 return (64 * out) + (32 + (in));
 603         case 0x96:
 604         case 0x97:
 605                 return (32 * out) + (16 + (in));
 606         default:
 607                 return (52 * out) + (26 + (in));
 608         }
 609 }
 610
 611 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
 612 {
 613         switch (hdsp->firmware_rev) {
 614         case 0xa:
 615                 return (64 * out) + in;
 616         case 0x96:
 617         case 0x97:
 618                 return (32 * out) + in;
 619         default:
 620                 return (52 * out) + in;
 621         }
 622 }
 623
 624 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
 625 {
 626         writel(val, hdsp->iobase + reg);
 627 }
 628
 629 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
 630 {
 631         return readl (hdsp->iobase + reg);
 632 }
 633
 634 static int hdsp_check_for_iobox (hdsp_t *hdsp)
 635 {
 636
 637         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 638         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
 639                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
 640                 hdsp->state &= ~HDSP_FirmwareLoaded;
 641                 return -EIO;
 642         }
 643         return 0;
 644
 645 }
 646
 647 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 648
 649         int i;
 650         unsigned long flags;
 651
 652         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 653
 654                 snd_printk ("Hammerfall-DSP: loading firmware\n");
 655
 656                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 657                 hdsp_write (hdsp, HDSP_fifoData, 0);
 658
 659                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 660                         snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
 661                         return -EIO;
 662                 }
 663
 664                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 665
 666                 for (i = 0; i < 24413; ++i) {
 667                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
 668                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 669                                 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
 670                                 return -EIO;
 671                         }
 672                 }
 673
 674                 if ((1000 / HZ) < 3000) {
 675                         ssleep(3);
 676                 } else {
 677                         mdelay(3000);
 678                 }
 679
 680                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 681                         snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
 682                         return -EIO;
 683                 }
 684
 685 #ifdef SNDRV_BIG_ENDIAN
 686                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 687 #else
 688                 hdsp->control2_register = 0;
 689 #endif
 690                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 691                 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
 692
 693         }
 694         if (hdsp->state & HDSP_InitializationComplete) {
 695                 snd_printk("Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
 696                 spin_lock_irqsave(&hdsp->lock, flags);
 697                 snd_hdsp_set_defaults(hdsp);
 698                 spin_unlock_irqrestore(&hdsp->lock, flags);
 699         }
 700
 701         hdsp->state |= HDSP_FirmwareLoaded;
 702
 703         return 0;
 704 }
 705
 706 static int hdsp_get_iobox_version (hdsp_t *hdsp)
 707 {
 708         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 709
 710                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
 711                 hdsp_write (hdsp, HDSP_fifoData, 0);
 712                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 713                         return -EIO;
 714                 }
 715
 716                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 717                 hdsp_write (hdsp, HDSP_fifoData, 0);
 718
 719                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
 720                         hdsp->io_type = Multiface;
 721                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
 722                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 723                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
 724                 } else {
 725                         hdsp->io_type = Digiface;
 726                 }
 727         } else {
 728                 /* firmware was already loaded, get iobox type */
 729                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
 730                         hdsp->io_type = Multiface;
 731                 } else {
 732                         hdsp->io_type = Digiface;
 733                 }
 734         }
 735         return 0;
 736 }
 737
 738
 739 static int hdsp_check_for_firmware (hdsp_t *hdsp)
 740 {
 741         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 742         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 743                 snd_printk("Hammerfall-DSP: firmware not present.\n");
 744                 hdsp->state &= ~HDSP_FirmwareLoaded;
 745                 return -EIO;
 746         }
 747         return 0;
 748 }
 749
 750
 751 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
 752 {
 753         int i;
 754
 755         /* the fifoStatus registers reports on how many words
 756            are available in the command FIFO.
 757         */
 758
 759         for (i = 0; i < timeout; i++) {
 760
 761                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 762                         return 0;
 763
 764                 /* not very friendly, but we only do this during a firmware
 765                    load and changing the mixer, so we just put up with it.
 766                 */
 767
 768                 udelay (100);
 769         }
 770
 771         snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
 772                     count, timeout);
 773         return -1;
 774 }
 775
 776 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
 777 {
 778         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
 779                 return 0;
 780         }
 781         return hdsp->mixer_matrix[addr];
 782 }
 783
 784 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
 785 {
 786         unsigned int ad;
 787
 788         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 789                 return -1;
 790
 791         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 792
 793                 /* from martin bjornsen:
 794
 795                    "You can only write dwords to the
 796                    mixer memory which contain two
 797                    mixer values in the low and high
 798                    word. So if you want to change
 799                    value 0 you have to read value 1
 800                    from the cache and write both to
 801                    the first dword in the mixer
 802                    memory."
 803                 */
 804
 805                 if (hdsp->io_type == H9632 && addr >= 512) {
 806                         return 0;
 807                 }
 808
 809                 if (hdsp->io_type == H9652 && addr >= 1352) {
 810                         return 0;
 811                 }
 812
 813                 hdsp->mixer_matrix[addr] = data;
 814
 815
 816                 /* `addr' addresses a 16-bit wide address, but
 817                    the address space accessed via hdsp_write
 818                    uses byte offsets. put another way, addr
 819                    varies from 0 to 1351, but to access the
 820                    corresponding memory location, we need
 821                    to access 0 to 2703 ...
 822                 */
 823                 ad = addr/2;
 824
 825                 hdsp_write (hdsp, 4096 + (ad*4),
 826                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 827                             hdsp->mixer_matrix[addr&0x7fe]);
 828
 829                 return 0;
 830
 831         } else {
 832
 833                 ad = (addr << 16) + data;
 834
 835                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
 836                         return -1;
 837                 }
 838
 839                 hdsp_write (hdsp, HDSP_fifoData, ad);
 840                 hdsp->mixer_matrix[addr] = data;
 841
 842         }
 843
 844         return 0;
 845 }
 846
 847 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
 848 {
 849         unsigned long flags;
 850         int ret = 1;
 851
 852         spin_lock_irqsave(&hdsp->lock, flags);
 853         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 854             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
 855                 ret = 0;
 856         }
 857         spin_unlock_irqrestore(&hdsp->lock, flags);
 858         return ret;
 859 }
 860
 861 static int hdsp_external_sample_rate (hdsp_t *hdsp)
 862 {
 863         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 864         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
 865
 866         switch (rate_bits) {
 867         case HDSP_systemFrequency32:   return 32000;
 868         case HDSP_systemFrequency44_1: return 44100;
 869         case HDSP_systemFrequency48:   return 48000;
 870         case HDSP_systemFrequency64:   return 64000;
 871         case HDSP_systemFrequency88_2: return 88200;
 872         case HDSP_systemFrequency96:   return 96000;
 873         default:
 874                 return 0;
 875         }
 876 }
 877
 878 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
 879 {
 880         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 881         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 882
 883         if (status & HDSP_SPDIFErrorFlag) {
 884                 return 0;
 885         }
 886
 887         switch (rate_bits) {
 888         case HDSP_spdifFrequency32KHz: return 32000;
 889         case HDSP_spdifFrequency44_1KHz: return 44100;
 890         case HDSP_spdifFrequency48KHz: return 48000;
 891         case HDSP_spdifFrequency64KHz: return 64000;
 892         case HDSP_spdifFrequency88_2KHz: return 88200;
 893         case HDSP_spdifFrequency96KHz: return 96000;
 894         case HDSP_spdifFrequency128KHz:
 895                 if (hdsp->io_type == H9632) return 128000;
 896                 break;
 897         case HDSP_spdifFrequency176_4KHz:
 898                 if (hdsp->io_type == H9632) return 176400;
 899                 break;
 900         case HDSP_spdifFrequency192KHz:
 901                 if (hdsp->io_type == H9632) return 192000;
 902                 break;
 903         default:
 904                 break;
 905         }
 906         snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
 907         return 0;
 908 }
 909
 910 static void hdsp_compute_period_size(hdsp_t *hdsp)
 911 {
 912         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
 913 }
 914
 915 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
 916 {
 917         int position;
 918
 919         position = hdsp_read(hdsp, HDSP_statusRegister);
 920
 921         if (!hdsp->precise_ptr) {
 922                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
 923         }
 924
 925         position &= HDSP_BufferPositionMask;
 926         position /= 4;
 927         position &= (hdsp->period_bytes/2) - 1;
 928         return position;
 929 }
 930
 931 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
 932 {
 933         hdsp_write (hdsp, HDSP_resetPointer, 0);
 934 }
 935
 936 static void hdsp_start_audio(hdsp_t *s)
 937 {
 938         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
 939         hdsp_write(s, HDSP_controlRegister, s->control_register);
 940 }
 941
 942 static void hdsp_stop_audio(hdsp_t *s)
 943 {
 944         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
 945         hdsp_write(s, HDSP_controlRegister, s->control_register);
 946 }
 947
 948 static void hdsp_silence_playback(hdsp_t *hdsp)
 949 {
 950         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
 951 }
 952
 953 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
 954 {
 955         int n;
 956
 957         spin_lock_irq(&s->lock);
 958
 959         frames >>= 7;
 960         n = 0;
 961         while (frames) {
 962                 n++;
 963                 frames >>= 1;
 964         }
 965
 966         s->control_register &= ~HDSP_LatencyMask;
 967         s->control_register |= hdsp_encode_latency(n);
 968
 969         hdsp_write(s, HDSP_controlRegister, s->control_register);
 970
 971         hdsp_compute_period_size(s);
 972
 973         spin_unlock_irq(&s->lock);
 974
 975         return 0;
 976 }
 977
 978 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
 979 {
 980         int reject_if_open = 0;
 981         int current_rate;
 982         int rate_bits;
 983
 984         /* ASSUMPTION: hdsp->lock is either held, or
 985            there is no need for it (e.g. during module
 986            initialization).
 987         */
 988
 989         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
 990                 if (called_internally) {
 991                         /* request from ctl or card initialization */
 992                         snd_printk("Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
 993                         return -1;
 994                 } else {
 995                         /* hw_param request while in AutoSync mode */
 996                         int external_freq = hdsp_external_sample_rate(hdsp);
 997                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
 998
 999                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1000                                 snd_printk("Hammerfall-DSP: Detected ADAT in double speed mode\n");
1001                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1002                                 snd_printk("Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1003                         } else if (rate != external_freq) {
1004                                 snd_printk("Hammerfall-DSP: No AutoSync source for requested rate\n");
1005                                 return -1;
1006                         }
1007                 }
1008         }
1009
1010         current_rate = hdsp->system_sample_rate;
1011
1012         /* Changing from a "single speed" to a "double speed" rate is
1013            not allowed if any substreams are open. This is because
1014            such a change causes a shift in the location of
1015            the DMA buffers and a reduction in the number of available
1016            buffers.
1017
1018            Note that a similar but essentially insoluble problem
1019            exists for externally-driven rate changes. All we can do
1020            is to flag rate changes in the read/write routines.  */
1021
1022         if (rate > 96000 && hdsp->io_type != H9632) {
1023                 return -EINVAL;
1024         }
1025
1026         switch (rate) {
1027         case 32000:
1028                 if (current_rate > 48000) {
1029                         reject_if_open = 1;
1030                 }
1031                 rate_bits = HDSP_Frequency32KHz;
1032                 break;
1033         case 44100:
1034                 if (current_rate > 48000) {
1035                         reject_if_open = 1;
1036                 }
1037                 rate_bits = HDSP_Frequency44_1KHz;
1038                 break;
1039         case 48000:
1040                 if (current_rate > 48000) {
1041                         reject_if_open = 1;
1042                 }
1043                 rate_bits = HDSP_Frequency48KHz;
1044                 break;
1045         case 64000:
1046                 if (current_rate <= 48000 || current_rate > 96000) {
1047                         reject_if_open = 1;
1048                 }
1049                 rate_bits = HDSP_Frequency64KHz;
1050                 break;
1051         case 88200:
1052                 if (current_rate <= 48000 || current_rate > 96000) {
1053                         reject_if_open = 1;
1054                 }
1055                 rate_bits = HDSP_Frequency88_2KHz;
1056                 break;
1057         case 96000:
1058                 if (current_rate <= 48000 || current_rate > 96000) {
1059                         reject_if_open = 1;
1060                 }
1061                 rate_bits = HDSP_Frequency96KHz;
1062                 break;
1063         case 128000:
1064                 if (current_rate < 128000) {
1065                         reject_if_open = 1;
1066                 }
1067                 rate_bits = HDSP_Frequency128KHz;
1068                 break;
1069         case 176400:
1070                 if (current_rate < 128000) {
1071                         reject_if_open = 1;
1072                 }
1073                 rate_bits = HDSP_Frequency176_4KHz;
1074                 break;
1075         case 192000:
1076                 if (current_rate < 128000) {
1077                         reject_if_open = 1;
1078                 }
1079                 rate_bits = HDSP_Frequency192KHz;
1080                 break;
1081         default:
1082                 return -EINVAL;
1083         }
1084
1085         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1086                 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1087                             hdsp->capture_pid,
1088                             hdsp->playback_pid);
1089                 return -EBUSY;
1090         }
1091
1092         hdsp->control_register &= ~HDSP_FrequencyMask;
1093         hdsp->control_register |= rate_bits;
1094         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1095
1096         if (rate >= 128000) {
1097                 hdsp->channel_map = channel_map_H9632_qs;
1098         } else if (rate > 48000) {
1099                 if (hdsp->io_type == H9632) {
1100                         hdsp->channel_map = channel_map_H9632_ds;
1101                 } else {
1102                         hdsp->channel_map = channel_map_ds;
1103                 }
1104         } else {
1105                 switch (hdsp->io_type) {
1106                 case Multiface:
1107                         hdsp->channel_map = channel_map_mf_ss;
1108                         break;
1109                 case Digiface:
1110                 case H9652:
1111                         hdsp->channel_map = channel_map_df_ss;
1112                         break;
1113                 case H9632:
1114                         hdsp->channel_map = channel_map_H9632_ss;
1115                         break;
1116                 default:
1117                         /* should never happen */
1118                         break;
1119                 }
1120         }
1121
1122         hdsp->system_sample_rate = rate;
1123
1124         return 0;
1125 }
1126
1127 /*----------------------------------------------------------------------------
1128    MIDI
1129   ----------------------------------------------------------------------------*/
1130
1131 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1132 {
1133         /* the hardware already does the relevant bit-mask with 0xff */
1134         if (id) {
1135                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1136         } else {
1137                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1138         }
1139 }
1140
1141 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1142 {
1143         /* the hardware already does the relevant bit-mask with 0xff */
1144         if (id) {
1145                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1146         } else {
1147                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1148         }
1149 }
1150
1151 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1152 {
1153         if (id) {
1154                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1155         } else {
1156                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1157         }
1158 }
1159
1160 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1161 {
1162         int fifo_bytes_used;
1163
1164         if (id) {
1165                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1166         } else {
1167                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1168         }
1169
1170         if (fifo_bytes_used < 128) {
1171                 return  128 - fifo_bytes_used;
1172         } else {
1173                 return 0;
1174         }
1175 }
1176
1177 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1178 {
1179         while (snd_hdsp_midi_input_available (hdsp, id)) {
1180                 snd_hdsp_midi_read_byte (hdsp, id);
1181         }
1182 }
1183
1184 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1185 {
1186         unsigned long flags;
1187         int n_pending;
1188         int to_write;
1189         int i;
1190         unsigned char buf[128];
1191
1192         /* Output is not interrupt driven */
1193
1194         spin_lock_irqsave (&hmidi->lock, flags);
1195         if (hmidi->output) {
1196                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1197                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1198                                 if (n_pending > (int)sizeof (buf))
1199                                         n_pending = sizeof (buf);
1200
1201                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1202                                         for (i = 0; i < to_write; ++i)
1203                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1204                                 }
1205                         }
1206                 }
1207         }
1208         spin_unlock_irqrestore (&hmidi->lock, flags);
1209         return 0;
1210 }
1211
1212 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1213 {
1214         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1215         unsigned long flags;
1216         int n_pending;
1217         int i;
1218
1219         spin_lock_irqsave (&hmidi->lock, flags);
1220         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1221                 if (hmidi->input) {
1222                         if (n_pending > (int)sizeof (buf)) {
1223                                 n_pending = sizeof (buf);
1224                         }
1225                         for (i = 0; i < n_pending; ++i) {
1226                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1227                         }
1228                         if (n_pending) {
1229                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1230                         }
1231                 } else {
1232                         /* flush the MIDI input FIFO */
1233                         while (--n_pending) {
1234                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1235                         }
1236                 }
1237         }
1238         hmidi->pending = 0;
1239         if (hmidi->id) {
1240                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1241         } else {
1242                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1243         }
1244         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1245         spin_unlock_irqrestore (&hmidi->lock, flags);
1246         return snd_hdsp_midi_output_write (hmidi);
1247 }
1248
1249 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1250 {
1251         hdsp_t *hdsp;
1252         hdsp_midi_t *hmidi;
1253         unsigned long flags;
1254         u32 ie;
1255
1256         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1257         hdsp = hmidi->hdsp;
1258         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1259         spin_lock_irqsave (&hdsp->lock, flags);
1260         if (up) {
1261                 if (!(hdsp->control_register & ie)) {
1262                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1263                         hdsp->control_register |= ie;
1264                 }
1265         } else {
1266                 hdsp->control_register &= ~ie;
1267                 tasklet_kill(&hdsp->midi_tasklet);
1268         }
1269
1270         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1271         spin_unlock_irqrestore (&hdsp->lock, flags);
1272 }
1273
1274 static void snd_hdsp_midi_output_timer(unsigned long data)
1275 {
1276         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1277         unsigned long flags;
1278
1279         snd_hdsp_midi_output_write(hmidi);
1280         spin_lock_irqsave (&hmidi->lock, flags);
1281
1282         /* this does not bump hmidi->istimer, because the
1283            kernel automatically removed the timer when it
1284            expired, and we are now adding it back, thus
1285            leaving istimer wherever it was set before.
1286         */
1287
1288         if (hmidi->istimer) {
1289                 hmidi->timer.expires = 1 + jiffies;
1290                 add_timer(&hmidi->timer);
1291         }
1292
1293         spin_unlock_irqrestore (&hmidi->lock, flags);
1294 }
1295
1296 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1297 {
1298         hdsp_midi_t *hmidi;
1299         unsigned long flags;
1300
1301         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1302         spin_lock_irqsave (&hmidi->lock, flags);
1303         if (up) {
1304                 if (!hmidi->istimer) {
1305                         init_timer(&hmidi->timer);
1306                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1307                         hmidi->timer.data = (unsigned long) hmidi;
1308                         hmidi->timer.expires = 1 + jiffies;
1309                         add_timer(&hmidi->timer);
1310                         hmidi->istimer++;
1311                 }
1312         } else {
1313                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1314                         del_timer (&hmidi->timer);
1315                 }
1316         }
1317         spin_unlock_irqrestore (&hmidi->lock, flags);
1318         if (up)
1319                 snd_hdsp_midi_output_write(hmidi);
1320 }
1321
1322 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1323 {
1324         hdsp_midi_t *hmidi;
1325
1326         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1327         spin_lock_irq (&hmidi->lock);
1328         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1329         hmidi->input = substream;
1330         spin_unlock_irq (&hmidi->lock);
1331
1332         return 0;
1333 }
1334
1335 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1336 {
1337         hdsp_midi_t *hmidi;
1338
1339         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1340         spin_lock_irq (&hmidi->lock);
1341         hmidi->output = substream;
1342         spin_unlock_irq (&hmidi->lock);
1343
1344         return 0;
1345 }
1346
1347 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1348 {
1349         hdsp_midi_t *hmidi;
1350
1351         snd_hdsp_midi_input_trigger (substream, 0);
1352
1353         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1354         spin_lock_irq (&hmidi->lock);
1355         hmidi->input = NULL;
1356         spin_unlock_irq (&hmidi->lock);
1357
1358         return 0;
1359 }
1360
1361 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1362 {
1363         hdsp_midi_t *hmidi;
1364
1365         snd_hdsp_midi_output_trigger (substream, 0);
1366
1367         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1368         spin_lock_irq (&hmidi->lock);
1369         hmidi->output = NULL;
1370         spin_unlock_irq (&hmidi->lock);
1371
1372         return 0;
1373 }
1374
1375 static snd_rawmidi_ops_t snd_hdsp_midi_output =
1376 {
1377         .open =         snd_hdsp_midi_output_open,
1378         .close =        snd_hdsp_midi_output_close,
1379         .trigger =      snd_hdsp_midi_output_trigger,
1380 };
1381
1382 static snd_rawmidi_ops_t snd_hdsp_midi_input =
1383 {
1384         .open =         snd_hdsp_midi_input_open,
1385         .close =        snd_hdsp_midi_input_close,
1386         .trigger =      snd_hdsp_midi_input_trigger,
1387 };
1388
1389 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1390 {
1391         char buf[32];
1392
1393         hdsp->midi[id].id = id;
1394         hdsp->midi[id].rmidi = NULL;
1395         hdsp->midi[id].input = NULL;
1396         hdsp->midi[id].output = NULL;
1397         hdsp->midi[id].hdsp = hdsp;
1398         hdsp->midi[id].istimer = 0;
1399         hdsp->midi[id].pending = 0;
1400         spin_lock_init (&hdsp->midi[id].lock);
1401
1402         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1403         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1404                 return -1;
1405         }
1406
1407         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1408         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1409
1410         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1411         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1412
1413         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1414                 SNDRV_RAWMIDI_INFO_INPUT |
1415                 SNDRV_RAWMIDI_INFO_DUPLEX;
1416
1417         return 0;
1418 }
1419
1420 /*-----------------------------------------------------------------------------
1421   Control Interface
1422   ----------------------------------------------------------------------------*/
1423
1424 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1425 {
1426         u32 val = 0;
1427         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1428         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1429         if (val & HDSP_SPDIFProfessional)
1430                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1431         else
1432                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1433         return val;
1434 }
1435
1436 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1437 {
1438         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1439                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1440         if (val & HDSP_SPDIFProfessional)
1441                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1442         else
1443                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1444 }
1445
1446 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1447 {
1448         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1449         uinfo->count = 1;
1450         return 0;
1451 }
1452
1453 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1454 {
1455         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1456
1457         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1458         return 0;
1459 }
1460
1461 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1462 {
1463         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1464         int change;
1465         u32 val;
1466
1467         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1468         spin_lock_irq(&hdsp->lock);
1469         change = val != hdsp->creg_spdif;
1470         hdsp->creg_spdif = val;
1471         spin_unlock_irq(&hdsp->lock);
1472         return change;
1473 }
1474
1475 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1476 {
1477         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1478         uinfo->count = 1;
1479         return 0;
1480 }
1481
1482 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1483 {
1484         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1485
1486         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1487         return 0;
1488 }
1489
1490 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1491 {
1492         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1493         int change;
1494         u32 val;
1495
1496         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1497         spin_lock_irq(&hdsp->lock);
1498         change = val != hdsp->creg_spdif_stream;
1499         hdsp->creg_spdif_stream = val;
1500         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1501         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1502         spin_unlock_irq(&hdsp->lock);
1503         return change;
1504 }
1505
1506 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1507 {
1508         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1509         uinfo->count = 1;
1510         return 0;
1511 }
1512
1513 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1514 {
1515         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1516         return 0;
1517 }
1518
1519 #define HDSP_SPDIF_IN(xname, xindex) \
1520 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1521   .name = xname, \
1522   .index = xindex, \
1523   .info = snd_hdsp_info_spdif_in, \
1524   .get = snd_hdsp_get_spdif_in, \
1525   .put = snd_hdsp_put_spdif_in }
1526
1527 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1528 {
1529         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1530 }
1531
1532 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1533 {
1534         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1535         hdsp->control_register |= hdsp_encode_spdif_in(in);
1536         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1537         return 0;
1538 }
1539
1540 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1541 {
1542         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1543         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1544
1545         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1546         uinfo->count = 1;
1547         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1548         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1549                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1550         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1551         return 0;
1552 }
1553
1554 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1555 {
1556         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1557
1558         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1559         return 0;
1560 }
1561
1562 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1563 {
1564         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1565         int change;
1566         unsigned int val;
1567
1568         if (!snd_hdsp_use_is_exclusive(hdsp))
1569                 return -EBUSY;
1570         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1571         spin_lock_irq(&hdsp->lock);
1572         change = val != hdsp_spdif_in(hdsp);
1573         if (change)
1574                 hdsp_set_spdif_input(hdsp, val);
1575         spin_unlock_irq(&hdsp->lock);
1576         return change;
1577 }
1578
1579 #define HDSP_SPDIF_OUT(xname, xindex) \
1580 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1581   .info = snd_hdsp_info_spdif_bits, \
1582   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1583
1584 static int hdsp_spdif_out(hdsp_t *hdsp)
1585 {
1586         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1587 }
1588
1589 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1590 {
1591         if (out) {
1592                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1593         } else {
1594                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1595         }
1596         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1597         return 0;
1598 }
1599
1600 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1601 {
1602         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1603         uinfo->count = 1;
1604         uinfo->value.integer.min = 0;
1605         uinfo->value.integer.max = 1;
1606         return 0;
1607 }
1608
1609 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1610 {
1611         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1612
1613         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1614         return 0;
1615 }
1616
1617 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1618 {
1619         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1620         int change;
1621         unsigned int val;
1622
1623         if (!snd_hdsp_use_is_exclusive(hdsp))
1624                 return -EBUSY;
1625         val = ucontrol->value.integer.value[0] & 1;
1626         spin_lock_irq(&hdsp->lock);
1627         change = (int)val != hdsp_spdif_out(hdsp);
1628         hdsp_set_spdif_output(hdsp, val);
1629         spin_unlock_irq(&hdsp->lock);
1630         return change;
1631 }
1632
1633 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1634 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1635   .info = snd_hdsp_info_spdif_bits, \
1636   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1637
1638 static int hdsp_spdif_professional(hdsp_t *hdsp)
1639 {
1640         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1641 }
1642
1643 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1644 {
1645         if (val) {
1646                 hdsp->control_register |= HDSP_SPDIFProfessional;
1647         } else {
1648                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1649         }
1650         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1651         return 0;
1652 }
1653
1654 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1655 {
1656         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1657
1658         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1659         return 0;
1660 }
1661
1662 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1663 {
1664         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1665         int change;
1666         unsigned int val;
1667
1668         if (!snd_hdsp_use_is_exclusive(hdsp))
1669                 return -EBUSY;
1670         val = ucontrol->value.integer.value[0] & 1;
1671         spin_lock_irq(&hdsp->lock);
1672         change = (int)val != hdsp_spdif_professional(hdsp);
1673         hdsp_set_spdif_professional(hdsp, val);
1674         spin_unlock_irq(&hdsp->lock);
1675         return change;
1676 }
1677
1678 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1679 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1680   .info = snd_hdsp_info_spdif_bits, \
1681   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1682
1683 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1684 {
1685         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1686 }
1687
1688 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1689 {
1690         if (val) {
1691                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1692         } else {
1693                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1694         }
1695         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1696         return 0;
1697 }
1698
1699 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1700 {
1701         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1702
1703         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1704         return 0;
1705 }
1706
1707 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1708 {
1709         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1710         int change;
1711         unsigned int val;
1712
1713         if (!snd_hdsp_use_is_exclusive(hdsp))
1714                 return -EBUSY;
1715         val = ucontrol->value.integer.value[0] & 1;
1716         spin_lock_irq(&hdsp->lock);
1717         change = (int)val != hdsp_spdif_emphasis(hdsp);
1718         hdsp_set_spdif_emphasis(hdsp, val);
1719         spin_unlock_irq(&hdsp->lock);
1720         return change;
1721 }
1722
1723 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1724 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1725   .info = snd_hdsp_info_spdif_bits, \
1726   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1727
1728 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1729 {
1730         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1731 }
1732
1733 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1734 {
1735         if (val) {
1736                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1737         } else {
1738                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1739         }
1740         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1741         return 0;
1742 }
1743
1744 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1745 {
1746         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1747
1748         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1749         return 0;
1750 }
1751
1752 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1753 {
1754         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1755         int change;
1756         unsigned int val;
1757
1758         if (!snd_hdsp_use_is_exclusive(hdsp))
1759                 return -EBUSY;
1760         val = ucontrol->value.integer.value[0] & 1;
1761         spin_lock_irq(&hdsp->lock);
1762         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1763         hdsp_set_spdif_nonaudio(hdsp, val);
1764         spin_unlock_irq(&hdsp->lock);
1765         return change;
1766 }
1767
1768 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1770   .name = xname, \
1771   .index = xindex, \
1772   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1773   .info = snd_hdsp_info_spdif_sample_rate, \
1774   .get = snd_hdsp_get_spdif_sample_rate \
1775 }
1776
1777 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1778 {
1779         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1780         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1781
1782         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1783         uinfo->count = 1;
1784         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1785         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1786                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1787         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1788         return 0;
1789 }
1790
1791 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1792 {
1793         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1794
1795         switch (hdsp_spdif_sample_rate(hdsp)) {
1796         case 32000:
1797                 ucontrol->value.enumerated.item[0] = 0;
1798                 break;
1799         case 44100:
1800                 ucontrol->value.enumerated.item[0] = 1;
1801                 break;
1802         case 48000:
1803                 ucontrol->value.enumerated.item[0] = 2;
1804                 break;
1805         case 64000:
1806                 ucontrol->value.enumerated.item[0] = 3;
1807                 break;
1808         case 88200:
1809                 ucontrol->value.enumerated.item[0] = 4;
1810                 break;
1811         case 96000:
1812                 ucontrol->value.enumerated.item[0] = 5;
1813                 break;
1814         case 128000:
1815                 ucontrol->value.enumerated.item[0] = 7;
1816                 break;
1817         case 176400:
1818                 ucontrol->value.enumerated.item[0] = 8;
1819                 break;
1820         case 192000:
1821                 ucontrol->value.enumerated.item[0] = 9;
1822                 break;
1823         default:
1824                 ucontrol->value.enumerated.item[0] = 6;
1825         }
1826         return 0;
1827 }
1828
1829 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1831   .name = xname, \
1832   .index = xindex, \
1833   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834   .info = snd_hdsp_info_system_sample_rate, \
1835   .get = snd_hdsp_get_system_sample_rate \
1836 }
1837
1838 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1839 {
1840         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1841         uinfo->count = 1;
1842         return 0;
1843 }
1844
1845 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1846 {
1847         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1848
1849         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1850         return 0;
1851 }
1852
1853 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1854 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1855   .name = xname, \
1856   .index = xindex, \
1857   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1858   .info = snd_hdsp_info_autosync_sample_rate, \
1859   .get = snd_hdsp_get_autosync_sample_rate \
1860 }
1861
1862 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1863 {
1864         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1865         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1866         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1867         uinfo->count = 1;
1868         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1869         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1870                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1871         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1872         return 0;
1873 }
1874
1875 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1876 {
1877         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1878
1879         switch (hdsp_external_sample_rate(hdsp)) {
1880         case 32000:
1881                 ucontrol->value.enumerated.item[0] = 0;
1882                 break;
1883         case 44100:
1884                 ucontrol->value.enumerated.item[0] = 1;
1885                 break;
1886         case 48000:
1887                 ucontrol->value.enumerated.item[0] = 2;
1888                 break;
1889         case 64000:
1890                 ucontrol->value.enumerated.item[0] = 3;
1891                 break;
1892         case 88200:
1893                 ucontrol->value.enumerated.item[0] = 4;
1894                 break;
1895         case 96000:
1896                 ucontrol->value.enumerated.item[0] = 5;
1897                 break;
1898         case 128000:
1899                 ucontrol->value.enumerated.item[0] = 7;
1900                 break;
1901         case 176400:
1902                 ucontrol->value.enumerated.item[0] = 8;
1903                 break;
1904         case 192000:
1905                 ucontrol->value.enumerated.item[0] = 9;
1906                 break;
1907         default:
1908                 ucontrol->value.enumerated.item[0] = 6;
1909         }
1910         return 0;
1911 }
1912
1913 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1914 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1915   .name = xname, \
1916   .index = xindex, \
1917   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1918   .info = snd_hdsp_info_system_clock_mode, \
1919   .get = snd_hdsp_get_system_clock_mode \
1920 }
1921
1922 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1923 {
1924         if (hdsp->control_register & HDSP_ClockModeMaster) {
1925                 return 0;
1926         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
1927                         return 0;
1928         }
1929         return 1;
1930 }
1931
1932 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1933 {
1934         static char *texts[] = {"Master", "Slave" };
1935
1936         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1937         uinfo->count = 1;
1938         uinfo->value.enumerated.items = 2;
1939         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1940                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1941         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1942         return 0;
1943 }
1944
1945 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1946 {
1947         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1948
1949         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1950         return 0;
1951 }
1952
1953 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1954 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1955   .name = xname, \
1956   .index = xindex, \
1957   .info = snd_hdsp_info_clock_source, \
1958   .get = snd_hdsp_get_clock_source, \
1959   .put = snd_hdsp_put_clock_source \
1960 }
1961
1962 static int hdsp_clock_source(hdsp_t *hdsp)
1963 {
1964         if (hdsp->control_register & HDSP_ClockModeMaster) {
1965                 switch (hdsp->system_sample_rate) {
1966                 case 32000:
1967                         return 1;
1968                 case 44100:
1969                         return 2;
1970                 case 48000:
1971                         return 3;
1972                 case 64000:
1973                         return 4;
1974                 case 88200:
1975                         return 5;
1976                 case 96000:
1977                         return 6;
1978                 case 128000:
1979                         return 7;
1980                 case 176400:
1981                         return 8;
1982                 case 192000:
1983                         return 9;
1984                 default:
1985                         return 3;
1986                 }
1987         } else {
1988                 return 0;
1989         }
1990 }
1991
1992 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
1993 {
1994         int rate;
1995         switch (mode) {
1996         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1997                 if (hdsp_external_sample_rate(hdsp) != 0) {
1998                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1999                         hdsp->control_register &= ~HDSP_ClockModeMaster;
2000                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2001                         return 0;
2002                     }
2003                 }
2004                 return -1;
2005         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2006                 rate = 32000;
2007                 break;
2008         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2009                 rate = 44100;
2010                 break;
2011         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2012                 rate = 48000;
2013                 break;
2014         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2015                 rate = 64000;
2016                 break;
2017         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2018                 rate = 88200;
2019                 break;
2020         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2021                 rate = 96000;
2022                 break;
2023         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2024                 rate = 128000;
2025                 break;
2026         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2027                 rate = 176400;
2028                 break;
2029         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2030                 rate = 192000;
2031                 break;
2032         default:
2033                 rate = 48000;
2034         }
2035         hdsp->control_register |= HDSP_ClockModeMaster;
2036         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2037         hdsp_set_rate(hdsp, rate, 1);
2038         return 0;
2039 }
2040
2041 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2042 {
2043         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2044         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2045
2046         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2047         uinfo->count = 1;
2048         if (hdsp->io_type == H9632)
2049             uinfo->value.enumerated.items = 10;
2050         else
2051             uinfo->value.enumerated.items = 7;
2052         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2053                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2054         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2055         return 0;
2056 }
2057
2058 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2059 {
2060         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2061
2062         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2063         return 0;
2064 }
2065
2066 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2067 {
2068         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2069         int change;
2070         int val;
2071
2072         if (!snd_hdsp_use_is_exclusive(hdsp))
2073                 return -EBUSY;
2074         val = ucontrol->value.enumerated.item[0];
2075         if (val < 0) val = 0;
2076         if (hdsp->io_type == H9632) {
2077             if (val > 9) val = 9;
2078         } else {
2079             if (val > 6) val = 6;
2080         }
2081         spin_lock_irq(&hdsp->lock);
2082         if (val != hdsp_clock_source(hdsp)) {
2083                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2084         } else {
2085                 change = 0;
2086         }
2087         spin_unlock_irq(&hdsp->lock);
2088         return change;
2089 }
2090
2091 static int snd_hdsp_info_clock_source_lock(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2092 {
2093         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2094         uinfo->count = 1;
2095         uinfo->value.integer.min = 0;
2096         uinfo->value.integer.max = 1;
2097         return 0;
2098 }
2099
2100 static int snd_hdsp_get_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2101 {
2102         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2103
2104         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2105         return 0;
2106 }
2107
2108 static int snd_hdsp_put_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2109 {
2110         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2111         int change;
2112
2113         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2114         if (change)
2115                 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2116         return change;
2117 }
2118
2119 #define HDSP_DA_GAIN(xname, xindex) \
2120 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2121   .name = xname, \
2122   .index = xindex, \
2123   .info = snd_hdsp_info_da_gain, \
2124   .get = snd_hdsp_get_da_gain, \
2125   .put = snd_hdsp_put_da_gain \
2126 }
2127
2128 static int hdsp_da_gain(hdsp_t *hdsp)
2129 {
2130         switch (hdsp->control_register & HDSP_DAGainMask) {
2131         case HDSP_DAGainHighGain:
2132                 return 0;
2133         case HDSP_DAGainPlus4dBu:
2134                 return 1;
2135         case HDSP_DAGainMinus10dBV:
2136                 return 2;
2137         default:
2138                 return 1;
2139         }
2140 }
2141
2142 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2143 {
2144         hdsp->control_register &= ~HDSP_DAGainMask;
2145         switch (mode) {
2146         case 0:
2147                 hdsp->control_register |= HDSP_DAGainHighGain;
2148                 break;
2149         case 1:
2150                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2151                 break;
2152         case 2:
2153                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2154                 break;
2155         default:
2156                 return -1;
2157
2158         }
2159         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2160         return 0;
2161 }
2162
2163 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2164 {
2165         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2166
2167         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2168         uinfo->count = 1;
2169         uinfo->value.enumerated.items = 3;
2170         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2171                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2172         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2173         return 0;
2174 }
2175
2176 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2177 {
2178         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2179
2180         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2181         return 0;
2182 }
2183
2184 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2185 {
2186         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2187         int change;
2188         int val;
2189
2190         if (!snd_hdsp_use_is_exclusive(hdsp))
2191                 return -EBUSY;
2192         val = ucontrol->value.enumerated.item[0];
2193         if (val < 0) val = 0;
2194         if (val > 2) val = 2;
2195         spin_lock_irq(&hdsp->lock);
2196         if (val != hdsp_da_gain(hdsp)) {
2197                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2198         } else {
2199                 change = 0;
2200         }
2201         spin_unlock_irq(&hdsp->lock);
2202         return change;
2203 }
2204
2205 #define HDSP_AD_GAIN(xname, xindex) \
2206 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2207   .name = xname, \
2208   .index = xindex, \
2209   .info = snd_hdsp_info_ad_gain, \
2210   .get = snd_hdsp_get_ad_gain, \
2211   .put = snd_hdsp_put_ad_gain \
2212 }
2213
2214 static int hdsp_ad_gain(hdsp_t *hdsp)
2215 {
2216         switch (hdsp->control_register & HDSP_ADGainMask) {
2217         case HDSP_ADGainMinus10dBV:
2218                 return 0;
2219         case HDSP_ADGainPlus4dBu:
2220                 return 1;
2221         case HDSP_ADGainLowGain:
2222                 return 2;
2223         default:
2224                 return 1;
2225         }
2226 }
2227
2228 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2229 {
2230         hdsp->control_register &= ~HDSP_ADGainMask;
2231         switch (mode) {
2232         case 0:
2233                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2234                 break;
2235         case 1:
2236                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2237                 break;
2238         case 2:
2239                 hdsp->control_register |= HDSP_ADGainLowGain;
2240                 break;
2241         default:
2242                 return -1;
2243
2244         }
2245         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2246         return 0;
2247 }
2248
2249 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2250 {
2251         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2252
2253         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2254         uinfo->count = 1;
2255         uinfo->value.enumerated.items = 3;
2256         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2257                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2258         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2259         return 0;
2260 }
2261
2262 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2263 {
2264         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2265
2266         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2267         return 0;
2268 }
2269
2270 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2271 {
2272         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2273         int change;
2274         int val;
2275
2276         if (!snd_hdsp_use_is_exclusive(hdsp))
2277                 return -EBUSY;
2278         val = ucontrol->value.enumerated.item[0];
2279         if (val < 0) val = 0;
2280         if (val > 2) val = 2;
2281         spin_lock_irq(&hdsp->lock);
2282         if (val != hdsp_ad_gain(hdsp)) {
2283                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2284         } else {
2285                 change = 0;
2286         }
2287         spin_unlock_irq(&hdsp->lock);
2288         return change;
2289 }
2290
2291 #define HDSP_PHONE_GAIN(xname, xindex) \
2292 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2293   .name = xname, \
2294   .index = xindex, \
2295   .info = snd_hdsp_info_phone_gain, \
2296   .get = snd_hdsp_get_phone_gain, \
2297   .put = snd_hdsp_put_phone_gain \
2298 }
2299
2300 static int hdsp_phone_gain(hdsp_t *hdsp)
2301 {
2302         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2303         case HDSP_PhoneGain0dB:
2304                 return 0;
2305         case HDSP_PhoneGainMinus6dB:
2306                 return 1;
2307         case HDSP_PhoneGainMinus12dB:
2308                 return 2;
2309         default:
2310                 return 0;
2311         }
2312 }
2313
2314 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2315 {
2316         hdsp->control_register &= ~HDSP_PhoneGainMask;
2317         switch (mode) {
2318         case 0:
2319                 hdsp->control_register |= HDSP_PhoneGain0dB;
2320                 break;
2321         case 1:
2322                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2323                 break;
2324         case 2:
2325                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2326                 break;
2327         default:
2328                 return -1;
2329
2330         }
2331         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2332         return 0;
2333 }
2334
2335 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2336 {
2337         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2338
2339         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2340         uinfo->count = 1;
2341         uinfo->value.enumerated.items = 3;
2342         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2343                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2344         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2345         return 0;
2346 }
2347
2348 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2349 {
2350         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2351
2352         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2353         return 0;
2354 }
2355
2356 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2357 {
2358         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2359         int change;
2360         int val;
2361
2362         if (!snd_hdsp_use_is_exclusive(hdsp))
2363                 return -EBUSY;
2364         val = ucontrol->value.enumerated.item[0];
2365         if (val < 0) val = 0;
2366         if (val > 2) val = 2;
2367         spin_lock_irq(&hdsp->lock);
2368         if (val != hdsp_phone_gain(hdsp)) {
2369                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2370         } else {
2371                 change = 0;
2372         }
2373         spin_unlock_irq(&hdsp->lock);
2374         return change;
2375 }
2376
2377 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2378 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2379   .name = xname, \
2380   .index = xindex, \
2381   .info = snd_hdsp_info_xlr_breakout_cable, \
2382   .get = snd_hdsp_get_xlr_breakout_cable, \
2383   .put = snd_hdsp_put_xlr_breakout_cable \
2384 }
2385
2386 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2387 {
2388         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2389                 return 1;
2390         }
2391         return 0;
2392 }
2393
2394 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2395 {
2396         if (mode) {
2397                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2398         } else {
2399                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2400         }
2401         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2402         return 0;
2403 }
2404
2405 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2406 {
2407         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2408         uinfo->count = 1;
2409         uinfo->value.integer.min = 0;
2410         uinfo->value.integer.max = 1;
2411         return 0;
2412 }
2413
2414 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2415 {
2416         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2417
2418         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2419         return 0;
2420 }
2421
2422 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2423 {
2424         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2425         int change;
2426         int val;
2427
2428         if (!snd_hdsp_use_is_exclusive(hdsp))
2429                 return -EBUSY;
2430         val = ucontrol->value.integer.value[0] & 1;
2431         spin_lock_irq(&hdsp->lock);
2432         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2433         hdsp_set_xlr_breakout_cable(hdsp, val);
2434         spin_unlock_irq(&hdsp->lock);
2435         return change;
2436 }
2437
2438 /* (De)activates old RME Analog Extension Board
2439    These are connected to the internal ADAT connector
2440    Switching this on desactivates external ADAT
2441 */
2442 #define HDSP_AEB(xname, xindex) \
2443 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2444   .name = xname, \
2445   .index = xindex, \
2446   .info = snd_hdsp_info_aeb, \
2447   .get = snd_hdsp_get_aeb, \
2448   .put = snd_hdsp_put_aeb \
2449 }
2450
2451 static int hdsp_aeb(hdsp_t *hdsp)
2452 {
2453         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2454                 return 1;
2455         }
2456         return 0;
2457 }
2458
2459 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2460 {
2461         if (mode) {
2462                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2463         } else {
2464                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2465         }
2466         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2467         return 0;
2468 }
2469
2470 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2471 {
2472         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2473         uinfo->count = 1;
2474         uinfo->value.integer.min = 0;
2475         uinfo->value.integer.max = 1;
2476         return 0;
2477 }
2478
2479 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2480 {
2481         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2482
2483         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2484         return 0;
2485 }
2486
2487 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2488 {
2489         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2490         int change;
2491         int val;
2492
2493         if (!snd_hdsp_use_is_exclusive(hdsp))
2494                 return -EBUSY;
2495         val = ucontrol->value.integer.value[0] & 1;
2496         spin_lock_irq(&hdsp->lock);
2497         change = (int)val != hdsp_aeb(hdsp);
2498         hdsp_set_aeb(hdsp, val);
2499         spin_unlock_irq(&hdsp->lock);
2500         return change;
2501 }
2502
2503 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2504 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2505   .name = xname, \
2506   .index = xindex, \
2507   .info = snd_hdsp_info_pref_sync_ref, \
2508   .get = snd_hdsp_get_pref_sync_ref, \
2509   .put = snd_hdsp_put_pref_sync_ref \
2510 }
2511
2512 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2513 {
2514         /* Notice that this looks at the requested sync source,
2515            not the one actually in use.
2516         */
2517
2518         switch (hdsp->control_register & HDSP_SyncRefMask) {
2519         case HDSP_SyncRef_ADAT1:
2520                 return HDSP_SYNC_FROM_ADAT1;
2521         case HDSP_SyncRef_ADAT2:
2522                 return HDSP_SYNC_FROM_ADAT2;
2523         case HDSP_SyncRef_ADAT3:
2524                 return HDSP_SYNC_FROM_ADAT3;
2525         case HDSP_SyncRef_SPDIF:
2526                 return HDSP_SYNC_FROM_SPDIF;
2527         case HDSP_SyncRef_WORD:
2528                 return HDSP_SYNC_FROM_WORD;
2529         case HDSP_SyncRef_ADAT_SYNC:
2530                 return HDSP_SYNC_FROM_ADAT_SYNC;
2531         default:
2532                 return HDSP_SYNC_FROM_WORD;
2533         }
2534         return 0;
2535 }
2536
2537 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2538 {
2539         hdsp->control_register &= ~HDSP_SyncRefMask;
2540         switch (pref) {
2541         case HDSP_SYNC_FROM_ADAT1:
2542                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2543                 break;
2544         case HDSP_SYNC_FROM_ADAT2:
2545                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2546                 break;
2547         case HDSP_SYNC_FROM_ADAT3:
2548                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2549                 break;
2550         case HDSP_SYNC_FROM_SPDIF:
2551                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2552                 break;
2553         case HDSP_SYNC_FROM_WORD:
2554                 hdsp->control_register |= HDSP_SyncRef_WORD;
2555                 break;
2556         case HDSP_SYNC_FROM_ADAT_SYNC:
2557                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2558                 break;
2559         default:
2560                 return -1;
2561         }
2562         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2563         return 0;
2564 }
2565
2566 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2567 {
2568         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2569         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2570
2571         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2572         uinfo->count = 1;
2573
2574         switch (hdsp->io_type) {
2575         case Digiface:
2576         case H9652:
2577                 uinfo->value.enumerated.items = 6;
2578                 break;
2579         case Multiface:
2580                 uinfo->value.enumerated.items = 4;
2581                 break;
2582         case H9632:
2583                 uinfo->value.enumerated.items = 3;
2584                 break;
2585         default:
2586                 uinfo->value.enumerated.items = 0;
2587                 break;
2588         }
2589
2590         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2591                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2592         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2593         return 0;
2594 }
2595
2596 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2597 {
2598         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2599
2600         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2601         return 0;
2602 }
2603
2604 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2605 {
2606         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2607         int change, max;
2608         unsigned int val;
2609
2610         if (!snd_hdsp_use_is_exclusive(hdsp))
2611                 return -EBUSY;
2612
2613         switch (hdsp->io_type) {
2614         case Digiface:
2615         case H9652:
2616                 max = 6;
2617                 break;
2618         case Multiface:
2619                 max = 4;
2620                 break;
2621         case H9632:
2622                 max = 3;
2623                 break;
2624         default:
2625                 return -EIO;
2626         }
2627
2628         val = ucontrol->value.enumerated.item[0] % max;
2629         spin_lock_irq(&hdsp->lock);
2630         change = (int)val != hdsp_pref_sync_ref(hdsp);
2631         hdsp_set_pref_sync_ref(hdsp, val);
2632         spin_unlock_irq(&hdsp->lock);
2633         return change;
2634 }
2635
2636 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2637 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2638   .name = xname, \
2639   .index = xindex, \
2640   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2641   .info = snd_hdsp_info_autosync_ref, \
2642   .get = snd_hdsp_get_autosync_ref, \
2643 }
2644
2645 static int hdsp_autosync_ref(hdsp_t *hdsp)
2646 {
2647         /* This looks at the autosync selected sync reference */
2648         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2649
2650         switch (status2 & HDSP_SelSyncRefMask) {
2651         case HDSP_SelSyncRef_WORD:
2652                 return HDSP_AUTOSYNC_FROM_WORD;
2653         case HDSP_SelSyncRef_ADAT_SYNC:
2654                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2655         case HDSP_SelSyncRef_SPDIF:
2656                 return HDSP_AUTOSYNC_FROM_SPDIF;
2657         case HDSP_SelSyncRefMask:
2658                 return HDSP_AUTOSYNC_FROM_NONE;
2659         case HDSP_SelSyncRef_ADAT1:
2660                 return HDSP_AUTOSYNC_FROM_ADAT1;
2661         case HDSP_SelSyncRef_ADAT2:
2662                 return HDSP_AUTOSYNC_FROM_ADAT2;
2663         case HDSP_SelSyncRef_ADAT3:
2664                 return HDSP_AUTOSYNC_FROM_ADAT3;
2665         default:
2666                 return HDSP_AUTOSYNC_FROM_WORD;
2667         }
2668         return 0;
2669 }
2670
2671 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2672 {
2673         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2674
2675         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2676         uinfo->count = 1;
2677         uinfo->value.enumerated.items = 7;
2678         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2679                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2680         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2681         return 0;
2682 }
2683
2684 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2685 {
2686         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2687
2688         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2689         return 0;
2690 }
2691
2692 #define HDSP_LINE_OUT(xname, xindex) \
2693 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2694   .name = xname, \
2695   .index = xindex, \
2696   .info = snd_hdsp_info_line_out, \
2697   .get = snd_hdsp_get_line_out, \
2698   .put = snd_hdsp_put_line_out \
2699 }
2700
2701 static int hdsp_line_out(hdsp_t *hdsp)
2702 {
2703         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2704 }
2705
2706 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2707 {
2708         if (out) {
2709                 hdsp->control_register |= HDSP_LineOut;
2710         } else {
2711                 hdsp->control_register &= ~HDSP_LineOut;
2712         }
2713         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2714         return 0;
2715 }
2716
2717 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2718 {
2719         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2720         uinfo->count = 1;
2721         uinfo->value.integer.min = 0;
2722         uinfo->value.integer.max = 1;
2723         return 0;
2724 }
2725
2726 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2727 {
2728         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2729
2730         spin_lock_irq(&hdsp->lock);
2731         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2732         spin_unlock_irq(&hdsp->lock);
2733         return 0;
2734 }
2735
2736 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2737 {
2738         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2739         int change;
2740         unsigned int val;
2741
2742         if (!snd_hdsp_use_is_exclusive(hdsp))
2743                 return -EBUSY;
2744         val = ucontrol->value.integer.value[0] & 1;
2745         spin_lock_irq(&hdsp->lock);
2746         change = (int)val != hdsp_line_out(hdsp);
2747         hdsp_set_line_output(hdsp, val);
2748         spin_unlock_irq(&hdsp->lock);
2749         return change;
2750 }
2751
2752 #define HDSP_PRECISE_POINTER(xname, xindex) \
2753 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2754   .name = xname, \
2755   .index = xindex, \
2756   .info = snd_hdsp_info_precise_pointer, \
2757   .get = snd_hdsp_get_precise_pointer, \
2758   .put = snd_hdsp_put_precise_pointer \
2759 }
2760
2761 static int hdsp_set_precise_pointer(hdsp_t *hdsp, int precise)
2762 {
2763         if (precise) {
2764                 hdsp->precise_ptr = 1;
2765         } else {
2766                 hdsp->precise_ptr = 0;
2767         }
2768         return 0;
2769 }
2770
2771 static int snd_hdsp_info_precise_pointer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2772 {
2773         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2774         uinfo->count = 1;
2775         uinfo->value.integer.min = 0;
2776         uinfo->value.integer.max = 1;
2777         return 0;
2778 }
2779
2780 static int snd_hdsp_get_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2781 {
2782         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2783
2784         spin_lock_irq(&hdsp->lock);
2785         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2786         spin_unlock_irq(&hdsp->lock);
2787         return 0;
2788 }
2789
2790 static int snd_hdsp_put_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2791 {
2792         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2793         int change;
2794         unsigned int val;
2795
2796         if (!snd_hdsp_use_is_exclusive(hdsp))
2797                 return -EBUSY;
2798         val = ucontrol->value.integer.value[0] & 1;
2799         spin_lock_irq(&hdsp->lock);
2800         change = (int)val != hdsp->precise_ptr;
2801         hdsp_set_precise_pointer(hdsp, val);
2802         spin_unlock_irq(&hdsp->lock);
2803         return change;
2804 }
2805
2806 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2807 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2808   .name = xname, \
2809   .index = xindex, \
2810   .info = snd_hdsp_info_use_midi_tasklet, \
2811   .get = snd_hdsp_get_use_midi_tasklet, \
2812   .put = snd_hdsp_put_use_midi_tasklet \
2813 }
2814
2815 static int hdsp_set_use_midi_tasklet(hdsp_t *hdsp, int use_tasklet)
2816 {
2817         if (use_tasklet) {
2818                 hdsp->use_midi_tasklet = 1;
2819         } else {
2820                 hdsp->use_midi_tasklet = 0;
2821         }
2822         return 0;
2823 }
2824
2825 static int snd_hdsp_info_use_midi_tasklet(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2826 {
2827         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2828         uinfo->count = 1;
2829         uinfo->value.integer.min = 0;
2830         uinfo->value.integer.max = 1;
2831         return 0;
2832 }
2833
2834 static int snd_hdsp_get_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2835 {
2836         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2837
2838         spin_lock_irq(&hdsp->lock);
2839         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2840         spin_unlock_irq(&hdsp->lock);
2841         return 0;
2842 }
2843
2844 static int snd_hdsp_put_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2845 {
2846         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2847         int change;
2848         unsigned int val;
2849
2850         if (!snd_hdsp_use_is_exclusive(hdsp))
2851                 return -EBUSY;
2852         val = ucontrol->value.integer.value[0] & 1;
2853         spin_lock_irq(&hdsp->lock);
2854         change = (int)val != hdsp->use_midi_tasklet;
2855         hdsp_set_use_midi_tasklet(hdsp, val);
2856         spin_unlock_irq(&hdsp->lock);
2857         return change;
2858 }
2859
2860 #define HDSP_MIXER(xname, xindex) \
2861 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2862   .name = xname, \
2863   .index = xindex, \
2864   .device = 0, \
2865   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2866                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2867   .info = snd_hdsp_info_mixer, \
2868   .get = snd_hdsp_get_mixer, \
2869   .put = snd_hdsp_put_mixer \
2870 }
2871
2872 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2873 {
2874         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2875         uinfo->count = 3;
2876         uinfo->value.integer.min = 0;
2877         uinfo->value.integer.max = 65536;
2878         uinfo->value.integer.step = 1;
2879         return 0;
2880 }
2881
2882 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2883 {
2884         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2885         int source;
2886         int destination;
2887         int addr;
2888
2889         source = ucontrol->value.integer.value[0];
2890         destination = ucontrol->value.integer.value[1];
2891
2892         if (source >= hdsp->max_channels) {
2893                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2894         } else {
2895                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2896         }
2897
2898         spin_lock_irq(&hdsp->lock);
2899         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2900         spin_unlock_irq(&hdsp->lock);
2901         return 0;
2902 }
2903
2904 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2905 {
2906         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2907         int change;
2908         int source;
2909         int destination;
2910         int gain;
2911         int addr;
2912
2913         if (!snd_hdsp_use_is_exclusive(hdsp))
2914                 return -EBUSY;
2915
2916         source = ucontrol->value.integer.value[0];
2917         destination = ucontrol->value.integer.value[1];
2918
2919         if (source >= hdsp->max_channels) {
2920                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2921         } else {
2922                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2923         }
2924
2925         gain = ucontrol->value.integer.value[2];
2926
2927         spin_lock_irq(&hdsp->lock);
2928         change = gain != hdsp_read_gain(hdsp, addr);
2929         if (change)
2930                 hdsp_write_gain(hdsp, addr, gain);
2931         spin_unlock_irq(&hdsp->lock);
2932         return change;
2933 }
2934
2935 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2936 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2937   .name = xname, \
2938   .index = xindex, \
2939   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2940   .info = snd_hdsp_info_sync_check, \
2941   .get = snd_hdsp_get_wc_sync_check \
2942 }
2943
2944 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2945 {
2946         static char *texts[] = {"No Lock", "Lock", "Sync" };
2947         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2948         uinfo->count = 1;
2949         uinfo->value.enumerated.items = 3;
2950         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2951                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2952         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2953         return 0;
2954 }
2955
2956 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2957 {
2958         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2959         if (status2 & HDSP_wc_lock) {
2960                 if (status2 & HDSP_wc_sync) {
2961                         return 2;
2962                 } else {
2963                          return 1;
2964                 }
2965         } else {
2966                 return 0;
2967         }
2968         return 0;
2969 }
2970
2971 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2972 {
2973         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2974
2975         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2976         return 0;
2977 }
2978
2979 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2980 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2981   .name = xname, \
2982   .index = xindex, \
2983   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2984   .info = snd_hdsp_info_sync_check, \
2985   .get = snd_hdsp_get_spdif_sync_check \
2986 }
2987
2988 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2989 {
2990         int status = hdsp_read(hdsp, HDSP_statusRegister);
2991         if (status & HDSP_SPDIFErrorFlag) {
2992                 return 0;
2993         } else {
2994                 if (status & HDSP_SPDIFSync) {
2995                         return 2;
2996                 } else {
2997                         return 1;
2998                 }
2999         }
3000         return 0;
3001 }
3002
3003 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3004 {
3005         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3006
3007         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3008         return 0;
3009 }
3010
3011 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3012 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3013   .name = xname, \
3014   .index = xindex, \
3015   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3016   .info = snd_hdsp_info_sync_check, \
3017   .get = snd_hdsp_get_adatsync_sync_check \
3018 }
3019
3020 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3021 {
3022         int status = hdsp_read(hdsp, HDSP_statusRegister);
3023         if (status & HDSP_TimecodeLock) {
3024                 if (status & HDSP_TimecodeSync) {
3025                         return 2;
3026                 } else {
3027                         return 1;
3028                 }
3029         } else {
3030                 return 0;
3031         }
3032 }
3033
3034 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3035 {
3036         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3037
3038         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3039         return 0;
3040 }
3041
3042 #define HDSP_ADAT_SYNC_CHECK \
3043 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3044   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3045   .info = snd_hdsp_info_sync_check, \
3046   .get = snd_hdsp_get_adat_sync_check \
3047 }
3048
3049 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3050 {
3051         int status = hdsp_read(hdsp, HDSP_statusRegister);
3052
3053         if (status & (HDSP_Lock0>>idx)) {
3054                 if (status & (HDSP_Sync0>>idx)) {
3055                         return 2;
3056                 } else {
3057                         return 1;
3058                 }
3059         } else {
3060                 return 0;
3061         }
3062 }
3063
3064 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3065 {
3066         int offset;
3067         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3068
3069         offset = ucontrol->id.index - 1;
3070         snd_assert(offset >= 0);
3071
3072         switch (hdsp->io_type) {
3073         case Digiface:
3074         case H9652:
3075                 if (offset >= 3)
3076                         return -EINVAL;
3077                 break;
3078         case Multiface:
3079         case H9632:
3080                 if (offset >= 1)
3081                         return -EINVAL;
3082                 break;
3083         default:
3084                 return -EIO;
3085         }
3086
3087         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3088         return 0;
3089 }
3090
3091 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3092 HDSP_DA_GAIN("DA Gain", 0),
3093 HDSP_AD_GAIN("AD Gain", 0),
3094 HDSP_PHONE_GAIN("Phones Gain", 0),
3095 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3096 };
3097
3098 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3099 {
3100         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3101         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3102         .info =         snd_hdsp_control_spdif_info,
3103         .get =          snd_hdsp_control_spdif_get,
3104         .put =          snd_hdsp_control_spdif_put,
3105 },
3106 {
3107         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3108         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3109         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3110         .info =         snd_hdsp_control_spdif_stream_info,
3111         .get =          snd_hdsp_control_spdif_stream_get,
3112         .put =          snd_hdsp_control_spdif_stream_put,
3113 },
3114 {
3115         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3116         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3117         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3118         .info =         snd_hdsp_control_spdif_mask_info,
3119         .get =          snd_hdsp_control_spdif_mask_get,
3120         .private_value = IEC958_AES0_NONAUDIO |
3121                          IEC958_AES0_PROFESSIONAL |
3122                          IEC958_AES0_CON_EMPHASIS,
3123 },
3124 {
3125         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3126         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3127         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3128         .info =         snd_hdsp_control_spdif_mask_info,
3129         .get =          snd_hdsp_control_spdif_mask_get,
3130         .private_value = IEC958_AES0_NONAUDIO |
3131                          IEC958_AES0_PROFESSIONAL |
3132                          IEC958_AES0_PRO_EMPHASIS,
3133 },
3134 HDSP_MIXER("Mixer", 0),
3135 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3136 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3137 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3138 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3139 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3140 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3141 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3142 {
3143         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3144         .name = "Sample Clock Source Locking",
3145         .info = snd_hdsp_info_clock_source_lock,
3146         .get = snd_hdsp_get_clock_source_lock,
3147         .put = snd_hdsp_put_clock_source_lock,
3148 },
3149 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3150 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3151 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3152 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3153 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3154 /* 'External Rate' complies with the alsa control naming scheme */
3155 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3156 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3157 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3158 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3159 HDSP_LINE_OUT("Line Out", 0),
3160 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3161 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3162 };
3163
3164 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3165 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3166
3167 static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3168 {
3169         unsigned int idx;
3170         int err;
3171         snd_kcontrol_t *kctl;
3172
3173         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3174                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3175                         return err;
3176                 }
3177                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3178                         hdsp->spdif_ctl = kctl;
3179         }
3180
3181         /* ADAT SyncCheck status */
3182         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3183         snd_hdsp_adat_sync_check.index = 1;
3184         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3185                 return err;
3186         }
3187         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3188                 for (idx = 1; idx < 3; ++idx) {
3189                         snd_hdsp_adat_sync_check.index = idx+1;
3190                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3191                                 return err;
3192                         }
3193                 }
3194         }
3195
3196         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3197         if (hdsp->io_type == H9632) {
3198                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3199                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3200                                 return err;
3201                         }
3202                 }
3203         }
3204
3205         /* AEB control for H96xx card */
3206         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3207                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3208                                 return err;
3209                 }
3210         }
3211
3212         return 0;
3213 }
3214
3215 /*------------------------------------------------------------
3216    /proc interface
3217  ------------------------------------------------------------*/
3218
3219 static void
3220 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3221 {
3222         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3223         unsigned int status;
3224         unsigned int status2;
3225         char *pref_sync_ref;
3226         char *autosync_ref;
3227         char *system_clock_mode;
3228         char *clock_source;
3229         int x;
3230
3231         if (hdsp_check_for_iobox (hdsp)) {
3232                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3233                 return;
3234         }
3235
3236         if (hdsp_check_for_firmware(hdsp)) {
3237                 if (hdsp->state & HDSP_FirmwareCached) {
3238                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3239                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3240                                 return;
3241                         }
3242                 } else {
3243                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3244                         return;
3245                 }
3246         }
3247
3248         status = hdsp_read(hdsp, HDSP_statusRegister);
3249         status2 = hdsp_read(hdsp, HDSP_status2Register);
3250
3251         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3252         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3253                     hdsp->capture_buffer, hdsp->playback_buffer);
3254         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3255                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3256         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3257         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3258         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3259         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3260         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3261         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3262         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3263         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3264         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3265         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3266
3267         snd_iprintf(buffer, "\n");
3268
3269         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3270
3271         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3272         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3273         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3274         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3275
3276         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3277
3278         snd_iprintf(buffer, "\n");
3279
3280
3281         switch (hdsp_clock_source(hdsp)) {
3282         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3283                 clock_source = "AutoSync";
3284                 break;
3285         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3286                 clock_source = "Internal 32 kHz";
3287                 break;
3288         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3289                 clock_source = "Internal 44.1 kHz";
3290                 break;
3291         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3292                 clock_source = "Internal 48 kHz";
3293                 break;
3294         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3295                 clock_source = "Internal 64 kHz";
3296                 break;
3297         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3298                 clock_source = "Internal 88.2 kHz";
3299                 break;
3300         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3301                 clock_source = "Internal 96 kHz";
3302                 break;
3303         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3304                 clock_source = "Internal 128 kHz";
3305                 break;
3306         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3307                 clock_source = "Internal 176.4 kHz";
3308                 break;
3309                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3310                 clock_source = "Internal 192 kHz";
3311                 break;
3312         default:
3313                 clock_source = "Error";
3314         }
3315         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3316
3317         if (hdsp_system_clock_mode(hdsp)) {
3318                 system_clock_mode = "Slave";
3319         } else {
3320                 system_clock_mode = "Master";
3321         }
3322
3323         switch (hdsp_pref_sync_ref (hdsp)) {
3324         case HDSP_SYNC_FROM_WORD:
3325                 pref_sync_ref = "Word Clock";
3326                 break;
3327         case HDSP_SYNC_FROM_ADAT_SYNC:
3328                 pref_sync_ref = "ADAT Sync";
3329                 break;
3330         case HDSP_SYNC_FROM_SPDIF:
3331                 pref_sync_ref = "SPDIF";
3332                 break;
3333         case HDSP_SYNC_FROM_ADAT1:
3334                 pref_sync_ref = "ADAT1";
3335                 break;
3336         case HDSP_SYNC_FROM_ADAT2:
3337                 pref_sync_ref = "ADAT2";
3338                 break;
3339         case HDSP_SYNC_FROM_ADAT3:
3340                 pref_sync_ref = "ADAT3";
3341                 break;
3342         default:
3343                 pref_sync_ref = "Word Clock";
3344                 break;
3345         }
3346         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3347
3348         switch (hdsp_autosync_ref (hdsp)) {
3349         case HDSP_AUTOSYNC_FROM_WORD:
3350                 autosync_ref = "Word Clock";
3351                 break;
3352         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3353                 autosync_ref = "ADAT Sync";
3354                 break;
3355         case HDSP_AUTOSYNC_FROM_SPDIF:
3356                 autosync_ref = "SPDIF";
3357                 break;
3358         case HDSP_AUTOSYNC_FROM_NONE:
3359                 autosync_ref = "None";
3360                 break;
3361         case HDSP_AUTOSYNC_FROM_ADAT1:
3362                 autosync_ref = "ADAT1";
3363                 break;
3364         case HDSP_AUTOSYNC_FROM_ADAT2:
3365                 autosync_ref = "ADAT2";
3366                 break;
3367         case HDSP_AUTOSYNC_FROM_ADAT3:
3368                 autosync_ref = "ADAT3";
3369                 break;
3370         default:
3371                 autosync_ref = "---";
3372                 break;
3373         }
3374         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3375
3376         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3377
3378         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3379
3380         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3381         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3382
3383         snd_iprintf(buffer, "\n");
3384
3385         switch (hdsp_spdif_in(hdsp)) {
3386         case HDSP_SPDIFIN_OPTICAL:
3387                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3388                 break;
3389         case HDSP_SPDIFIN_COAXIAL:
3390                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3391                 break;
3392         case HDSP_SPDIFIN_INTERNAL:
3393                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3394                 break;
3395         case HDSP_SPDIFIN_AES:
3396                 snd_iprintf(buffer, "IEC958 input: AES\n");
3397                 break;
3398         default:
3399                 snd_iprintf(buffer, "IEC958 input: ???\n");
3400                 break;
3401         }
3402
3403         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3404                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3405         } else {
3406                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3407         }
3408
3409         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3410                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3411         } else {
3412                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3413         }
3414
3415         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3416                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3417         } else {
3418                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3419         }
3420
3421         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3422                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3423         } else {
3424                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3425         }
3426         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3427                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3428         } else {
3429                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3430         }
3431
3432         snd_iprintf(buffer, "\n");
3433
3434         /* Sync Check */
3435         x = status & HDSP_Sync0;
3436         if (status & HDSP_Lock0) {
3437                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3438         } else {
3439                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3440         }
3441
3442         switch (hdsp->io_type) {
3443         case Digiface:
3444         case H9652:
3445                 x = status & HDSP_Sync1;
3446                 if (status & HDSP_Lock1) {
3447                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3448                 } else {
3449                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3450                 }
3451                 x = status & HDSP_Sync2;
3452                 if (status & HDSP_Lock2) {
3453                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3454                 } else {
3455                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3456                 }
3457         default:
3458                 /* relax */
3459                 break;
3460         }
3461
3462         x = status & HDSP_SPDIFSync;
3463         if (status & HDSP_SPDIFErrorFlag) {
3464                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3465         } else {
3466                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3467         }
3468
3469         x = status2 & HDSP_wc_sync;
3470         if (status2 & HDSP_wc_lock) {
3471                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3472         } else {
3473                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3474         }
3475
3476         x = status & HDSP_TimecodeSync;
3477         if (status & HDSP_TimecodeLock) {
3478                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3479         } else {
3480                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3481         }
3482
3483         snd_iprintf(buffer, "\n");
3484
3485         /* Informations about H9632 specific controls */
3486         if (hdsp->io_type == H9632) {
3487                 char *tmp;
3488
3489                 switch (hdsp_ad_gain(hdsp)) {
3490                 case 0:
3491                         tmp = "-10 dBV";
3492                         break;
3493                 case 1:
3494                         tmp = "+4 dBu";
3495                         break;
3496                 default:
3497                         tmp = "Lo Gain";
3498                         break;
3499                 }
3500                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3501
3502                 switch (hdsp_da_gain(hdsp)) {
3503                 case 0:
3504                         tmp = "Hi Gain";
3505                         break;
3506                 case 1:
3507                         tmp = "+4 dBu";
3508                         break;
3509                 default:
3510                         tmp = "-10 dBV";
3511                         break;
3512                 }
3513                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3514
3515                 switch (hdsp_phone_gain(hdsp)) {
3516                 case 0:
3517                         tmp = "0 dB";
3518                         break;
3519                 case 1:
3520                         tmp = "-6 dB";
3521                         break;
3522                 default:
3523                         tmp = "-12 dB";
3524                         break;
3525                 }
3526                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3527
3528                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3529
3530                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3531                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3532                 } else {
3533                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3534                 }
3535                 snd_iprintf(buffer, "\n");
3536         }
3537
3538 }
3539
3540 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3541 {
3542         snd_info_entry_t *entry;
3543
3544         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3545                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3546 }
3547
3548 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3549 {
3550         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3551         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3552 }
3553
3554 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3555 {
3556         unsigned long pb_bus, cb_bus;
3557
3558         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3559             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3560                 if (hdsp->capture_dma_buf.area)
3561                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3562                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3563                 return -ENOMEM;
3564         }
3565
3566         /* Align to bus-space 64K boundary */
3567
3568         cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3569         pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3570
3571         /* Tell the card where it is */
3572
3573         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3574         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3575
3576         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3577         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3578
3579         return 0;
3580 }
3581
3582 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3583 {
3584         unsigned int i;
3585
3586         /* ASSUMPTION: hdsp->lock is either held, or
3587            there is no need to hold it (e.g. during module
3588            initalization).
3589          */
3590
3591         /* set defaults:
3592
3593            SPDIF Input via Coax
3594            Master clock mode
3595            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3596                             which implies 2 4096 sample, 32Kbyte periods).
3597            Enable line out.
3598          */
3599
3600         hdsp->control_register = HDSP_ClockModeMaster |
3601                                  HDSP_SPDIFInputCoaxial |
3602                                  hdsp_encode_latency(7) |
3603                                  HDSP_LineOut;
3604
3605
3606         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3607
3608 #ifdef SNDRV_BIG_ENDIAN
3609         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3610 #else
3611         hdsp->control2_register = 0;
3612 #endif
3613         if (hdsp->io_type == H9652) {
3614                 snd_hdsp_9652_enable_mixer (hdsp);
3615         } else {
3616             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3617         }
3618
3619         hdsp_reset_hw_pointer(hdsp);
3620         hdsp_compute_period_size(hdsp);
3621
3622         /* silence everything */
3623
3624         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3625                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3626         }
3627
3628         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3629                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3630                         return -EIO;
3631                 }
3632         }
3633
3634         /* H9632 specific defaults */
3635         if (hdsp->io_type == H9632) {
3636                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3637                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3638         }
3639
3640         /* set a default rate so that the channel map is set up.
3641          */
3642
3643         hdsp_set_rate(hdsp, 48000, 1);
3644
3645         return 0;
3646 }
3647
3648 static void hdsp_midi_tasklet(unsigned long arg)
3649 {
3650         hdsp_t *hdsp = (hdsp_t *)arg;
3651
3652         if (hdsp->midi[0].pending) {
3653                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3654         }
3655         if (hdsp->midi[1].pending) {
3656                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3657         }
3658 }
3659
3660 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3661 {
3662         hdsp_t *hdsp = (hdsp_t *) dev_id;
3663         unsigned int status;
3664         int audio;
3665         int midi0;
3666         int midi1;
3667         unsigned int midi0status;
3668         unsigned int midi1status;
3669         int schedule = 0;
3670
3671         status = hdsp_read(hdsp, HDSP_statusRegister);
3672
3673         audio = status & HDSP_audioIRQPending;
3674         midi0 = status & HDSP_midi0IRQPending;
3675         midi1 = status & HDSP_midi1IRQPending;
3676
3677         if (!audio && !midi0 && !midi1) {
3678                 return IRQ_NONE;
3679         }
3680
3681         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3682
3683         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3684         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3685
3686         if (audio) {
3687                 if (hdsp->capture_substream) {
3688                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3689                 }
3690
3691                 if (hdsp->playback_substream) {
3692                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3693                 }
3694         }
3695
3696         if (midi0 && midi0status) {
3697                 if (hdsp->use_midi_tasklet) {
3698                         /* we disable interrupts for this input until processing is done */
3699                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3700                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3701                         hdsp->midi[0].pending = 1;
3702                         schedule = 1;
3703                 } else {
3704                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3705                 }
3706         }
3707         if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3708                 if (hdsp->use_midi_tasklet) {
3709                         /* we disable interrupts for this input until processing is done */
3710                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3711                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3712                         hdsp->midi[1].pending = 1;
3713                         schedule = 1;
3714                 } else {
3715                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3716                 }
3717         }
3718         if (hdsp->use_midi_tasklet && schedule)
3719                 tasklet_hi_schedule(&hdsp->midi_tasklet);
3720         return IRQ_HANDLED;
3721 }
3722
3723 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3724 {
3725         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3726         return hdsp_hw_pointer(hdsp);
3727 }
3728
3729 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3730                                              int stream,
3731                                              int channel)
3732
3733 {
3734         int mapped_channel;
3735
3736         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3737
3738         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3739                 return NULL;
3740         }
3741
3742         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3743                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3744         } else {
3745                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3746         }
3747 }
3748
3749 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3750                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3751 {
3752         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3753         char *channel_buf;
3754
3755         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3756
3757         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3758         snd_assert(channel_buf != NULL, return -EIO);
3759         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3760                 return -EFAULT;
3761         return count;
3762 }
3763
3764 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3765                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3766 {
3767         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3768         char *channel_buf;
3769
3770         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3771
3772         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3773         snd_assert(channel_buf != NULL, return -EIO);
3774         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3775                 return -EFAULT;
3776         return count;
3777 }
3778
3779 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3780                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3781 {
3782         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3783         char *channel_buf;
3784
3785         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3786         snd_assert(channel_buf != NULL, return -EIO);
3787         memset(channel_buf + pos * 4, 0, count * 4);
3788         return count;
3789 }
3790
3791 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3792 {
3793         snd_pcm_runtime_t *runtime = substream->runtime;
3794         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3795         snd_pcm_substream_t *other;
3796         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3797                 other = hdsp->capture_substream;
3798         else
3799                 other = hdsp->playback_substream;
3800         if (hdsp->running)
3801                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3802         else
3803                 runtime->status->hw_ptr = 0;
3804         if (other) {
3805                 struct list_head *pos;
3806                 snd_pcm_substream_t *s;
3807                 snd_pcm_runtime_t *oruntime = other->runtime;
3808                 snd_pcm_group_for_each(pos, substream) {
3809                         s = snd_pcm_group_substream_entry(pos);
3810                         if (s == other) {
3811                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3812                                 break;
3813                         }
3814                 }
3815         }
3816         return 0;
3817 }
3818
3819 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3820                                  snd_pcm_hw_params_t *params)
3821 {
3822         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3823         int err;
3824         pid_t this_pid;
3825         pid_t other_pid;
3826
3827         if (hdsp_check_for_iobox (hdsp)) {
3828                 return -EIO;
3829         }
3830
3831         if (hdsp_check_for_firmware(hdsp)) {
3832                 if (hdsp->state & HDSP_FirmwareCached) {
3833                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3834                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3835                         }
3836                 } else {
3837                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3838                 }
3839                 return -EIO;
3840         }
3841
3842         spin_lock_irq(&hdsp->lock);
3843
3844         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3845                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3846                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3847                 this_pid = hdsp->playback_pid;
3848                 other_pid = hdsp->capture_pid;
3849         } else {
3850                 this_pid = hdsp->capture_pid;
3851                 other_pid = hdsp->playback_pid;
3852         }
3853
3854         if ((other_pid > 0) && (this_pid != other_pid)) {
3855
3856                 /* The other stream is open, and not by the same
3857                    task as this one. Make sure that the parameters
3858                    that matter are the same.
3859                  */
3860
3861                 if (params_rate(params) != hdsp->system_sample_rate) {
3862                         spin_unlock_irq(&hdsp->lock);
3863                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3864                         return -EBUSY;
3865                 }
3866
3867                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3868                         spin_unlock_irq(&hdsp->lock);
3869                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3870                         return -EBUSY;
3871                 }
3872
3873                 /* We're fine. */
3874
3875                 spin_unlock_irq(&hdsp->lock);
3876                 return 0;
3877
3878         } else {
3879                 spin_unlock_irq(&hdsp->lock);
3880         }
3881
3882         /* how to make sure that the rate matches an externally-set one ?
3883          */
3884
3885         spin_lock_irq(&hdsp->lock);
3886         if (! hdsp->clock_source_locked) {
3887                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3888                         spin_unlock_irq(&hdsp->lock);
3889                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3890                         return err;
3891                 }
3892         }
3893         spin_unlock_irq(&hdsp->lock);
3894
3895         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3896                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3897                 return err;
3898         }
3899
3900         return 0;
3901 }
3902
3903 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3904                                     snd_pcm_channel_info_t *info)
3905 {
3906         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3907         int mapped_channel;
3908
3909         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3910
3911         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3912                 return -EINVAL;
3913         }
3914
3915         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3916         info->first = 0;
3917         info->step = 32;
3918         return 0;
3919 }
3920
3921 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3922                              unsigned int cmd, void *arg)
3923 {
3924         switch (cmd) {
3925         case SNDRV_PCM_IOCTL1_RESET:
3926         {
3927                 return snd_hdsp_reset(substream);
3928         }
3929         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3930         {
3931                 snd_pcm_channel_info_t *info = arg;
3932                 return snd_hdsp_channel_info(substream, info);
3933         }
3934         default:
3935                 break;
3936         }
3937
3938         return snd_pcm_lib_ioctl(substream, cmd, arg);
3939 }
3940
3941 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3942 {
3943         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3944         snd_pcm_substream_t *other;
3945         int running;
3946
3947         if (hdsp_check_for_iobox (hdsp)) {
3948                 return -EIO;
3949         }
3950
3951         if (hdsp_check_for_firmware(hdsp)) {
3952                 if (hdsp->state & HDSP_FirmwareCached) {
3953                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3954                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3955                         }
3956                 } else {
3957                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3958                 }
3959                 return -EIO;
3960         }
3961
3962         spin_lock(&hdsp->lock);
3963         running = hdsp->running;
3964         switch (cmd) {
3965         case SNDRV_PCM_TRIGGER_START:
3966                 running |= 1 << substream->stream;
3967                 break;
3968         case SNDRV_PCM_TRIGGER_STOP:
3969                 running &= ~(1 << substream->stream);
3970                 break;
3971         default:
3972                 snd_BUG();
3973                 spin_unlock(&hdsp->lock);
3974                 return -EINVAL;
3975         }
3976         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3977                 other = hdsp->capture_substream;
3978         else
3979                 other = hdsp->playback_substream;
3980
3981         if (other) {
3982                 struct list_head *pos;
3983                 snd_pcm_substream_t *s;
3984                 snd_pcm_group_for_each(pos, substream) {
3985                         s = snd_pcm_group_substream_entry(pos);
3986                         if (s == other) {
3987                                 snd_pcm_trigger_done(s, substream);
3988                                 if (cmd == SNDRV_PCM_TRIGGER_START)
3989                                         running |= 1 << s->stream;
3990                                 else
3991                                         running &= ~(1 << s->stream);
3992                                 goto _ok;
3993                         }
3994                 }
3995                 if (cmd == SNDRV_PCM_TRIGGER_START) {
3996                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3997                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3998                                 hdsp_silence_playback(hdsp);
3999                 } else {
4000                         if (running &&
4001                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4002                                 hdsp_silence_playback(hdsp);
4003                 }
4004         } else {
4005                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4006                                 hdsp_silence_playback(hdsp);
4007         }
4008  _ok:
4009         snd_pcm_trigger_done(substream, substream);
4010         if (!hdsp->running && running)
4011                 hdsp_start_audio(hdsp);
4012         else if (hdsp->running && !running)
4013                 hdsp_stop_audio(hdsp);
4014         hdsp->running = running;
4015         spin_unlock(&hdsp->lock);
4016
4017         return 0;
4018 }
4019
4020 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4021 {
4022         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4023         int result = 0;
4024
4025         if (hdsp_check_for_iobox (hdsp)) {
4026                 return -EIO;
4027         }
4028
4029         if (hdsp_check_for_firmware(hdsp)) {
4030                 if (hdsp->state & HDSP_FirmwareCached) {
4031                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4032                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4033                         }
4034                 } else {
4035                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4036                 }
4037                 return -EIO;
4038         }
4039
4040         spin_lock_irq(&hdsp->lock);
4041         if (!hdsp->running)
4042                 hdsp_reset_hw_pointer(hdsp);
4043         spin_unlock_irq(&hdsp->lock);
4044         return result;
4045 }
4046
4047 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4048 {
4049         .info =                 (SNDRV_PCM_INFO_MMAP |
4050                                  SNDRV_PCM_INFO_MMAP_VALID |
4051                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4052                                  SNDRV_PCM_INFO_SYNC_START |
4053                                  SNDRV_PCM_INFO_DOUBLE),
4054 #ifdef SNDRV_BIG_ENDIAN
4055         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4056 #else
4057         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4058 #endif
4059         .rates =                (SNDRV_PCM_RATE_32000 |
4060                                  SNDRV_PCM_RATE_44100 |
4061                                  SNDRV_PCM_RATE_48000 |
4062                                  SNDRV_PCM_RATE_64000 |
4063                                  SNDRV_PCM_RATE_88200 |
4064                                  SNDRV_PCM_RATE_96000),
4065         .rate_min =             32000,
4066         .rate_max =             96000,
4067         .channels_min =         14,
4068         .channels_max =         HDSP_MAX_CHANNELS,
4069         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4070         .period_bytes_min =     (64 * 4) * 10,
4071         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4072         .periods_min =          2,
4073         .periods_max =          2,
4074         .fifo_size =            0
4075 };
4076
4077 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4078 {
4079         .info =                 (SNDRV_PCM_INFO_MMAP |
4080                                  SNDRV_PCM_INFO_MMAP_VALID |
4081                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4082                                  SNDRV_PCM_INFO_SYNC_START),
4083 #ifdef SNDRV_BIG_ENDIAN
4084         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4085 #else
4086         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4087 #endif
4088         .rates =                (SNDRV_PCM_RATE_32000 |
4089                                  SNDRV_PCM_RATE_44100 |
4090                                  SNDRV_PCM_RATE_48000 |
4091                                  SNDRV_PCM_RATE_64000 |
4092                                  SNDRV_PCM_RATE_88200 |
4093                                  SNDRV_PCM_RATE_96000),
4094         .rate_min =             32000,
4095         .rate_max =             96000,
4096         .channels_min =         14,
4097         .channels_max =         HDSP_MAX_CHANNELS,
4098         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4099         .period_bytes_min =     (64 * 4) * 10,
4100         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4101         .periods_min =          2,
4102         .periods_max =          2,
4103         .fifo_size =            0
4104 };
4105
4106 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4107
4108 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4109         .count = ARRAY_SIZE(hdsp_period_sizes),
4110         .list = hdsp_period_sizes,
4111         .mask = 0
4112 };
4113
4114 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4115
4116 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4117         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4118         .list = hdsp_9632_sample_rates,
4119         .mask = 0
4120 };
4121
4122 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4123                                         snd_pcm_hw_rule_t *rule)
4124 {
4125         hdsp_t *hdsp = rule->private;
4126         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4127         if (hdsp->io_type == H9632) {
4128                 unsigned int list[3];
4129                 list[0] = hdsp->qs_in_channels;
4130                 list[1] = hdsp->ds_in_channels;
4131                 list[2] = hdsp->ss_in_channels;
4132                 return snd_interval_list(c, 3, list, 0);
4133         } else {
4134                 unsigned int list[2];
4135                 list[0] = hdsp->ds_in_channels;
4136                 list[1] = hdsp->ss_in_channels;
4137                 return snd_interval_list(c, 2, list, 0);
4138         }
4139 }
4140
4141 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4142                                         snd_pcm_hw_rule_t *rule)
4143 {
4144         unsigned int list[3];
4145         hdsp_t *hdsp = rule->private;
4146         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4147         if (hdsp->io_type == H9632) {
4148                 list[0] = hdsp->qs_out_channels;
4149                 list[1] = hdsp->ds_out_channels;
4150                 list[2] = hdsp->ss_out_channels;
4151                 return snd_interval_list(c, 3, list, 0);
4152         } else {
4153                 list[0] = hdsp->ds_out_channels;
4154                 list[1] = hdsp->ss_out_channels;
4155         }
4156         return snd_interval_list(c, 2, list, 0);
4157 }
4158
4159 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4160                                              snd_pcm_hw_rule_t *rule)
4161 {
4162         hdsp_t *hdsp = rule->private;
4163         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4164         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4165         if (r->min > 96000 && hdsp->io_type == H9632) {
4166                 snd_interval_t t = {
4167                         .min = hdsp->qs_in_channels,
4168                         .max = hdsp->qs_in_channels,
4169                         .integer = 1,
4170                 };
4171                 return snd_interval_refine(c, &t);
4172         } else if (r->min > 48000 && r->max <= 96000) {
4173                 snd_interval_t t = {
4174                         .min = hdsp->ds_in_channels,
4175                         .max = hdsp->ds_in_channels,
4176                         .integer = 1,
4177                 };
4178                 return snd_interval_refine(c, &t);
4179         } else if (r->max < 64000) {
4180                 snd_interval_t t = {
4181                         .min = hdsp->ss_in_channels,
4182                         .max = hdsp->ss_in_channels,
4183                         .integer = 1,
4184                 };
4185                 return snd_interval_refine(c, &t);
4186         }
4187         return 0;
4188 }
4189
4190 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4191                                              snd_pcm_hw_rule_t *rule)
4192 {
4193         hdsp_t *hdsp = rule->private;
4194         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4195         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4196         if (r->min > 96000 && hdsp->io_type == H9632) {
4197                 snd_interval_t t = {
4198                         .min = hdsp->qs_out_channels,
4199                         .max = hdsp->qs_out_channels,
4200                         .integer = 1,
4201                 };
4202                 return snd_interval_refine(c, &t);
4203         } else if (r->min > 48000 && r->max <= 96000) {
4204                 snd_interval_t t = {
4205                         .min = hdsp->ds_out_channels,
4206                         .max = hdsp->ds_out_channels,
4207                         .integer = 1,
4208                 };
4209                 return snd_interval_refine(c, &t);
4210         } else if (r->max < 64000) {
4211                 snd_interval_t t = {
4212                         .min = hdsp->ss_out_channels,
4213                         .max = hdsp->ss_out_channels,
4214                         .integer = 1,
4215                 };
4216                 return snd_interval_refine(c, &t);
4217         }
4218         return 0;
4219 }
4220
4221 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4222                                              snd_pcm_hw_rule_t *rule)
4223 {
4224         hdsp_t *hdsp = rule->private;
4225         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4226         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4227         if (c->min >= hdsp->ss_out_channels) {
4228                 snd_interval_t t = {
4229                         .min = 32000,
4230                         .max = 48000,
4231                         .integer = 1,
4232                 };
4233                 return snd_interval_refine(r, &t);
4234         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4235                 snd_interval_t t = {
4236                         .min = 128000,
4237                         .max = 192000,
4238                         .integer = 1,
4239                 };
4240                 return snd_interval_refine(r, &t);
4241         } else if (c->max <= hdsp->ds_out_channels) {
4242                 snd_interval_t t = {
4243                         .min = 64000,
4244                         .max = 96000,
4245                         .integer = 1,
4246                 };
4247                 return snd_interval_refine(r, &t);
4248         }
4249         return 0;
4250 }
4251
4252 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4253                                              snd_pcm_hw_rule_t *rule)
4254 {
4255         hdsp_t *hdsp = rule->private;
4256         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4257         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4258         if (c->min >= hdsp->ss_in_channels) {
4259                 snd_interval_t t = {
4260                         .min = 32000,
4261                         .max = 48000,
4262                         .integer = 1,
4263                 };
4264                 return snd_interval_refine(r, &t);
4265         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4266                 snd_interval_t t = {
4267                         .min = 128000,
4268                         .max = 192000,
4269                         .integer = 1,
4270                 };
4271                 return snd_interval_refine(r, &t);
4272         } else if (c->max <= hdsp->ds_in_channels) {
4273                 snd_interval_t t = {
4274                         .min = 64000,
4275                         .max = 96000,
4276                         .integer = 1,
4277                 };
4278                 return snd_interval_refine(r, &t);
4279         }
4280         return 0;
4281 }
4282
4283 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4284 {
4285         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4286         snd_pcm_runtime_t *runtime = substream->runtime;
4287
4288         if (hdsp_check_for_iobox (hdsp)) {
4289                 return -EIO;
4290         }
4291
4292         if (hdsp_check_for_firmware(hdsp)) {
4293                 if (hdsp->state & HDSP_FirmwareCached) {
4294                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4295                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4296                         }
4297                 } else {
4298                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4299                 }
4300                 return -EIO;
4301         }
4302
4303         spin_lock_irq(&hdsp->lock);
4304
4305         snd_pcm_set_sync(substream);
4306
4307         runtime->hw = snd_hdsp_playback_subinfo;
4308         runtime->dma_area = hdsp->playback_buffer;
4309         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4310
4311         hdsp->playback_pid = current->pid;
4312         hdsp->playback_substream = substream;
4313
4314         spin_unlock_irq(&hdsp->lock);
4315
4316         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4317         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4318         if (hdsp->clock_source_locked) {
4319                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4320         } else if (hdsp->io_type == H9632) {
4321                 runtime->hw.rate_max = 192000;
4322                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4323                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4324         }
4325         if (hdsp->io_type == H9632) {
4326                 runtime->hw.channels_min = hdsp->qs_out_channels;
4327                 runtime->hw.channels_max = hdsp->ss_out_channels;
4328         }
4329
4330         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4331                              snd_hdsp_hw_rule_out_channels, hdsp,
4332                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4333         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4334                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4335                              SNDRV_PCM_HW_PARAM_RATE, -1);
4336         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4337                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4338                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4339
4340         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4341         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4342         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4343                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4344         return 0;
4345 }
4346
4347 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4348 {
4349         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4350
4351         spin_lock_irq(&hdsp->lock);
4352
4353         hdsp->playback_pid = -1;
4354         hdsp->playback_substream = NULL;
4355
4356         spin_unlock_irq(&hdsp->lock);
4357
4358         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4359         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4360                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4361         return 0;
4362 }
4363
4364
4365 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4366 {
4367         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4368         snd_pcm_runtime_t *runtime = substream->runtime;
4369
4370         if (hdsp_check_for_iobox (hdsp)) {
4371                 return -EIO;
4372         }
4373
4374         if (hdsp_check_for_firmware(hdsp)) {
4375                 if (hdsp->state & HDSP_FirmwareCached) {
4376                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4377                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4378                         }
4379                 } else {
4380                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4381                 }
4382                 return -EIO;
4383         }
4384
4385         spin_lock_irq(&hdsp->lock);
4386
4387         snd_pcm_set_sync(substream);
4388
4389         runtime->hw = snd_hdsp_capture_subinfo;
4390         runtime->dma_area = hdsp->capture_buffer;
4391         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4392
4393         hdsp->capture_pid = current->pid;
4394         hdsp->capture_substream = substream;
4395
4396         spin_unlock_irq(&hdsp->lock);
4397
4398         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4399         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4400         if (hdsp->io_type == H9632) {
4401                 runtime->hw.channels_min = hdsp->qs_in_channels;
4402                 runtime->hw.channels_max = hdsp->ss_in_channels;
4403                 runtime->hw.rate_max = 192000;
4404                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4405                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4406         }
4407         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4408                              snd_hdsp_hw_rule_in_channels, hdsp,
4409                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4410         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4411                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4412                              SNDRV_PCM_HW_PARAM_RATE, -1);
4413         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4414                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4415                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4416         return 0;
4417 }
4418
4419 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4420 {
4421         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4422
4423         spin_lock_irq(&hdsp->lock);
4424
4425         hdsp->capture_pid = -1;
4426         hdsp->capture_substream = NULL;
4427
4428         spin_unlock_irq(&hdsp->lock);
4429         return 0;
4430 }
4431
4432 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4433 {
4434         /* we have nothing to initialize but the call is required */
4435         return 0;
4436 }
4437
4438
4439 /* helper functions for copying meter values */
4440 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4441 {
4442         u32 val = readl(src);
4443         return copy_to_user(dest, &val, 4);
4444 }
4445
4446 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4447 {
4448         u32 rms_low, rms_high;
4449         u64 rms;
4450         rms_low = readl(src_low);
4451         rms_high = readl(src_high);
4452         rms = ((u64)rms_high << 32) | rms_low;
4453         return copy_to_user(dest, &rms, 8);
4454 }
4455
4456 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4457 {
4458         u32 rms_low, rms_high;
4459         u64 rms;
4460         rms_low = readl(src_low) & 0xffffff00;
4461         rms_high = readl(src_high) & 0xffffff00;
4462         rms = ((u64)rms_high << 32) | rms_low;
4463         return copy_to_user(dest, &rms, 8);
4464 }
4465
4466 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4467 {
4468         int doublespeed = 0;
4469         int i, j, channels, ofs;
4470
4471         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4472                 doublespeed = 1;
4473         channels = doublespeed ? 14 : 26;
4474         for (i = 0, j = 0; i < 26; ++i) {
4475                 if (doublespeed && (i & 4))
4476                         continue;
4477                 ofs = HDSP_9652_peakBase - j * 4;
4478                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4479                         return -EFAULT;
4480                 ofs -= channels * 4;
4481                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4482                         return -EFAULT;
4483                 ofs -= channels * 4;
4484                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4485                         return -EFAULT;
4486                 ofs = HDSP_9652_rmsBase + j * 8;
4487                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4488                                 hdsp->iobase + ofs + 4))
4489                         return -EFAULT;
4490                 ofs += channels * 8;
4491                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4492                                 hdsp->iobase + ofs + 4))
4493                         return -EFAULT;
4494                 ofs += channels * 8;
4495                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4496                                 hdsp->iobase + ofs + 4))
4497                         return -EFAULT;
4498                 j++;
4499         }
4500         return 0;
4501 }
4502
4503 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4504 {
4505         int i, j;
4506         hdsp_9632_meters_t __iomem *m;
4507         int doublespeed = 0;
4508
4509         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4510                 doublespeed = 1;
4511         m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4512         for (i = 0, j = 0; i < 16; ++i, ++j) {
4513                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4514                         return -EFAULT;
4515                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4516                         return -EFAULT;
4517                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4518                         return -EFAULT;
4519                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4520                                 &m->input_rms_high[j]))
4521                         return -EFAULT;
4522                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4523                                 &m->playback_rms_high[j]))
4524                         return -EFAULT;
4525                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4526                                 &m->output_rms_high[j]))
4527                         return -EFAULT;
4528                 if (doublespeed && i == 3) i += 4;
4529         }
4530         return 0;
4531 }
4532
4533 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4534 {
4535         int i;
4536
4537         for (i = 0; i < 26; i++) {
4538                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4539                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4540                         return -EFAULT;
4541                 if (copy_u32_le(&peak_rms->input_peaks[i],
4542                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4543                         return -EFAULT;
4544         }
4545         for (i = 0; i < 28; i++) {
4546                 if (copy_u32_le(&peak_rms->output_peaks[i],
4547                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4548                         return -EFAULT;
4549         }
4550         for (i = 0; i < 26; ++i) {
4551                 if (copy_u64_le(&peak_rms->playback_rms[i],
4552                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4553                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4554                         return -EFAULT;
4555                 if (copy_u64_le(&peak_rms->input_rms[i],
4556                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4557                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4558                         return -EFAULT;
4559         }
4560         return 0;
4561 }
4562
4563 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4564 {
4565         hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4566         void __user *argp = (void __user *)arg;
4567
4568         switch (cmd) {
4569         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4570                 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4571
4572                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4573                         snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4574                         return -EINVAL;
4575                 }
4576
4577                 switch (hdsp->io_type) {
4578                 case H9652:
4579                         return hdsp_9652_get_peak(hdsp, peak_rms);
4580                 case H9632:
4581                         return hdsp_9632_get_peak(hdsp, peak_rms);
4582                 default:
4583                         return hdsp_get_peak(hdsp, peak_rms);
4584                 }
4585         }
4586         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4587                 hdsp_config_info_t info;
4588                 unsigned long flags;
4589                 int i;
4590
4591                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4592                         snd_printk("Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4593                         return -EINVAL;
4594                 }
4595                 spin_lock_irqsave(&hdsp->lock, flags);
4596                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4597                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4598                 if (hdsp->io_type != H9632) {
4599                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4600                 }
4601                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4602                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4603                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4604                 }
4605                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4606                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4607                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4608                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4609                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4610                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4611                 info.system_sample_rate = hdsp->system_sample_rate;
4612                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4613                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4614                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4615                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4616                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4617                 if (hdsp->io_type == H9632) {
4618                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4619                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4620                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4621                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4622
4623                 }
4624                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4625                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4626                 }
4627                 spin_unlock_irqrestore(&hdsp->lock, flags);
4628                 if (copy_to_user(argp, &info, sizeof(info)))
4629                         return -EFAULT;
4630                 break;
4631         }
4632         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4633                 hdsp_9632_aeb_t h9632_aeb;
4634
4635                 if (hdsp->io_type != H9632) return -EINVAL;
4636                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4637                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4638                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4639                         return -EFAULT;
4640                 break;
4641         }
4642         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4643                 hdsp_version_t hdsp_version;
4644                 int err;
4645
4646                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4647                 if (hdsp->io_type == Undefined) {
4648                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4649                                 return err;
4650                         }
4651                 }
4652                 hdsp_version.io_type = hdsp->io_type;
4653                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4654                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4655                         return -EFAULT;
4656                 }
4657                 break;
4658         }
4659         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4660                 hdsp_firmware_t __user *firmware;
4661                 u32 __user *firmware_data;
4662                 int err;
4663
4664                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4665                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4666                 if (hdsp->io_type == Undefined) return -EINVAL;
4667
4668                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4669                         return -EBUSY;
4670
4671                 snd_printk("Hammerfall-DSP: initializing firmware upload\n");
4672                 firmware = (hdsp_firmware_t __user *)argp;
4673
4674                 if (get_user(firmware_data, &firmware->firmware_data)) {
4675                         return -EFAULT;
4676                 }
4677
4678                 if (hdsp_check_for_iobox (hdsp)) {
4679                         return -EIO;
4680                 }
4681
4682                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4683                         return -EFAULT;
4684                 }
4685
4686                 hdsp->state |= HDSP_FirmwareCached;
4687
4688                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4689                         return err;
4690                 }
4691
4692                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4693                         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4694                                 return err;
4695                         }
4696
4697                         snd_hdsp_initialize_channels(hdsp);
4698                         snd_hdsp_initialize_midi_flush(hdsp);
4699
4700                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4701                                 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4702                             return err;
4703                         }
4704                 }
4705                 break;
4706         }
4707         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4708                 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4709                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4710                         return -EFAULT;
4711                 break;
4712         }
4713         default:
4714                 return -EINVAL;
4715         }
4716         return 0;
4717 }
4718
4719 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4720         .open =         snd_hdsp_playback_open,
4721         .close =        snd_hdsp_playback_release,
4722         .ioctl =        snd_hdsp_ioctl,
4723         .hw_params =    snd_hdsp_hw_params,
4724         .prepare =      snd_hdsp_prepare,
4725         .trigger =      snd_hdsp_trigger,
4726         .pointer =      snd_hdsp_hw_pointer,
4727         .copy =         snd_hdsp_playback_copy,
4728         .silence =      snd_hdsp_hw_silence,
4729 };
4730
4731 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4732         .open =         snd_hdsp_capture_open,
4733         .close =        snd_hdsp_capture_release,
4734         .ioctl =        snd_hdsp_ioctl,
4735         .hw_params =    snd_hdsp_hw_params,
4736         .prepare =      snd_hdsp_prepare,
4737         .trigger =      snd_hdsp_trigger,
4738         .pointer =      snd_hdsp_hw_pointer,
4739         .copy =         snd_hdsp_capture_copy,
4740 };
4741
4742 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4743                                            hdsp_t *hdsp)
4744 {
4745         snd_hwdep_t *hw;
4746         int err;
4747
4748         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4749                 return err;
4750
4751         hdsp->hwdep = hw;
4752         hw->private_data = hdsp;
4753         strcpy(hw->name, "HDSP hwdep interface");
4754
4755         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4756         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4757         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4758
4759         return 0;
4760 }
4761
4762 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp)
4763 {
4764         snd_pcm_t *pcm;
4765         int err;
4766
4767         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4768                 return err;
4769
4770         hdsp->pcm = pcm;
4771         pcm->private_data = hdsp;
4772         strcpy(pcm->name, hdsp->card_name);
4773
4774         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4775         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4776
4777         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4778
4779         return 0;
4780 }
4781
4782 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4783 {
4784         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4785         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4786 }
4787
4788 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4789 {
4790         int i;
4791
4792         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4793                 snd_printk("Hammerfall-DSP: enable_io fifo_wait failed\n");
4794                 return -EIO;
4795         }
4796
4797         for (i = 0; i < hdsp->max_channels; ++i) {
4798                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4799                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4800         }
4801
4802         return 0;
4803 }
4804
4805 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4806 {
4807         int status, aebi_channels, aebo_channels;
4808
4809         switch (hdsp->io_type) {
4810         case Digiface:
4811                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4812                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4813                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4814                 break;
4815
4816         case H9652:
4817                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4818                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4819                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4820                 break;
4821
4822         case H9632:
4823                 status = hdsp_read(hdsp, HDSP_statusRegister);
4824                 /* HDSP_AEBx bits are low when AEB are connected */
4825                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4826                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4827                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4828                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4829                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4830                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4831                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4832                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4833                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4834                 break;
4835
4836         case Multiface:
4837                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4838                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4839                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4840                 break;
4841
4842         default:
4843                 /* should never get here */
4844                 break;
4845         }
4846 }
4847
4848 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4849 {
4850         snd_hdsp_flush_midi_input (hdsp, 0);
4851         snd_hdsp_flush_midi_input (hdsp, 1);
4852 }
4853
4854 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4855 {
4856         int err;
4857
4858         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4859                 snd_printk("Hammerfall-DSP: Error creating pcm interface\n");
4860                 return err;
4861         }
4862
4863
4864         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4865                 snd_printk("Hammerfall-DSP: Error creating first midi interface\n");
4866                 return err;
4867         }
4868
4869         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4870                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4871                         snd_printk("Hammerfall-DSP: Error creating second midi interface\n");
4872                         return err;
4873                 }
4874         }
4875
4876         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4877                 snd_printk("Hammerfall-DSP: Error creating ctl interface\n");
4878                 return err;
4879         }
4880
4881         snd_hdsp_proc_init(hdsp);
4882
4883         hdsp->system_sample_rate = -1;
4884         hdsp->playback_pid = -1;
4885         hdsp->capture_pid = -1;
4886         hdsp->capture_substream = NULL;
4887         hdsp->playback_substream = NULL;
4888
4889         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4890                 snd_printk("Hammerfall-DSP: Error setting default values\n");
4891                 return err;
4892         }
4893
4894         if (!(hdsp->state & HDSP_InitializationComplete)) {
4895                 strcpy(card->shortname, "Hammerfall DSP");
4896                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4897                         hdsp->port, hdsp->irq);
4898
4899                 if ((err = snd_card_register(card)) < 0) {
4900                         snd_printk("Hammerfall-DSP: error registering card\n");
4901                         return err;
4902                 }
4903                 hdsp->state |= HDSP_InitializationComplete;
4904         }
4905
4906         return 0;
4907 }
4908
4909 #ifdef HDSP_FW_LOADER
4910 /* load firmware via hotplug fw loader */
4911 static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp)
4912 {
4913         const char *fwfile;
4914         const struct firmware *fw;
4915         int err;
4916
4917         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4918                 return 0;
4919         if (hdsp->io_type == Undefined) {
4920                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4921                         return err;
4922                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4923                         return 0;
4924         }
4925
4926         /* caution: max length of firmware filename is 30! */
4927         switch (hdsp->io_type) {
4928         case Multiface:
4929                 if (hdsp->firmware_rev == 0xa)
4930                         fwfile = "multiface_firmware.bin";
4931                 else
4932                         fwfile = "multiface_firmware_rev11.bin";
4933                 break;
4934         case Digiface:
4935                 if (hdsp->firmware_rev == 0xa)
4936                         fwfile = "digiface_firmware.bin";
4937                 else
4938                         fwfile = "digiface_firmware_rev11.bin";
4939                 break;
4940         default:
4941                 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4942                 return -EINVAL;
4943         }
4944
4945         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4946                 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4947                 return -ENOENT;
4948         }
4949         if (fw->size < sizeof(hdsp->firmware_cache)) {
4950                 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4951                            (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4952                 release_firmware(fw);
4953                 return -EINVAL;
4954         }
4955
4956         memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4957
4958         release_firmware(fw);
4959
4960         hdsp->state |= HDSP_FirmwareCached;
4961
4962         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4963                 return err;
4964
4965         if (!(hdsp->state & HDSP_InitializationComplete)) {
4966                 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4967                         return err;
4968                 }
4969
4970                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4971                         snd_printk("Hammerfall-DSP: error creating hwdep device\n");
4972                         return err;
4973                 }
4974                 snd_hdsp_initialize_channels(hdsp);
4975                 snd_hdsp_initialize_midi_flush(hdsp);
4976                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4977                         snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4978                         return err;
4979                 }
4980         }
4981         return 0;
4982 }
4983 #endif
4984
4985 static int __devinit snd_hdsp_create(snd_card_t *card,
4986                                      hdsp_t *hdsp)
4987 {
4988         struct pci_dev *pci = hdsp->pci;
4989         int err;
4990         int is_9652 = 0;
4991         int is_9632 = 0;
4992
4993         hdsp->irq = -1;
4994         hdsp->state = 0;
4995         hdsp->midi[0].rmidi = NULL;
4996         hdsp->midi[1].rmidi = NULL;
4997         hdsp->midi[0].input = NULL;
4998         hdsp->midi[1].input = NULL;
4999         hdsp->midi[0].output = NULL;
5000         hdsp->midi[1].output = NULL;
5001         hdsp->midi[0].pending = 0;
5002         hdsp->midi[1].pending = 0;
5003         spin_lock_init(&hdsp->midi[0].lock);
5004         spin_lock_init(&hdsp->midi[1].lock);
5005         hdsp->iobase = NULL;
5006         hdsp->control_register = 0;
5007         hdsp->control2_register = 0;
5008         hdsp->io_type = Undefined;
5009         hdsp->max_channels = 26;
5010
5011         hdsp->card = card;
5012
5013         spin_lock_init(&hdsp->lock);
5014
5015         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5016
5017         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5018         hdsp->firmware_rev &= 0xff;
5019
5020         /* From Martin Bjoernsen :
5021             "It is important that the card's latency timer register in
5022             the PCI configuration space is set to a value much larger
5023             than 0 by the computer's BIOS or the driver.
5024             The windows driver always sets this 8 bit register [...]
5025             to its maximum 255 to avoid problems with some computers."
5026         */
5027         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5028
5029         strcpy(card->driver, "H-DSP");
5030         strcpy(card->mixername, "Xilinx FPGA");
5031
5032         if (hdsp->firmware_rev < 0xa) {
5033                 return -ENODEV;
5034         } else if (hdsp->firmware_rev < 0x64) {
5035                 hdsp->card_name = "RME Hammerfall DSP";
5036         } else if (hdsp->firmware_rev < 0x96) {
5037                 hdsp->card_name = "RME HDSP 9652";
5038                 is_9652 = 1;
5039         } else {
5040                 hdsp->card_name = "RME HDSP 9632";
5041                 hdsp->max_channels = 16;
5042                 is_9632 = 1;
5043         }
5044
5045         if ((err = pci_enable_device(pci)) < 0) {
5046                 return err;
5047         }
5048
5049         pci_set_master(hdsp->pci);
5050
5051         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5052                 return err;
5053         hdsp->port = pci_resource_start(pci, 0);
5054         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5055                 snd_printk("Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5056                 return -EBUSY;
5057         }
5058
5059         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5060                 snd_printk("Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5061                 return -EBUSY;
5062         }
5063
5064         hdsp->irq = pci->irq;
5065         hdsp->precise_ptr = 1;
5066         hdsp->use_midi_tasklet = 1;
5067
5068         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5069                 return err;
5070         }
5071
5072         if (!is_9652 && !is_9632) {
5073                 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5074                 if ((1000 / HZ) < 2000) {
5075                         ssleep(2);
5076                 } else {
5077                         mdelay(2000);
5078                 }
5079
5080                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5081 #ifdef HDSP_FW_LOADER
5082                         if ((err = hdsp_request_fw_loader(hdsp)) < 0) {
5083                                 /* we don't fail as this can happen
5084                                    if userspace is not ready for
5085                                    firmware upload
5086                                 */
5087                                 snd_printk("Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5088                         } else {
5089                                 /* init is complete, we return */
5090                                 return 0;
5091                         }
5092 #endif
5093                         /* no iobox connected, we defer initialization */
5094                         snd_printk("Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5095                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5096                                 return err;
5097                         }
5098                         return 0;
5099                 } else {
5100                         snd_printk("Hammerfall-DSP: Firmware already present, initializing card.\n");
5101                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5102                                 hdsp->io_type = Multiface;
5103                         } else {
5104                                 hdsp->io_type = Digiface;
5105                         }
5106                 }
5107         }
5108
5109         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5110                 return err;
5111         }
5112
5113         if (is_9652) {
5114                 hdsp->io_type = H9652;
5115         }
5116
5117         if (is_9632) {
5118                 hdsp->io_type = H9632;
5119         }
5120
5121         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5122                 return err;
5123         }
5124
5125         snd_hdsp_initialize_channels(hdsp);
5126         snd_hdsp_initialize_midi_flush(hdsp);
5127
5128         hdsp->state |= HDSP_FirmwareLoaded;
5129
5130         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5131                 return err;
5132         }
5133
5134         return 0;
5135 }
5136
5137 static int snd_hdsp_free(hdsp_t *hdsp)
5138 {
5139         if (hdsp->port) {
5140                 /* stop the audio, and cancel all interrupts */
5141                 tasklet_kill(&hdsp->midi_tasklet);
5142                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5143                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5144         }
5145
5146         if (hdsp->irq >= 0)
5147                 free_irq(hdsp->irq, (void *)hdsp);
5148
5149         snd_hdsp_free_buffers(hdsp);
5150
5151         if (hdsp->iobase)
5152                 iounmap(hdsp->iobase);
5153
5154         if (hdsp->port)
5155                 pci_release_regions(hdsp->pci);
5156
5157         pci_disable_device(hdsp->pci);
5158         return 0;
5159 }
5160
5161 static void snd_hdsp_card_free(snd_card_t *card)
5162 {
5163         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5164
5165         if (hdsp)
5166                 snd_hdsp_free(hdsp);
5167 }
5168
5169 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5170                                     const struct pci_device_id *pci_id)
5171 {
5172         static int dev;
5173         hdsp_t *hdsp;
5174         snd_card_t *card;
5175         int err;
5176
5177         if (dev >= SNDRV_CARDS)
5178                 return -ENODEV;
5179         if (!enable[dev]) {
5180                 dev++;
5181                 return -ENOENT;
5182         }
5183
5184         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5185                 return -ENOMEM;
5186
5187         hdsp = (hdsp_t *) card->private_data;
5188         card->private_free = snd_hdsp_card_free;
5189         hdsp->dev = dev;
5190         hdsp->pci = pci;
5191         snd_card_set_dev(card, &pci->dev);
5192
5193         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5194                 snd_card_free(card);
5195                 return err;
5196         }
5197
5198         strcpy(card->shortname, "Hammerfall DSP");
5199         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5200                 hdsp->port, hdsp->irq);
5201
5202         if ((err = snd_card_register(card)) < 0) {
5203                 snd_card_free(card);
5204                 return err;
5205         }
5206         pci_set_drvdata(pci, card);
5207         dev++;
5208         return 0;
5209 }
5210
5211 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5212 {
5213         snd_card_free(pci_get_drvdata(pci));
5214         pci_set_drvdata(pci, NULL);
5215 }
5216
5217 static struct pci_driver driver = {
5218         .name =     "RME Hammerfall DSP",
5219         .owner =    THIS_MODULE,
5220         .id_table = snd_hdsp_ids,
5221         .probe =    snd_hdsp_probe,
5222         .remove = __devexit_p(snd_hdsp_remove),
5223 };
5224
5225 static int __init alsa_card_hdsp_init(void)
5226 {
5227         return pci_register_driver(&driver);
5228 }
5229
5230 static void __exit alsa_card_hdsp_exit(void)
5231 {
5232         pci_unregister_driver(&driver);
5233 }
5234
5235 module_init(alsa_card_hdsp_init)
5236 module_exit(alsa_card_hdsp_exit)