1 /******************************************************************************
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
29 (C) Copyright AudioScience Inc. 1998-2003
30 *******************************************************************************/
31 #define SOURCEFILE_NAME "hpi6000.c"
33 #include "hpi_internal.h"
34 #include "hpimsginit.h"
40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41 #define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43 #define HPI_HIF_ERROR_MASK 0x4000
45 /* HPI6000 specific error codes */
47 #define HPI6000_ERROR_BASE 900
48 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
49 #define HPI6000_ERROR_MSG_RESP_SEND_MSG_ACK 902
50 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
51 #define HPI6000_ERROR_MSG_GET_ADR 904
52 #define HPI6000_ERROR_RESP_GET_ADR 905
53 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
54 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
55 #define HPI6000_ERROR_MSG_INVALID_DSP_INDEX 908
56 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
58 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
59 #define HPI6000_ERROR_SEND_DATA_ACK 912
60 #define HPI6000_ERROR_SEND_DATA_ADR 913
61 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
62 #define HPI6000_ERROR_SEND_DATA_CMD 915
63 #define HPI6000_ERROR_SEND_DATA_WRITE 916
64 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
65 #define HPI6000_ERROR_SEND_DATA_VERIFY 918
67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
68 #define HPI6000_ERROR_GET_DATA_ACK 922
69 #define HPI6000_ERROR_GET_DATA_CMD 923
70 #define HPI6000_ERROR_GET_DATA_READ 924
71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925
73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952
75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
79 #define HPI6000_ERROR_MSG_RESP_BLOCKVERIFY32 963
81 /* adapter init errors */
82 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
84 /* can't access PCI2040 */
85 #define HPI6000_ERROR_INIT_PCI2040 931
86 /* can't access DSP HPI i/f */
87 #define HPI6000_ERROR_INIT_DSPHPI 932
88 /* can't access internal DSP memory */
89 #define HPI6000_ERROR_INIT_DSPINTMEM 933
90 /* can't access SDRAM - test#1 */
91 #define HPI6000_ERROR_INIT_SDRAM1 934
92 /* can't access SDRAM - test#2 */
93 #define HPI6000_ERROR_INIT_SDRAM2 935
95 #define HPI6000_ERROR_INIT_VERIFY 938
97 #define HPI6000_ERROR_INIT_NOACK 939
99 #define HPI6000_ERROR_INIT_PLDTEST1 941
100 #define HPI6000_ERROR_INIT_PLDTEST2 942
104 #define HIDE_PCI_ASSERTS
107 /* for PCI2040 i/f chip */
108 /* HPI CSR registers */
109 /* word offsets from CSR base */
110 /* use when io addresses defined as u32 * */
112 #define INTERRUPT_EVENT_SET 0
113 #define INTERRUPT_EVENT_CLEAR 1
114 #define INTERRUPT_MASK_SET 2
115 #define INTERRUPT_MASK_CLEAR 3
116 #define HPI_ERROR_REPORT 4
118 #define HPI_DATA_WIDTH 6
121 /* HPI registers, spaced 8K bytes = 2K words apart */
122 #define DSP_SPACING 0x800
124 #define CONTROL 0x0000
125 #define ADDRESS 0x0200
126 #define DATA_AUTOINC 0x0400
129 #define TIMEOUT 500000
132 __iomem u32 *prHPI_control;
133 __iomem u32 *prHPI_address;
134 __iomem u32 *prHPI_data;
135 __iomem u32 *prHPI_data_auto_inc;
136 char c_dsp_rev; /*A, B */
137 u32 control_cache_address_on_dsp;
138 u32 control_cache_length_on_dsp;
139 struct hpi_adapter_obj *pa_parent_adapter;
143 __iomem u32 *dw2040_HPICSR;
144 __iomem u32 *dw2040_HPIDSP;
147 struct dsp_obj ado[MAX_DSPS];
149 u32 message_buffer_address_on_dsp;
150 u32 response_buffer_address_on_dsp;
151 u32 pCI2040HPI_error_count;
153 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
154 struct hpi_control_cache *p_cache;
157 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
158 u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
159 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
160 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
162 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
163 u32 *pos_error_code);
164 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
169 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm);
171 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
172 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
174 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
175 struct hpi_response *phr);
177 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
180 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
181 u16 dsp_index, u32 host_cmd);
183 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
185 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
186 struct hpi_message *phm, struct hpi_response *phr);
188 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
189 struct hpi_message *phm, struct hpi_response *phr);
191 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
193 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
195 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
198 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
201 static void subsys_create_adapter(struct hpi_message *phm,
202 struct hpi_response *phr);
204 static void subsys_delete_adapter(struct hpi_message *phm,
205 struct hpi_response *phr);
207 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
208 struct hpi_message *phm, struct hpi_response *phr);
210 static short create_adapter_obj(struct hpi_adapter_obj *pao,
211 u32 *pos_error_code);
215 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
216 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
218 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
221 switch (phm->function) {
222 case HPI_SUBSYS_OPEN:
223 case HPI_SUBSYS_CLOSE:
224 case HPI_SUBSYS_GET_INFO:
225 case HPI_SUBSYS_DRIVER_UNLOAD:
226 case HPI_SUBSYS_DRIVER_LOAD:
227 case HPI_SUBSYS_FIND_ADAPTERS:
228 /* messages that should not get here */
229 phr->error = HPI_ERROR_UNIMPLEMENTED;
231 case HPI_SUBSYS_CREATE_ADAPTER:
232 subsys_create_adapter(phm, phr);
234 case HPI_SUBSYS_DELETE_ADAPTER:
235 subsys_delete_adapter(phm, phr);
238 phr->error = HPI_ERROR_INVALID_FUNC;
243 static void control_message(struct hpi_adapter_obj *pao,
244 struct hpi_message *phm, struct hpi_response *phr)
247 switch (phm->function) {
248 case HPI_CONTROL_GET_STATE:
249 if (pao->has_control_cache) {
251 err = hpi6000_update_control_cache(pao, phm);
258 if (hpi_check_control_cache(((struct hpi_hw_obj *)
259 pao->priv)->p_cache, phm,
263 hw_message(pao, phm, phr);
265 case HPI_CONTROL_GET_INFO:
266 hw_message(pao, phm, phr);
268 case HPI_CONTROL_SET_STATE:
269 hw_message(pao, phm, phr);
270 hpi_sync_control_cache(((struct hpi_hw_obj *)pao->priv)->
274 phr->error = HPI_ERROR_INVALID_FUNC;
279 static void adapter_message(struct hpi_adapter_obj *pao,
280 struct hpi_message *phm, struct hpi_response *phr)
282 switch (phm->function) {
283 case HPI_ADAPTER_GET_INFO:
284 hw_message(pao, phm, phr);
286 case HPI_ADAPTER_GET_ASSERT:
287 adapter_get_asserts(pao, phm, phr);
289 case HPI_ADAPTER_OPEN:
290 case HPI_ADAPTER_CLOSE:
291 case HPI_ADAPTER_TEST_ASSERT:
292 case HPI_ADAPTER_SELFTEST:
293 case HPI_ADAPTER_GET_MODE:
294 case HPI_ADAPTER_SET_MODE:
295 case HPI_ADAPTER_FIND_OBJECT:
296 case HPI_ADAPTER_GET_PROPERTY:
297 case HPI_ADAPTER_SET_PROPERTY:
298 case HPI_ADAPTER_ENUM_PROPERTY:
299 hw_message(pao, phm, phr);
302 phr->error = HPI_ERROR_INVALID_FUNC;
307 static void outstream_message(struct hpi_adapter_obj *pao,
308 struct hpi_message *phm, struct hpi_response *phr)
310 switch (phm->function) {
311 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
312 case HPI_OSTREAM_HOSTBUFFER_FREE:
313 /* Don't let these messages go to the HW function because
314 * they're called without allocating the spinlock.
315 * For the HPI6000 adapters the HW would return
316 * HPI_ERROR_INVALID_FUNC anyway.
318 phr->error = HPI_ERROR_INVALID_FUNC;
321 hw_message(pao, phm, phr);
326 static void instream_message(struct hpi_adapter_obj *pao,
327 struct hpi_message *phm, struct hpi_response *phr)
330 switch (phm->function) {
331 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
332 case HPI_ISTREAM_HOSTBUFFER_FREE:
333 /* Don't let these messages go to the HW function because
334 * they're called without allocating the spinlock.
335 * For the HPI6000 adapters the HW would return
336 * HPI_ERROR_INVALID_FUNC anyway.
338 phr->error = HPI_ERROR_INVALID_FUNC;
341 hw_message(pao, phm, phr);
346 /************************************************************************/
348 * Entry point from HPIMAN
349 * All calls to the HPI start here
351 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
353 struct hpi_adapter_obj *pao = NULL;
355 /* subsytem messages get executed by every HPI. */
356 /* All other messages are ignored unless the adapter index matches */
357 /* an adapter in the HPI */
358 HPI_DEBUG_LOG(DEBUG, "O %d,F %x\n", phm->object, phm->function);
360 /* if Dsp has crashed then do not communicate with it any more */
361 if (phm->object != HPI_OBJ_SUBSYSTEM) {
362 pao = hpi_find_adapter(phm->adapter_index);
365 " %d,%d refused, for another HPI?\n",
366 phm->object, phm->function);
370 if (pao->dsp_crashed >= 10) {
371 hpi_init_response(phr, phm->object, phm->function,
372 HPI_ERROR_DSP_HARDWARE);
373 HPI_DEBUG_LOG(DEBUG, " %d,%d dsp crashed.\n",
374 phm->object, phm->function);
378 /* Init default response including the size field */
379 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
380 hpi_init_response(phr, phm->object, phm->function,
381 HPI_ERROR_PROCESSING_MESSAGE);
384 case HPI_TYPE_MESSAGE:
385 switch (phm->object) {
386 case HPI_OBJ_SUBSYSTEM:
387 subsys_message(phm, phr);
390 case HPI_OBJ_ADAPTER:
392 sizeof(struct hpi_response_header) +
393 sizeof(struct hpi_adapter_res);
394 adapter_message(pao, phm, phr);
397 case HPI_OBJ_CONTROL:
398 control_message(pao, phm, phr);
401 case HPI_OBJ_OSTREAM:
402 outstream_message(pao, phm, phr);
405 case HPI_OBJ_ISTREAM:
406 instream_message(pao, phm, phr);
410 hw_message(pao, phm, phr);
416 phr->error = HPI_ERROR_INVALID_TYPE;
421 /************************************************************************/
424 /* create an adapter object and initialise it based on resource information
425 * passed in in the message
426 * NOTE - you cannot use this function AND the FindAdapters function at the
427 * same time, the application must use only one of them to get the adapters
429 static void subsys_create_adapter(struct hpi_message *phm,
430 struct hpi_response *phr)
432 /* create temp adapter obj, because we don't know what index yet */
433 struct hpi_adapter_obj ao;
434 struct hpi_adapter_obj *pao;
439 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
441 memset(&ao, 0, sizeof(ao));
443 /* this HPI only creates adapters for TI/PCI2040 based devices */
444 if (phm->u.s.resource.bus_type != HPI_BUS_PCI)
446 if (phm->u.s.resource.r.pci->vendor_id != HPI_PCI_VENDOR_ID_TI)
448 if (phm->u.s.resource.r.pci->device_id != HPI_PCI_DEV_ID_PCI2040)
451 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
453 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
454 phr->error = HPI_ERROR_MEMORY_ALLOC;
458 /* create the adapter object based on the resource information */
459 /*? memcpy(&ao.Pci,&phm->u.s.Resource.r.Pci,sizeof(ao.Pci)); */
460 ao.pci = *phm->u.s.resource.r.pci;
462 error = create_adapter_obj(&ao, &os_error_code);
464 error = hpi_add_adapter(&ao);
466 phr->u.s.data = os_error_code;
471 /* need to update paParentAdapter */
472 pao = hpi_find_adapter(ao.index);
474 /* We just added this adapter, why can't we find it!? */
475 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
480 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
481 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
482 phw->ado[dsp_index].pa_parent_adapter = pao;
485 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
486 phr->u.s.adapter_index = ao.index;
487 phr->u.s.num_adapters++;
491 static void subsys_delete_adapter(struct hpi_message *phm,
492 struct hpi_response *phr)
494 struct hpi_adapter_obj *pao = NULL;
495 struct hpi_hw_obj *phw;
497 pao = hpi_find_adapter(phm->adapter_index);
501 phw = (struct hpi_hw_obj *)pao->priv;
503 if (pao->has_control_cache)
504 hpi_free_control_cache(phw->p_cache);
506 hpi_delete_adapter(pao);
512 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
513 static short create_adapter_obj(struct hpi_adapter_obj *pao,
516 short boot_error = 0;
518 u32 control_cache_size = 0;
519 u32 control_cache_count = 0;
520 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
522 /* init error reporting */
523 pao->dsp_crashed = 0;
525 /* The PCI2040 has the following address map */
526 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
527 /* BAR1 - 32K = HPI registers on DSP */
528 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
529 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
530 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
533 /* set addresses for the possible DSP HPI interfaces */
534 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
535 phw->ado[dsp_index].prHPI_control =
536 phw->dw2040_HPIDSP + (CONTROL +
537 DSP_SPACING * dsp_index);
539 phw->ado[dsp_index].prHPI_address =
540 phw->dw2040_HPIDSP + (ADDRESS +
541 DSP_SPACING * dsp_index);
542 phw->ado[dsp_index].prHPI_data =
543 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
545 phw->ado[dsp_index].prHPI_data_auto_inc =
546 phw->dw2040_HPIDSP + (DATA_AUTOINC +
547 DSP_SPACING * dsp_index);
549 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
550 phw->ado[dsp_index].prHPI_control,
551 phw->ado[dsp_index].prHPI_address,
552 phw->ado[dsp_index].prHPI_data,
553 phw->ado[dsp_index].prHPI_data_auto_inc);
555 phw->ado[dsp_index].pa_parent_adapter = pao;
558 phw->pCI2040HPI_error_count = 0;
559 pao->has_control_cache = 0;
561 /* Set the default number of DSPs on this card */
562 /* This is (conditionally) adjusted after bootloading */
563 /* of the first DSP in the bootload section. */
566 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
570 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
572 phw->message_buffer_address_on_dsp = 0L;
573 phw->response_buffer_address_on_dsp = 0L;
575 /* get info about the adapter by asking the adapter */
576 /* send a HPI_ADAPTER_GET_INFO message */
578 struct hpi_message hM;
579 struct hpi_response hR0; /* response from DSP 0 */
580 struct hpi_response hR1; /* response from DSP 1 */
583 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
584 memset(&hM, 0, sizeof(hM));
585 hM.type = HPI_TYPE_MESSAGE;
586 hM.size = sizeof(struct hpi_message);
587 hM.object = HPI_OBJ_ADAPTER;
588 hM.function = HPI_ADAPTER_GET_INFO;
589 hM.adapter_index = 0;
590 memset(&hR0, 0, sizeof(hR0));
591 memset(&hR1, 0, sizeof(hR1));
592 hR0.size = sizeof(hR0);
593 hR1.size = sizeof(hR1);
595 error = hpi6000_message_response_sequence(pao, 0, &hM, &hR0);
597 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hR0.error);
600 if (phw->num_dsp == 2) {
601 error = hpi6000_message_response_sequence(pao, 1, &hM,
606 pao->adapter_type = hR0.u.a.adapter_type;
607 pao->index = hR0.u.a.adapter_index;
610 memset(&phw->control_cache[0], 0,
611 sizeof(struct hpi_control_cache_single) *
612 HPI_NMIXER_CONTROLS);
613 /* Read the control cache length to figure out if it is turned on */
615 hpi_read_word(&phw->ado[0],
616 HPI_HIF_ADDR(control_cache_size_in_bytes));
617 if (control_cache_size) {
618 control_cache_count =
619 hpi_read_word(&phw->ado[0],
620 HPI_HIF_ADDR(control_cache_count));
621 pao->has_control_cache = 1;
624 hpi_alloc_control_cache(control_cache_count,
625 control_cache_size, (struct hpi_control_cache_info *)
626 &phw->control_cache[0]
629 pao->has_control_cache = 0;
631 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
632 pao->adapter_type, pao->index);
633 pao->open = 0; /* upon creation the adapter is closed */
637 /************************************************************************/
640 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
641 struct hpi_message *phm, struct hpi_response *phr)
643 #ifndef HIDE_PCI_ASSERTS
644 /* if we have PCI2040 asserts then collect them */
645 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
646 phr->u.a.serial_number =
647 gw_pci_read_asserts * 100 + gw_pci_write_asserts;
648 phr->u.a.adapter_index = 1; /* assert count */
649 phr->u.a.adapter_type = -1; /* "dsp index" */
650 strcpy(phr->u.a.sz_adapter_assert, "PCI2040 error");
651 gw_pci_read_asserts = 0;
652 gw_pci_write_asserts = 0;
656 hw_message(pao, phm, phr); /*get DSP asserts */
661 /************************************************************************/
664 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
667 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
674 u32 test_addr = 0x80000000;
675 u32 test_data = 0x00000001;
676 u32 dw2040_reset = 0;
679 u32 adapter_info = 0;
682 struct dsp_code dsp_code;
683 u16 boot_load_family = 0;
685 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
687 switch (pao->pci.subsys_device_id) {
689 case 0x5110: /* ASI5100 revB or higher with C6711D */
692 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
695 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x8800);
698 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
701 /* reset all DSPs, indicate two DSPs are present
702 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
705 dw2040_reset = 0x0003000F;
706 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
708 /* read back register to make sure PCI2040 chip is functioning
709 * note that bits 4..15 are read-only and so should always return zero,
710 * even though we wrote 1 to them
712 for (i = 0; i < 1000; i++)
713 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
714 if (delay != dw2040_reset) {
715 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
717 return HPI6000_ERROR_INIT_PCI2040;
720 /* Indicate that DSP#0,1 is a C6X */
721 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
722 /* set Bit30 and 29 - which will prevent Target aborts from being
723 * issued upon HPI or GP error
725 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
727 /* isolate DSP HAD8 line from PCI2040 so that
728 * Little endian can be set by pullup
730 dw2040_reset = dw2040_reset & (~(endian << 3));
731 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
733 phw->ado[0].c_dsp_rev = 'B'; /* revB */
734 phw->ado[1].c_dsp_rev = 'B'; /* revB */
736 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
737 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
738 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
739 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
740 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
742 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
743 dw2040_reset = dw2040_reset & (~0x00000008);
744 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
745 /*delay to allow DSP to get going */
746 for (i = 0; i < 100; i++)
747 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
749 /* loop through all DSPs, downloading DSP code */
750 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
751 struct dsp_obj *pdo = &phw->ado[dsp_index];
753 /* configure DSP so that we download code into the SRAM */
754 /* set control reg for little endian, HWOB=1 */
755 iowrite32(0x00010001, pdo->prHPI_control);
757 /* test access to the HPI address register (HPIA) */
758 test_data = 0x00000001;
759 for (j = 0; j < 32; j++) {
760 iowrite32(test_data, pdo->prHPI_address);
761 data = ioread32(pdo->prHPI_address);
762 if (data != test_data) {
763 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
764 test_data, data, dsp_index);
765 return HPI6000_ERROR_INIT_DSPHPI;
767 test_data = test_data << 1;
770 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
771 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
772 * we're going to do this unconditionally
774 /* PLLDIV1 should have a value of 8000 after reset */
776 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
779 /* C6713 datasheet says we cannot program PLL from HPI,
780 * and indeed if we try to set the PLL multiply from the
781 * HPI, the PLL does not seem to lock,
782 * so we enable the PLL and use the default of x 7
785 hpi_write_word(pdo, 0x01B7C100, 0x0000);
786 for (i = 0; i < 100; i++)
787 delay = ioread32(phw->dw2040_HPICSR +
790 /* ** use default of PLL x7 ** */
791 /* EMIF = 225/3=75MHz */
792 hpi_write_word(pdo, 0x01B7C120, 0x8002);
794 hpi_write_word(pdo, 0x01B7C11C, 0x8001);
796 hpi_write_word(pdo, 0x01B7C118, 0x8000);
798 for (i = 0; i < 2000; i++)
799 delay = ioread32(phw->dw2040_HPICSR +
801 /* PLL not bypassed */
802 hpi_write_word(pdo, 0x01B7C100, 0x0001);
804 for (i = 0; i < 2000; i++)
805 delay = ioread32(phw->dw2040_HPICSR +
809 /* test r/w to internal DSP memory
810 * C6711 has L2 cache mapped to 0x0 when reset
812 * revB - because of bug 3.0.1 last HPI read
813 * (before HPI address issued) must be non-autoinc
815 /* test each bit in the 32bit word */
816 for (i = 0; i < 100; i++) {
817 test_addr = 0x00000000;
818 test_data = 0x00000001;
819 for (j = 0; j < 32; j++) {
820 hpi_write_word(pdo, test_addr + i, test_data);
821 data = hpi_read_word(pdo, test_addr + i);
822 if (data != test_data) {
824 "DSP mem %x %x %x %x\n",
825 test_addr + i, test_data,
828 return HPI6000_ERROR_INIT_DSPINTMEM;
830 test_data = test_data << 1;
834 /* memory map of ASI6200
835 00000000-0000FFFF 16Kx32 internal program
836 01800000-019FFFFF Internal peripheral
837 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
838 90000000-9000FFFF CE1 Async peripherals:
846 3 CLK2EN = 1 CLKOUT2 enabled
847 4 CLK1EN = 0 CLKOUT1 disabled
848 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
850 7 NOHOLD = 1 external HOLD disabled
851 8 HOLDA = 0 HOLDA output is low
852 9 HOLD = 0 HOLD input is low
853 10 ARDY = 1 ARDY input is high
854 11 BUSREQ = 0 BUSREQ output is low
857 hpi_write_word(pdo, 0x01800000, 0x34A8);
859 /* EMIF CE0 setup - 2Mx32 Sync DRAM
866 7..4 MTYPE 0011 Sync DRAM 32bits
870 hpi_write_word(pdo, 0x01800008, 0x00000030);
872 /* EMIF SDRAM Extension
882 6-5 TWR = 2-1 = 01b (tWR = 10ns)
883 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
884 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
885 1 CAS latency = 3 ECLK
886 (for Micron 2M32-7 operating at 100Mhz)
889 /* need to use this else DSP code crashes */
890 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
892 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
895 29..28 SDRSZ 00 11 row address pins
896 27..26 SDCSZ 01 8 column address pins
897 25 RFEN 1 refersh enabled
904 /* need to use this else DSP code crashes */
905 hpi_write_word(pdo, 0x01800018, 0x47117000);
907 /* EMIF SDRAM Refresh Timing */
908 hpi_write_word(pdo, 0x0180001C, 0x00000410);
910 /*MIF CE1 setup - Async peripherals
911 @100MHz bus speed, each cycle is 10ns,
913 27..22 Wr strobe = 3 30ns
917 13..8 Rd strobe = 3 30ns
918 7..4 MTYPE 0010 Async 32bits
924 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
925 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
926 hpi_write_word(pdo, 0x01800004, cE1);
929 /* delay a little to allow SDRAM and DSP to "get going" */
931 for (i = 0; i < 1000; i++)
932 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
934 /* test access to SDRAM */
936 test_addr = 0x80000000;
937 test_data = 0x00000001;
938 /* test each bit in the 32bit word */
939 for (j = 0; j < 32; j++) {
940 hpi_write_word(pdo, test_addr, test_data);
941 data = hpi_read_word(pdo, test_addr);
942 if (data != test_data) {
944 "DSP dram %x %x %x %x\n",
945 test_addr, test_data, data,
948 return HPI6000_ERROR_INIT_SDRAM1;
950 test_data = test_data << 1;
952 /* test every Nth address in the DRAM */
953 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
954 #define DRAM_INC 1024
955 test_addr = 0x80000000;
957 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
958 hpi_write_word(pdo, test_addr + i, test_data);
961 test_addr = 0x80000000;
963 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
964 data = hpi_read_word(pdo, test_addr + i);
965 if (data != test_data) {
967 "DSP dram %x %x %x %x\n",
968 test_addr + i, test_data,
970 return HPI6000_ERROR_INIT_SDRAM2;
977 /* write the DSP code down into the DSPs memory */
978 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
979 dsp_code.ps_dev = pao->pci.p_os_data;
981 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
993 error = hpi_dsp_code_read_word(&dsp_code, &length);
996 if (length == 0xFFFFFFFF)
997 break; /* end of code */
999 error = hpi_dsp_code_read_word(&dsp_code, &address);
1002 error = hpi_dsp_code_read_word(&dsp_code, &type);
1005 error = hpi_dsp_code_read_block(length, &dsp_code,
1009 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
1010 address, pcode, length);
1016 hpi_dsp_code_close(&dsp_code);
1019 /* verify that code was written correctly */
1020 /* this time through, assume no errors in DSP code file/array */
1021 hpi_dsp_code_rewind(&dsp_code);
1028 hpi_dsp_code_read_word(&dsp_code, &length);
1029 if (length == 0xFFFFFFFF)
1030 break; /* end of code */
1032 hpi_dsp_code_read_word(&dsp_code, &address);
1033 hpi_dsp_code_read_word(&dsp_code, &type);
1034 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1036 for (i = 0; i < length; i++) {
1037 data = hpi_read_word(pdo, address);
1038 if (data != *pcode) {
1039 error = HPI6000_ERROR_INIT_VERIFY;
1040 HPI_DEBUG_LOG(ERROR,
1041 "DSP verify %x %x %x %x\n",
1042 address, *pcode, data,
1052 hpi_dsp_code_close(&dsp_code);
1056 /* zero out the hostmailbox */
1058 u32 address = HPI_HIF_ADDR(host_cmd);
1059 for (i = 0; i < 4; i++) {
1060 hpi_write_word(pdo, address, 0);
1064 /* write the DSP number into the hostmailbox */
1065 /* structure before starting the DSP */
1066 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1068 /* write the DSP adapter Info into the */
1069 /* hostmailbox before starting the DSP */
1071 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1074 /* step 3. Start code by sending interrupt */
1075 iowrite32(0x00030003, pdo->prHPI_control);
1076 for (i = 0; i < 10000; i++)
1077 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
1079 /* wait for a non-zero value in hostcmd -
1080 * indicating initialization is complete
1082 * Init could take a while if DSP checks SDRAM memory
1083 * Was 200000. Increased to 2000000 for ASI8801 so we
1084 * don't get 938 errors.
1089 read = hpi_read_word(pdo,
1090 HPI_HIF_ADDR(host_cmd));
1092 && hpi6000_check_PCI2040_error_flag(pao,
1097 /* The following is a workaround for bug #94:
1098 * Bluescreen on install and subsequent boots on a
1099 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1100 * ServerWorks chipset. Without this delay the system
1101 * locks up with a bluescreen (NOT GPF or pagefault).
1104 hpios_delay_micro_seconds(1000);
1107 return HPI6000_ERROR_INIT_NOACK;
1109 /* read the DSP adapter Info from the */
1110 /* hostmailbox structure after starting the DSP */
1111 if (dsp_index == 0) {
1112 /*u32 dwTestData=0; */
1117 HPI_HIF_ADDR(adapter_info));
1118 if (HPI_ADAPTER_FAMILY_ASI
1119 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1121 HPI_ADAPTER_FAMILY_ASI(0x6200))
1122 /* all 6200 cards have this many DSPs */
1125 /* test that the PLD is programmed */
1126 /* and we can read/write 24bits */
1127 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1129 switch (boot_load_family) {
1130 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1131 /* ASI6100/6200 has 24bit path to FPGA */
1133 /* ASI5100 uses AX6 code, */
1134 /* but has no PLD r/w register to test */
1135 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.
1136 subsys_device_id) ==
1137 HPI_ADAPTER_FAMILY_ASI(0x5100))
1140 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1141 /* ASI8800 has 16bit path to FPGA */
1145 test_data = 0xAAAAAA00L & mask;
1146 /* write to 24 bit Debug register (D31-D8) */
1147 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1148 read = hpi_read_word(pdo,
1149 PLD_BASE_ADDRESS + 4L) & mask;
1150 if (read != test_data) {
1151 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1153 return HPI6000_ERROR_INIT_PLDTEST1;
1155 test_data = 0x55555500L & mask;
1156 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1157 read = hpi_read_word(pdo,
1158 PLD_BASE_ADDRESS + 4L) & mask;
1159 if (read != test_data) {
1160 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1162 return HPI6000_ERROR_INIT_PLDTEST2;
1169 #define PCI_TIMEOUT 100
1171 static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1173 u32 timeout = PCI_TIMEOUT;
1176 iowrite32(address, pdo->prHPI_address);
1177 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1187 /* write one word to the HPI port */
1188 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1190 if (hpi_set_address(pdo, address))
1192 iowrite32(data, pdo->prHPI_data);
1195 /* read one word from the HPI port */
1196 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1200 if (hpi_set_address(pdo, address))
1201 return 0; /*? no way to return error */
1203 /* take care of errata in revB DSP (2.0.1) */
1204 data = ioread32(pdo->prHPI_data);
1208 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1209 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1212 u16 length16 = length - 1;
1217 if (hpi_set_address(pdo, address))
1220 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1222 /* take care of errata in revB DSP (2.0.1) */
1223 /* must end with non auto-inc */
1224 iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1227 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1229 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1232 u16 length16 = length - 1;
1237 if (hpi_set_address(pdo, address))
1240 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1242 /* take care of errata in revB DSP (2.0.1) */
1243 /* must end with non auto-inc */
1244 *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1247 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1248 u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1250 struct dsp_obj *pdo =
1251 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1252 u32 time_out = PCI_TIMEOUT;
1253 int c6711_burst_size = 128;
1254 u32 local_hpi_address = hpi_address;
1255 int local_count = count;
1257 u32 *pdata = source;
1259 while (local_count) {
1260 if (local_count > c6711_burst_size)
1261 xfer_size = c6711_burst_size;
1263 xfer_size = local_count;
1265 time_out = PCI_TIMEOUT;
1267 hpi_write_block(pdo, local_hpi_address, pdata,
1269 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1275 local_hpi_address += sizeof(u32) * xfer_size;
1276 local_count -= xfer_size;
1285 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1286 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1288 struct dsp_obj *pdo =
1289 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1290 u32 time_out = PCI_TIMEOUT;
1291 int c6711_burst_size = 16;
1292 u32 local_hpi_address = hpi_address;
1293 int local_count = count;
1298 while (local_count) {
1299 if (local_count > c6711_burst_size)
1300 xfer_size = c6711_burst_size;
1302 xfer_size = local_count;
1304 time_out = PCI_TIMEOUT;
1306 hpi_read_block(pdo, local_hpi_address, pdata,
1308 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1314 local_hpi_address += sizeof(u32) * xfer_size;
1315 local_count -= xfer_size;
1325 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1326 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1328 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1329 struct dsp_obj *pdo = &phw->ado[dsp_index];
1337 /* does the DSP we are referencing exist? */
1338 if (dsp_index >= phw->num_dsp)
1339 return HPI6000_ERROR_MSG_INVALID_DSP_INDEX;
1341 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1342 if (ack & HPI_HIF_ERROR_MASK) {
1344 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1346 pao->dsp_crashed = 0;
1348 /* send the message */
1350 /* get the address and size */
1351 if (phw->message_buffer_address_on_dsp == 0) {
1356 HPI_HIF_ADDR(message_buffer_address));
1357 phw->message_buffer_address_on_dsp = address;
1358 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1361 return HPI6000_ERROR_MSG_GET_ADR;
1363 address = phw->message_buffer_address_on_dsp;
1365 /* dwLength = sizeof(struct hpi_message); */
1369 p_data = (u32 *)phm;
1370 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1372 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1374 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1375 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1376 hpi6000_send_dsp_interrupt(pdo);
1378 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1379 if (ack & HPI_HIF_ERROR_MASK)
1380 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1382 /* get the address and size */
1383 if (phw->response_buffer_address_on_dsp == 0) {
1388 HPI_HIF_ADDR(response_buffer_address));
1389 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1391 phw->response_buffer_address_on_dsp = address;
1394 return HPI6000_ERROR_RESP_GET_ADR;
1396 address = phw->response_buffer_address_on_dsp;
1398 /* read the length of the response back from the DSP */
1401 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1402 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1404 length = sizeof(struct hpi_response);
1407 p_data = (u32 *)phr;
1408 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1410 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1412 /* set i/f back to idle */
1413 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1414 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1415 hpi6000_send_dsp_interrupt(pdo);
1417 error = hpi_validate_response(phm, phr);
1421 /* have to set up the below defines to match stuff in the MAP file */
1423 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1424 #define MSG_LENGTH 11
1425 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1426 #define RESP_LENGTH 16
1427 #define QUEUE_START (HPI_HIF_BASE+0x88)
1428 #define QUEUE_SIZE 0x8000
1430 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1432 /*#define CHECKING // comment this line in to enable checking */
1434 if (address < (u32)MSG_ADDRESS)
1436 if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1438 if ((address + (length_in_dwords << 2)) >
1439 (u32)(QUEUE_START + QUEUE_SIZE))
1443 (void)length_in_dwords;
1448 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1449 struct hpi_message *phm, struct hpi_response *phr)
1451 struct dsp_obj *pdo =
1452 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1455 u32 length, address;
1456 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1461 /* round dwDataSize down to nearest 4 bytes */
1462 while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1464 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1465 if (ack & HPI_HIF_ERROR_MASK)
1466 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1468 if (hpi6000_send_host_command(pao, dsp_index,
1470 return HPI6000_ERROR_SEND_DATA_CMD;
1472 hpi6000_send_dsp_interrupt(pdo);
1474 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1476 if (ack & HPI_HIF_ERROR_MASK)
1477 return HPI6000_ERROR_SEND_DATA_ACK;
1480 /* get the address and size */
1481 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1482 /* DSP returns number of DWORDS */
1483 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1484 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1486 if (!hpi6000_send_data_check_adr(address, length))
1487 return HPI6000_ERROR_SEND_DATA_ADR;
1489 /* send the data. break data into 512 DWORD blocks (2K bytes)
1490 * and send using block write. 2Kbytes is the max as this is the
1491 * memory window given to the HPI data register by the PCI2040
1500 if (hpi6000_dsp_block_write32(pao, dsp_index,
1501 address, p_data, blk_len))
1502 return HPI6000_ERROR_SEND_DATA_WRITE;
1503 address += blk_len * 4;
1509 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1510 return HPI6000_ERROR_SEND_DATA_IDLECMD;
1512 hpi6000_send_dsp_interrupt(pdo);
1514 data_sent += length * 4;
1517 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1521 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1522 struct hpi_message *phm, struct hpi_response *phr)
1524 struct dsp_obj *pdo =
1525 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1528 u32 length, address;
1529 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1531 (void)phr; /* this parameter not used! */
1533 /* round dwDataSize down to nearest 4 bytes */
1534 while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1535 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1536 if (ack & HPI_HIF_ERROR_MASK)
1537 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1539 if (hpi6000_send_host_command(pao, dsp_index,
1541 return HPI6000_ERROR_GET_DATA_CMD;
1542 hpi6000_send_dsp_interrupt(pdo);
1544 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1546 if (ack & HPI_HIF_ERROR_MASK)
1547 return HPI6000_ERROR_GET_DATA_ACK;
1549 /* get the address and size */
1551 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1552 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1553 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1562 if (hpi6000_dsp_block_read32(pao, dsp_index,
1563 address, p_data, blk_len))
1564 return HPI6000_ERROR_GET_DATA_READ;
1565 address += blk_len * 4;
1571 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1572 return HPI6000_ERROR_GET_DATA_IDLECMD;
1573 hpi6000_send_dsp_interrupt(pdo);
1575 data_got += length * 4;
1580 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1582 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
1585 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1586 u16 dsp_index, u32 host_cmd)
1588 struct dsp_obj *pdo =
1589 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1590 u32 timeout = TIMEOUT;
1594 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1595 /* flush the FIFO */
1596 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1597 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1599 /* reset the interrupt bit */
1600 iowrite32(0x00040004, pdo->prHPI_control);
1608 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1609 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1614 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1616 /* read the error bits from the PCI2040 */
1617 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1619 /* reset the error flag */
1620 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1621 phw->pCI2040HPI_error_count++;
1622 if (read_or_write == 1)
1623 gw_pci_read_asserts++; /************* inc global */
1625 gw_pci_write_asserts++;
1631 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1634 struct dsp_obj *pdo =
1635 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1640 /* wait for host interrupt to signal ack is ready */
1643 hPIC = ioread32(pdo->prHPI_control);
1644 if (hPIC & 0x04) /* 0x04 = HINT from DSP */
1648 return HPI_HIF_ERROR_MASK;
1650 /* wait for dwAckValue */
1653 /* read the ack mailbox */
1654 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1655 if (ack == ack_value)
1657 if ((ack & HPI_HIF_ERROR_MASK)
1658 && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1660 /*for (i=0;i<1000;i++) */
1663 if (ack & HPI_HIF_ERROR_MASK)
1664 /* indicates bad read from DSP -
1665 typically 0xffffff is read for some reason */
1666 ack = HPI_HIF_ERROR_MASK;
1669 ack = HPI_HIF_ERROR_MASK;
1673 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1674 struct hpi_message *phm)
1676 const u16 dsp_index = 0;
1677 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1678 struct dsp_obj *pdo = &phw->ado[dsp_index];
1680 u32 cache_dirty_flag;
1683 hpios_dsplock_lock(pao);
1688 hpi_read_word((struct dsp_obj *)pdo,
1689 HPI_HIF_ADDR(control_cache_is_dirty));
1690 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1692 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1696 if (cache_dirty_flag) {
1697 /* read the cached controls */
1702 if (pdo->control_cache_address_on_dsp == 0) {
1705 hpi_read_word((struct dsp_obj *)pdo,
1706 HPI_HIF_ADDR(control_cache_address));
1708 length = hpi_read_word((struct dsp_obj *)pdo,
1710 (control_cache_size_in_bytes));
1711 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1714 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1717 pdo->control_cache_address_on_dsp = address;
1718 pdo->control_cache_length_on_dsp = length;
1720 address = pdo->control_cache_address_on_dsp;
1721 length = pdo->control_cache_length_on_dsp;
1724 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1725 (u32 *)&phw->control_cache[0],
1726 length / sizeof(u32))) {
1727 err = HPI6000_ERROR_CONTROL_CACHE_READ;
1731 hpi_write_word((struct dsp_obj *)pdo,
1732 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1733 /* flush the FIFO */
1734 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1735 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1738 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1746 hpios_dsplock_unlock(pao);
1750 /** Get dsp index for multi DSP adapters only */
1751 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1754 switch (phm->object) {
1755 case HPI_OBJ_ISTREAM:
1756 if (phm->obj_index < 2)
1759 case HPI_OBJ_PROFILE:
1760 ret = phm->obj_index;
1768 /** Complete transaction with DSP
1770 Send message, get response, send or get stream data if any.
1772 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1773 struct hpi_response *phr)
1777 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
1778 hpios_dsplock_lock(pao);
1783 dsp_index = get_dsp_index(pao, phm);
1785 /* is this checked on the DSP anyway? */
1786 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1787 || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1788 struct hpi_message hm;
1790 hm.obj_index = phm->u.d.u.stream.stream_index;
1791 hm.object = phm->u.d.u.stream.object_type;
1792 add_index = get_dsp_index(pao, &hm);
1793 if (add_index != dsp_index) {
1794 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1799 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1801 /* maybe an error response */
1803 /* something failed in the HPI/DSP interface */
1805 /* just the header of the response is valid */
1806 phr->size = sizeof(struct hpi_response_header);
1810 if (phr->error != 0) /* something failed in the DSP */
1813 switch (phm->function) {
1814 case HPI_OSTREAM_WRITE:
1815 case HPI_ISTREAM_ANC_WRITE:
1816 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1818 case HPI_ISTREAM_READ:
1819 case HPI_OSTREAM_ANC_READ:
1820 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1822 case HPI_ADAPTER_GET_ASSERT:
1823 phr->u.a.adapter_index = 0; /* dsp 0 default */
1825 if (!phr->u.a.adapter_type) {
1826 /* no assert from dsp 0, check dsp 1 */
1827 error = hpi6000_message_response_sequence(pao,
1829 phr->u.a.adapter_index = 1;
1838 hpios_dsplock_unlock(pao);