sound/pci/asihpi/hpi6000.c

   1 /******************************************************************************
   2
   3     AudioScience HPI driver
   4     Copyright (C) 1997-2010  AudioScience Inc. <support@audioscience.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of version 2 of the GNU General Public License as
   8     published by the Free Software Foundation;
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18
  19  Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
  20  These PCI bus adapters are based on the TI C6711 DSP.
  21
  22  Exported functions:
  23  void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
  24
  25  #defines
  26  HIDE_PCI_ASSERTS to show the PCI asserts
  27  PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
  28
  29 (C) Copyright AudioScience Inc. 1998-2003
  30 *******************************************************************************/
  31 #define SOURCEFILE_NAME "hpi6000.c"
  32
  33 #include "hpi_internal.h"
  34 #include "hpimsginit.h"
  35 #include "hpidebug.h"
  36 #include "hpi6000.h"
  37 #include "hpidspcd.h"
  38 #include "hpicmn.h"
  39
  40 #define HPI_HIF_BASE (0x00000200)       /* start of C67xx internal RAM */
  41 #define HPI_HIF_ADDR(member) \
  42         (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
  43 #define HPI_HIF_ERROR_MASK      0x4000
  44
  45 /* HPI6000 specific error codes */
  46 #define HPI6000_ERROR_BASE 900  /* not actually used anywhere */
  47
  48 /* operational/messaging errors */
  49 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT             901
  50
  51 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK             903
  52 #define HPI6000_ERROR_MSG_GET_ADR                       904
  53 #define HPI6000_ERROR_RESP_GET_ADR                      905
  54 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32             906
  55 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32              907
  56
  57 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS              909
  58
  59 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT            911
  60 #define HPI6000_ERROR_SEND_DATA_ACK                     912
  61 #define HPI6000_ERROR_SEND_DATA_ADR                     913
  62 #define HPI6000_ERROR_SEND_DATA_TIMEOUT                 914
  63 #define HPI6000_ERROR_SEND_DATA_CMD                     915
  64 #define HPI6000_ERROR_SEND_DATA_WRITE                   916
  65 #define HPI6000_ERROR_SEND_DATA_IDLECMD                 917
  66
  67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT             921
  68 #define HPI6000_ERROR_GET_DATA_ACK                      922
  69 #define HPI6000_ERROR_GET_DATA_CMD                      923
  70 #define HPI6000_ERROR_GET_DATA_READ                     924
  71 #define HPI6000_ERROR_GET_DATA_IDLECMD                  925
  72
  73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN             951
  74 #define HPI6000_ERROR_CONTROL_CACHE_READ                952
  75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH               953
  76
  77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD               961
  78 #define HPI6000_ERROR_MSG_RESP_IDLECMD                  962
  79
  80 /* Initialisation/bootload errors */
  81 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID               930
  82
  83 /* can't access PCI2040 */
  84 #define HPI6000_ERROR_INIT_PCI2040                      931
  85 /* can't access DSP HPI i/f */
  86 #define HPI6000_ERROR_INIT_DSPHPI                       932
  87 /* can't access internal DSP memory */
  88 #define HPI6000_ERROR_INIT_DSPINTMEM                    933
  89 /* can't access SDRAM - test#1 */
  90 #define HPI6000_ERROR_INIT_SDRAM1                       934
  91 /* can't access SDRAM - test#2 */
  92 #define HPI6000_ERROR_INIT_SDRAM2                       935
  93
  94 #define HPI6000_ERROR_INIT_VERIFY                       938
  95
  96 #define HPI6000_ERROR_INIT_NOACK                        939
  97
  98 #define HPI6000_ERROR_INIT_PLDTEST1                     941
  99 #define HPI6000_ERROR_INIT_PLDTEST2                     942
 100
 101 /* local defines */
 102
 103 #define HIDE_PCI_ASSERTS
 104 #define PROFILE_DSP2
 105
 106 /* for PCI2040 i/f chip */
 107 /* HPI CSR registers */
 108 /* word offsets from CSR base */
 109 /* use when io addresses defined as u32 * */
 110
 111 #define INTERRUPT_EVENT_SET     0
 112 #define INTERRUPT_EVENT_CLEAR   1
 113 #define INTERRUPT_MASK_SET      2
 114 #define INTERRUPT_MASK_CLEAR    3
 115 #define HPI_ERROR_REPORT        4
 116 #define HPI_RESET               5
 117 #define HPI_DATA_WIDTH          6
 118
 119 #define MAX_DSPS 2
 120 /* HPI registers, spaced 8K bytes = 2K words apart */
 121 #define DSP_SPACING             0x800
 122
 123 #define CONTROL                 0x0000
 124 #define ADDRESS                 0x0200
 125 #define DATA_AUTOINC            0x0400
 126 #define DATA                    0x0600
 127
 128 #define TIMEOUT 500000
 129
 130 struct dsp_obj {
 131         __iomem u32 *prHPI_control;
 132         __iomem u32 *prHPI_address;
 133         __iomem u32 *prHPI_data;
 134         __iomem u32 *prHPI_data_auto_inc;
 135         char c_dsp_rev;         /*A, B */
 136         u32 control_cache_address_on_dsp;
 137         u32 control_cache_length_on_dsp;
 138         struct hpi_adapter_obj *pa_parent_adapter;
 139 };
 140
 141 struct hpi_hw_obj {
 142         __iomem u32 *dw2040_HPICSR;
 143         __iomem u32 *dw2040_HPIDSP;
 144
 145         u16 num_dsp;
 146         struct dsp_obj ado[MAX_DSPS];
 147
 148         u32 message_buffer_address_on_dsp;
 149         u32 response_buffer_address_on_dsp;
 150         u32 pCI2040HPI_error_count;
 151
 152         struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
 153         struct hpi_control_cache *p_cache;
 154 };
 155
 156 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
 157         u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
 158 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
 159         u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
 160
 161 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
 162         u32 *pos_error_code);
 163 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
 164         u16 read_or_write);
 165 #define H6READ 1
 166 #define H6WRITE 0
 167
 168 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
 169         struct hpi_message *phm);
 170 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
 171         u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
 172
 173 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
 174         struct hpi_response *phr);
 175
 176 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
 177         u32 ack_value);
 178
 179 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
 180         u16 dsp_index, u32 host_cmd);
 181
 182 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
 183
 184 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
 185         struct hpi_message *phm, struct hpi_response *phr);
 186
 187 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
 188         struct hpi_message *phm, struct hpi_response *phr);
 189
 190 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
 191
 192 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
 193
 194 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
 195         u32 length);
 196
 197 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
 198         u32 length);
 199
 200 static void subsys_create_adapter(struct hpi_message *phm,
 201         struct hpi_response *phr);
 202
 203 static void subsys_delete_adapter(struct hpi_message *phm,
 204         struct hpi_response *phr);
 205
 206 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
 207         struct hpi_message *phm, struct hpi_response *phr);
 208
 209 static short create_adapter_obj(struct hpi_adapter_obj *pao,
 210         u32 *pos_error_code);
 211
 212 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
 213
 214 /* local globals */
 215
 216 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
 217 static u16 gw_pci_write_asserts;        /* used to count PCI2040 errors */
 218
 219 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
 220 {
 221         switch (phm->function) {
 222         case HPI_SUBSYS_CREATE_ADAPTER:
 223                 subsys_create_adapter(phm, phr);
 224                 break;
 225         case HPI_SUBSYS_DELETE_ADAPTER:
 226                 subsys_delete_adapter(phm, phr);
 227                 break;
 228         default:
 229                 phr->error = HPI_ERROR_INVALID_FUNC;
 230                 break;
 231         }
 232 }
 233
 234 static void control_message(struct hpi_adapter_obj *pao,
 235         struct hpi_message *phm, struct hpi_response *phr)
 236 {
 237         switch (phm->function) {
 238         case HPI_CONTROL_GET_STATE:
 239                 if (pao->has_control_cache) {
 240                         u16 err;
 241                         err = hpi6000_update_control_cache(pao, phm);
 242
 243                         if (err) {
 244                                 if (err >= HPI_ERROR_BACKEND_BASE) {
 245                                         phr->error =
 246                                                 HPI_ERROR_CONTROL_CACHING;
 247                                         phr->specific_error = err;
 248                                 } else {
 249                                         phr->error = err;
 250                                 }
 251                                 break;
 252                         }
 253
 254                         if (hpi_check_control_cache(((struct hpi_hw_obj *)
 255                                                 pao->priv)->p_cache, phm,
 256                                         phr))
 257                                 break;
 258                 }
 259                 hw_message(pao, phm, phr);
 260                 break;
 261         case HPI_CONTROL_SET_STATE:
 262                 hw_message(pao, phm, phr);
 263                 hpi_cmn_control_cache_sync_to_msg(((struct hpi_hw_obj *)pao->
 264                                 priv)->p_cache, phm, phr);
 265                 break;
 266
 267         case HPI_CONTROL_GET_INFO:
 268         default:
 269                 hw_message(pao, phm, phr);
 270                 break;
 271         }
 272 }
 273
 274 static void adapter_message(struct hpi_adapter_obj *pao,
 275         struct hpi_message *phm, struct hpi_response *phr)
 276 {
 277         switch (phm->function) {
 278         case HPI_ADAPTER_GET_ASSERT:
 279                 adapter_get_asserts(pao, phm, phr);
 280                 break;
 281
 282         default:
 283                 hw_message(pao, phm, phr);
 284                 break;
 285         }
 286 }
 287
 288 static void outstream_message(struct hpi_adapter_obj *pao,
 289         struct hpi_message *phm, struct hpi_response *phr)
 290 {
 291         switch (phm->function) {
 292         case HPI_OSTREAM_HOSTBUFFER_ALLOC:
 293         case HPI_OSTREAM_HOSTBUFFER_FREE:
 294                 /* Don't let these messages go to the HW function because
 295                  * they're called without locking the spinlock.
 296                  * For the HPI6000 adapters the HW would return
 297                  * HPI_ERROR_INVALID_FUNC anyway.
 298                  */
 299                 phr->error = HPI_ERROR_INVALID_FUNC;
 300                 break;
 301         default:
 302                 hw_message(pao, phm, phr);
 303                 return;
 304         }
 305 }
 306
 307 static void instream_message(struct hpi_adapter_obj *pao,
 308         struct hpi_message *phm, struct hpi_response *phr)
 309 {
 310
 311         switch (phm->function) {
 312         case HPI_ISTREAM_HOSTBUFFER_ALLOC:
 313         case HPI_ISTREAM_HOSTBUFFER_FREE:
 314                 /* Don't let these messages go to the HW function because
 315                  * they're called without locking the spinlock.
 316                  * For the HPI6000 adapters the HW would return
 317                  * HPI_ERROR_INVALID_FUNC anyway.
 318                  */
 319                 phr->error = HPI_ERROR_INVALID_FUNC;
 320                 break;
 321         default:
 322                 hw_message(pao, phm, phr);
 323                 return;
 324         }
 325 }
 326
 327 /************************************************************************/
 328 /** HPI_6000()
 329  * Entry point from HPIMAN
 330  * All calls to the HPI start here
 331  */
 332 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
 333 {
 334         struct hpi_adapter_obj *pao = NULL;
 335
 336         /* subsytem messages get executed by every HPI. */
 337         /* All other messages are ignored unless the adapter index matches */
 338         /* an adapter in the HPI */
 339         /*HPI_DEBUG_LOG(DEBUG, "O %d,F %x\n", phm->wObject, phm->wFunction); */
 340
 341         /* if Dsp has crashed then do not communicate with it any more */
 342         if (phm->object != HPI_OBJ_SUBSYSTEM) {
 343                 pao = hpi_find_adapter(phm->adapter_index);
 344                 if (!pao) {
 345                         HPI_DEBUG_LOG(DEBUG,
 346                                 " %d,%d refused, for another HPI?\n",
 347                                 phm->object, phm->function);
 348                         return;
 349                 }
 350
 351                 if (pao->dsp_crashed >= 10) {
 352                         hpi_init_response(phr, phm->object, phm->function,
 353                                 HPI_ERROR_DSP_HARDWARE);
 354                         HPI_DEBUG_LOG(DEBUG, " %d,%d dsp crashed.\n",
 355                                 phm->object, phm->function);
 356                         return;
 357                 }
 358         }
 359         /* Init default response including the size field */
 360         if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
 361                 hpi_init_response(phr, phm->object, phm->function,
 362                         HPI_ERROR_PROCESSING_MESSAGE);
 363
 364         switch (phm->type) {
 365         case HPI_TYPE_MESSAGE:
 366                 switch (phm->object) {
 367                 case HPI_OBJ_SUBSYSTEM:
 368                         subsys_message(phm, phr);
 369                         break;
 370
 371                 case HPI_OBJ_ADAPTER:
 372                         phr->size =
 373                                 sizeof(struct hpi_response_header) +
 374                                 sizeof(struct hpi_adapter_res);
 375                         adapter_message(pao, phm, phr);
 376                         break;
 377
 378                 case HPI_OBJ_CONTROL:
 379                         control_message(pao, phm, phr);
 380                         break;
 381
 382                 case HPI_OBJ_OSTREAM:
 383                         outstream_message(pao, phm, phr);
 384                         break;
 385
 386                 case HPI_OBJ_ISTREAM:
 387                         instream_message(pao, phm, phr);
 388                         break;
 389
 390                 default:
 391                         hw_message(pao, phm, phr);
 392                         break;
 393                 }
 394                 break;
 395
 396         default:
 397                 phr->error = HPI_ERROR_INVALID_TYPE;
 398                 break;
 399         }
 400 }
 401
 402 /************************************************************************/
 403 /* SUBSYSTEM */
 404
 405 /* create an adapter object and initialise it based on resource information
 406  * passed in in the message
 407  * NOTE - you cannot use this function AND the FindAdapters function at the
 408  * same time, the application must use only one of them to get the adapters
 409  */
 410 static void subsys_create_adapter(struct hpi_message *phm,
 411         struct hpi_response *phr)
 412 {
 413         /* create temp adapter obj, because we don't know what index yet */
 414         struct hpi_adapter_obj ao;
 415         struct hpi_adapter_obj *pao;
 416         u32 os_error_code;
 417         u16 err = 0;
 418         u32 dsp_index = 0;
 419
 420         HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
 421
 422         memset(&ao, 0, sizeof(ao));
 423
 424         ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
 425         if (!ao.priv) {
 426                 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
 427                 phr->error = HPI_ERROR_MEMORY_ALLOC;
 428                 return;
 429         }
 430
 431         /* create the adapter object based on the resource information */
 432         ao.pci = *phm->u.s.resource.r.pci;
 433
 434         err = create_adapter_obj(&ao, &os_error_code);
 435         if (err) {
 436                 delete_adapter_obj(&ao);
 437                 if (err >= HPI_ERROR_BACKEND_BASE) {
 438                         phr->error = HPI_ERROR_DSP_BOOTLOAD;
 439                         phr->specific_error = err;
 440                 } else {
 441                         phr->error = err;
 442                 }
 443
 444                 phr->u.s.data = os_error_code;
 445                 return;
 446         }
 447         /* need to update paParentAdapter */
 448         pao = hpi_find_adapter(ao.index);
 449         if (!pao) {
 450                 /* We just added this adapter, why can't we find it!? */
 451                 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
 452                 phr->error = HPI_ERROR_BAD_ADAPTER;
 453                 return;
 454         }
 455
 456         for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
 457                 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
 458                 phw->ado[dsp_index].pa_parent_adapter = pao;
 459         }
 460
 461         phr->u.s.adapter_type = ao.adapter_type;
 462         phr->u.s.adapter_index = ao.index;
 463         phr->error = 0;
 464 }
 465
 466 static void subsys_delete_adapter(struct hpi_message *phm,
 467         struct hpi_response *phr)
 468 {
 469         struct hpi_adapter_obj *pao = NULL;
 470
 471         pao = hpi_find_adapter(phm->obj_index);
 472         if (!pao)
 473                 return;
 474
 475         delete_adapter_obj(pao);
 476         hpi_delete_adapter(pao);
 477         phr->error = 0;
 478 }
 479
 480 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
 481 static short create_adapter_obj(struct hpi_adapter_obj *pao,
 482         u32 *pos_error_code)
 483 {
 484         short boot_error = 0;
 485         u32 dsp_index = 0;
 486         u32 control_cache_size = 0;
 487         u32 control_cache_count = 0;
 488         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
 489
 490         /* The PCI2040 has the following address map */
 491         /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
 492         /* BAR1 - 32K = HPI registers on DSP */
 493         phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
 494         phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
 495         HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
 496                 phw->dw2040_HPIDSP);
 497
 498         /* set addresses for the possible DSP HPI interfaces */
 499         for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
 500                 phw->ado[dsp_index].prHPI_control =
 501                         phw->dw2040_HPIDSP + (CONTROL +
 502                         DSP_SPACING * dsp_index);
 503
 504                 phw->ado[dsp_index].prHPI_address =
 505                         phw->dw2040_HPIDSP + (ADDRESS +
 506                         DSP_SPACING * dsp_index);
 507                 phw->ado[dsp_index].prHPI_data =
 508                         phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
 509
 510                 phw->ado[dsp_index].prHPI_data_auto_inc =
 511                         phw->dw2040_HPIDSP + (DATA_AUTOINC +
 512                         DSP_SPACING * dsp_index);
 513
 514                 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
 515                         phw->ado[dsp_index].prHPI_control,
 516                         phw->ado[dsp_index].prHPI_address,
 517                         phw->ado[dsp_index].prHPI_data,
 518                         phw->ado[dsp_index].prHPI_data_auto_inc);
 519
 520                 phw->ado[dsp_index].pa_parent_adapter = pao;
 521         }
 522
 523         phw->pCI2040HPI_error_count = 0;
 524         pao->has_control_cache = 0;
 525
 526         /* Set the default number of DSPs on this card */
 527         /* This is (conditionally) adjusted after bootloading */
 528         /* of the first DSP in the bootload section. */
 529         phw->num_dsp = 1;
 530
 531         boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
 532         if (boot_error)
 533                 return boot_error;
 534
 535         HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
 536
 537         phw->message_buffer_address_on_dsp = 0L;
 538         phw->response_buffer_address_on_dsp = 0L;
 539
 540         /* get info about the adapter by asking the adapter */
 541         /* send a HPI_ADAPTER_GET_INFO message */
 542         {
 543                 struct hpi_message hm;
 544                 struct hpi_response hr0;        /* response from DSP 0 */
 545                 struct hpi_response hr1;        /* response from DSP 1 */
 546                 u16 error = 0;
 547
 548                 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
 549                 memset(&hm, 0, sizeof(hm));
 550                 hm.type = HPI_TYPE_MESSAGE;
 551                 hm.size = sizeof(struct hpi_message);
 552                 hm.object = HPI_OBJ_ADAPTER;
 553                 hm.function = HPI_ADAPTER_GET_INFO;
 554                 hm.adapter_index = 0;
 555                 memset(&hr0, 0, sizeof(hr0));
 556                 memset(&hr1, 0, sizeof(hr1));
 557                 hr0.size = sizeof(hr0);
 558                 hr1.size = sizeof(hr1);
 559
 560                 error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
 561                 if (hr0.error) {
 562                         HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
 563                         return hr0.error;
 564                 }
 565                 if (phw->num_dsp == 2) {
 566                         error = hpi6000_message_response_sequence(pao, 1, &hm,
 567                                 &hr1);
 568                         if (error)
 569                                 return error;
 570                 }
 571                 pao->adapter_type = hr0.u.ax.info.adapter_type;
 572                 pao->index = hr0.u.ax.info.adapter_index;
 573         }
 574
 575         memset(&phw->control_cache[0], 0,
 576                 sizeof(struct hpi_control_cache_single) *
 577                 HPI_NMIXER_CONTROLS);
 578         /* Read the control cache length to figure out if it is turned on */
 579         control_cache_size =
 580                 hpi_read_word(&phw->ado[0],
 581                 HPI_HIF_ADDR(control_cache_size_in_bytes));
 582         if (control_cache_size) {
 583                 control_cache_count =
 584                         hpi_read_word(&phw->ado[0],
 585                         HPI_HIF_ADDR(control_cache_count));
 586
 587                 phw->p_cache =
 588                         hpi_alloc_control_cache(control_cache_count,
 589                         control_cache_size, (unsigned char *)
 590                         &phw->control_cache[0]
 591                         );
 592                 if (phw->p_cache)
 593                         pao->has_control_cache = 1;
 594         }
 595
 596         HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
 597                 pao->adapter_type, pao->index);
 598         pao->open = 0;  /* upon creation the adapter is closed */
 599
 600         if (phw->p_cache)
 601                 phw->p_cache->adap_idx = pao->index;
 602
 603         return hpi_add_adapter(pao);
 604 }
 605
 606 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
 607 {
 608         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
 609
 610         if (pao->has_control_cache)
 611                 hpi_free_control_cache(phw->p_cache);
 612
 613         /* reset DSPs on adapter */
 614         iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
 615
 616         kfree(phw);
 617 }
 618
 619 /************************************************************************/
 620 /* ADAPTER */
 621
 622 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
 623         struct hpi_message *phm, struct hpi_response *phr)
 624 {
 625 #ifndef HIDE_PCI_ASSERTS
 626         /* if we have PCI2040 asserts then collect them */
 627         if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
 628                 phr->u.ax.assert.p1 =
 629                         gw_pci_read_asserts * 100 + gw_pci_write_asserts;
 630                 phr->u.ax.assert.p2 = 0;
 631                 phr->u.ax.assert.count = 1;     /* assert count */
 632                 phr->u.ax.assert.dsp_index = -1;        /* "dsp index" */
 633                 strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
 634                 phr->u.ax.assert.dsp_msg_addr = 0;
 635                 gw_pci_read_asserts = 0;
 636                 gw_pci_write_asserts = 0;
 637                 phr->error = 0;
 638         } else
 639 #endif
 640                 hw_message(pao, phm, phr);      /*get DSP asserts */
 641
 642         return;
 643 }
 644
 645 /************************************************************************/
 646 /* LOW-LEVEL */
 647
 648 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
 649         u32 *pos_error_code)
 650 {
 651         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
 652         short error;
 653         u32 timeout;
 654         u32 read = 0;
 655         u32 i = 0;
 656         u32 data = 0;
 657         u32 j = 0;
 658         u32 test_addr = 0x80000000;
 659         u32 test_data = 0x00000001;
 660         u32 dw2040_reset = 0;
 661         u32 dsp_index = 0;
 662         u32 endian = 0;
 663         u32 adapter_info = 0;
 664         u32 delay = 0;
 665
 666         struct dsp_code dsp_code;
 667         u16 boot_load_family = 0;
 668
 669         /* NOTE don't use wAdapterType in this routine. It is not setup yet */
 670
 671         switch (pao->pci.pci_dev->subsystem_device) {
 672         case 0x5100:
 673         case 0x5110:    /* ASI5100 revB or higher with C6711D */
 674         case 0x5200:    /* ASI5200 PCIe version of ASI5100 */
 675         case 0x6100:
 676         case 0x6200:
 677                 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
 678                 break;
 679         default:
 680                 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
 681         }
 682
 683         /* reset all DSPs, indicate two DSPs are present
 684          * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
 685          */
 686         endian = 0;
 687         dw2040_reset = 0x0003000F;
 688         iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
 689
 690         /* read back register to make sure PCI2040 chip is functioning
 691          * note that bits 4..15 are read-only and so should always return zero,
 692          * even though we wrote 1 to them
 693          */
 694         hpios_delay_micro_seconds(1000);
 695         delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
 696
 697         if (delay != dw2040_reset) {
 698                 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
 699                         delay);
 700                 return HPI6000_ERROR_INIT_PCI2040;
 701         }
 702
 703         /* Indicate that DSP#0,1 is a C6X */
 704         iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
 705         /* set Bit30 and 29 - which will prevent Target aborts from being
 706          * issued upon HPI or GP error
 707          */
 708         iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
 709
 710         /* isolate DSP HAD8 line from PCI2040 so that
 711          * Little endian can be set by pullup
 712          */
 713         dw2040_reset = dw2040_reset & (~(endian << 3));
 714         iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
 715
 716         phw->ado[0].c_dsp_rev = 'B';    /* revB */
 717         phw->ado[1].c_dsp_rev = 'B';    /* revB */
 718
 719         /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
 720         dw2040_reset = dw2040_reset & (~0x00000001);    /* start DSP 0 */
 721         iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
 722         dw2040_reset = dw2040_reset & (~0x00000002);    /* start DSP 1 */
 723         iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
 724
 725         /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
 726         dw2040_reset = dw2040_reset & (~0x00000008);
 727         iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
 728         /*delay to allow DSP to get going */
 729         hpios_delay_micro_seconds(100);
 730
 731         /* loop through all DSPs, downloading DSP code */
 732         for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
 733                 struct dsp_obj *pdo = &phw->ado[dsp_index];
 734
 735                 /* configure DSP so that we download code into the SRAM */
 736                 /* set control reg for little endian, HWOB=1 */
 737                 iowrite32(0x00010001, pdo->prHPI_control);
 738
 739                 /* test access to the HPI address register (HPIA) */
 740                 test_data = 0x00000001;
 741                 for (j = 0; j < 32; j++) {
 742                         iowrite32(test_data, pdo->prHPI_address);
 743                         data = ioread32(pdo->prHPI_address);
 744                         if (data != test_data) {
 745                                 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
 746                                         test_data, data, dsp_index);
 747                                 return HPI6000_ERROR_INIT_DSPHPI;
 748                         }
 749                         test_data = test_data << 1;
 750                 }
 751
 752 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
 753 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
 754 * we're going to do this unconditionally
 755 */
 756 /* PLLDIV1 should have a value of 8000 after reset */
 757 /*
 758         if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
 759 */
 760                 {
 761                         /* C6713 datasheet says we cannot program PLL from HPI,
 762                          * and indeed if we try to set the PLL multiply from the
 763                          * HPI, the PLL does not seem to lock,
 764                          * so we enable the PLL and use the default of x 7
 765                          */
 766                         /* bypass PLL */
 767                         hpi_write_word(pdo, 0x01B7C100, 0x0000);
 768                         hpios_delay_micro_seconds(100);
 769
 770                         /*  ** use default of PLL  x7 ** */
 771                         /* EMIF = 225/3=75MHz */
 772                         hpi_write_word(pdo, 0x01B7C120, 0x8002);
 773                         hpios_delay_micro_seconds(100);
 774
 775                         /* peri = 225/2 */
 776                         hpi_write_word(pdo, 0x01B7C11C, 0x8001);
 777                         hpios_delay_micro_seconds(100);
 778
 779                         /* cpu  = 225/1 */
 780                         hpi_write_word(pdo, 0x01B7C118, 0x8000);
 781
 782                         /* ~2ms delay */
 783                         hpios_delay_micro_seconds(2000);
 784
 785                         /* PLL not bypassed */
 786                         hpi_write_word(pdo, 0x01B7C100, 0x0001);
 787                         /* ~2ms delay */
 788                         hpios_delay_micro_seconds(2000);
 789                 }
 790
 791                 /* test r/w to internal DSP memory
 792                  * C6711 has L2 cache mapped to 0x0 when reset
 793                  *
 794                  *  revB - because of bug 3.0.1 last HPI read
 795                  * (before HPI address issued) must be non-autoinc
 796                  */
 797                 /* test each bit in the 32bit word */
 798                 for (i = 0; i < 100; i++) {
 799                         test_addr = 0x00000000;
 800                         test_data = 0x00000001;
 801                         for (j = 0; j < 32; j++) {
 802                                 hpi_write_word(pdo, test_addr + i, test_data);
 803                                 data = hpi_read_word(pdo, test_addr + i);
 804                                 if (data != test_data) {
 805                                         HPI_DEBUG_LOG(ERROR,
 806                                                 "DSP mem %x %x %x %x\n",
 807                                                 test_addr + i, test_data,
 808                                                 data, dsp_index);
 809
 810                                         return HPI6000_ERROR_INIT_DSPINTMEM;
 811                                 }
 812                                 test_data = test_data << 1;
 813                         }
 814                 }
 815
 816                 /* memory map of ASI6200
 817                    00000000-0000FFFF    16Kx32 internal program
 818                    01800000-019FFFFF    Internal peripheral
 819                    80000000-807FFFFF    CE0 2Mx32 SDRAM running @ 100MHz
 820                    90000000-9000FFFF    CE1 Async peripherals:
 821
 822                    EMIF config
 823                    ------------
 824                    Global EMIF control
 825                    0 -
 826                    1 -
 827                    2 -
 828                    3 CLK2EN = 1   CLKOUT2 enabled
 829                    4 CLK1EN = 0   CLKOUT1 disabled
 830                    5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
 831                    6 -
 832                    7 NOHOLD = 1   external HOLD disabled
 833                    8 HOLDA = 0    HOLDA output is low
 834                    9 HOLD = 0             HOLD input is low
 835                    10 ARDY = 1    ARDY input is high
 836                    11 BUSREQ = 0   BUSREQ output is low
 837                    12,13 Reserved = 1
 838                  */
 839                 hpi_write_word(pdo, 0x01800000, 0x34A8);
 840
 841                 /* EMIF CE0 setup - 2Mx32 Sync DRAM
 842                    31..28       Wr setup
 843                    27..22       Wr strobe
 844                    21..20       Wr hold
 845                    19..16       Rd setup
 846                    15..14       -
 847                    13..8        Rd strobe
 848                    7..4         MTYPE   0011            Sync DRAM 32bits
 849                    3            Wr hold MSB
 850                    2..0         Rd hold
 851                  */
 852                 hpi_write_word(pdo, 0x01800008, 0x00000030);
 853
 854                 /* EMIF SDRAM Extension
 855                    31-21        0
 856                    20           WR2RD = 0
 857                    19-18        WR2DEAC = 1
 858                    17           WR2WR = 0
 859                    16-15        R2WDQM = 2
 860                    14-12        RD2WR = 4
 861                    11-10        RD2DEAC = 1
 862                    9            RD2RD = 1
 863                    8-7          THZP = 10b
 864                    6-5          TWR  = 2-1 = 01b (tWR = 10ns)
 865                    4            TRRD = 0b = 2 ECLK (tRRD = 14ns)
 866                    3-1          TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
 867                    1            CAS latency = 3 ECLK
 868                    (for Micron 2M32-7 operating at 100Mhz)
 869                  */
 870
 871                 /* need to use this else DSP code crashes */
 872                 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
 873
 874                 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
 875                    31           -               -
 876                    30           SDBSZ   1               4 bank
 877                    29..28       SDRSZ   00              11 row address pins
 878                    27..26       SDCSZ   01              8 column address pins
 879                    25           RFEN    1               refersh enabled
 880                    24           INIT    1               init SDRAM
 881                    23..20       TRCD    0001
 882                    19..16       TRP             0001
 883                    15..12       TRC             0110
 884                    11..0        -               -
 885                  */
 886                 /*      need to use this else DSP code crashes */
 887                 hpi_write_word(pdo, 0x01800018, 0x47117000);
 888
 889                 /* EMIF SDRAM Refresh Timing */
 890                 hpi_write_word(pdo, 0x0180001C, 0x00000410);
 891
 892                 /*MIF CE1 setup - Async peripherals
 893                    @100MHz bus speed, each cycle is 10ns,
 894                    31..28       Wr setup  = 1
 895                    27..22       Wr strobe = 3                   30ns
 896                    21..20       Wr hold = 1
 897                    19..16       Rd setup =1
 898                    15..14       Ta = 2
 899                    13..8        Rd strobe = 3                   30ns
 900                    7..4         MTYPE   0010            Async 32bits
 901                    3            Wr hold MSB =0
 902                    2..0         Rd hold = 1
 903                  */
 904                 {
 905                         u32 cE1 =
 906                                 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
 907                                 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
 908                         hpi_write_word(pdo, 0x01800004, cE1);
 909                 }
 910
 911                 /* delay a little to allow SDRAM and DSP to "get going" */
 912                 hpios_delay_micro_seconds(1000);
 913
 914                 /* test access to SDRAM */
 915                 {
 916                         test_addr = 0x80000000;
 917                         test_data = 0x00000001;
 918                         /* test each bit in the 32bit word */
 919                         for (j = 0; j < 32; j++) {
 920                                 hpi_write_word(pdo, test_addr, test_data);
 921                                 data = hpi_read_word(pdo, test_addr);
 922                                 if (data != test_data) {
 923                                         HPI_DEBUG_LOG(ERROR,
 924                                                 "DSP dram %x %x %x %x\n",
 925                                                 test_addr, test_data, data,
 926                                                 dsp_index);
 927
 928                                         return HPI6000_ERROR_INIT_SDRAM1;
 929                                 }
 930                                 test_data = test_data << 1;
 931                         }
 932                         /* test every Nth address in the DRAM */
 933 #define DRAM_SIZE_WORDS 0x200000        /*2_mx32 */
 934 #define DRAM_INC 1024
 935                         test_addr = 0x80000000;
 936                         test_data = 0x0;
 937                         for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
 938                                 hpi_write_word(pdo, test_addr + i, test_data);
 939                                 test_data++;
 940                         }
 941                         test_addr = 0x80000000;
 942                         test_data = 0x0;
 943                         for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
 944                                 data = hpi_read_word(pdo, test_addr + i);
 945                                 if (data != test_data) {
 946                                         HPI_DEBUG_LOG(ERROR,
 947                                                 "DSP dram %x %x %x %x\n",
 948                                                 test_addr + i, test_data,
 949                                                 data, dsp_index);
 950                                         return HPI6000_ERROR_INIT_SDRAM2;
 951                                 }
 952                                 test_data++;
 953                         }
 954
 955                 }
 956
 957                 /* write the DSP code down into the DSPs memory */
 958                 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
 959                 dsp_code.ps_dev = pao->pci.pci_dev;
 960
 961                 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
 962                         pos_error_code);
 963
 964                 if (error)
 965                         return error;
 966
 967                 while (1) {
 968                         u32 length;
 969                         u32 address;
 970                         u32 type;
 971                         u32 *pcode;
 972
 973                         error = hpi_dsp_code_read_word(&dsp_code, &length);
 974                         if (error)
 975                                 break;
 976                         if (length == 0xFFFFFFFF)
 977                                 break;  /* end of code */
 978
 979                         error = hpi_dsp_code_read_word(&dsp_code, &address);
 980                         if (error)
 981                                 break;
 982                         error = hpi_dsp_code_read_word(&dsp_code, &type);
 983                         if (error)
 984                                 break;
 985                         error = hpi_dsp_code_read_block(length, &dsp_code,
 986                                 &pcode);
 987                         if (error)
 988                                 break;
 989                         error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
 990                                 address, pcode, length);
 991                         if (error)
 992                                 break;
 993                 }
 994
 995                 if (error) {
 996                         hpi_dsp_code_close(&dsp_code);
 997                         return error;
 998                 }
 999                 /* verify that code was written correctly */
1000                 /* this time through, assume no errors in DSP code file/array */
1001                 hpi_dsp_code_rewind(&dsp_code);
1002                 while (1) {
1003                         u32 length;
1004                         u32 address;
1005                         u32 type;
1006                         u32 *pcode;
1007
1008                         hpi_dsp_code_read_word(&dsp_code, &length);
1009                         if (length == 0xFFFFFFFF)
1010                                 break;  /* end of code */
1011
1012                         hpi_dsp_code_read_word(&dsp_code, &address);
1013                         hpi_dsp_code_read_word(&dsp_code, &type);
1014                         hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1015
1016                         for (i = 0; i < length; i++) {
1017                                 data = hpi_read_word(pdo, address);
1018                                 if (data != *pcode) {
1019                                         error = HPI6000_ERROR_INIT_VERIFY;
1020                                         HPI_DEBUG_LOG(ERROR,
1021                                                 "DSP verify %x %x %x %x\n",
1022                                                 address, *pcode, data,
1023                                                 dsp_index);
1024                                         break;
1025                                 }
1026                                 pcode++;
1027                                 address += 4;
1028                         }
1029                         if (error)
1030                                 break;
1031                 }
1032                 hpi_dsp_code_close(&dsp_code);
1033                 if (error)
1034                         return error;
1035
1036                 /* zero out the hostmailbox */
1037                 {
1038                         u32 address = HPI_HIF_ADDR(host_cmd);
1039                         for (i = 0; i < 4; i++) {
1040                                 hpi_write_word(pdo, address, 0);
1041                                 address += 4;
1042                         }
1043                 }
1044                 /* write the DSP number into the hostmailbox */
1045                 /* structure before starting the DSP */
1046                 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1047
1048                 /* write the DSP adapter Info into the */
1049                 /* hostmailbox before starting the DSP */
1050                 if (dsp_index > 0)
1051                         hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1052                                 adapter_info);
1053
1054                 /* step 3. Start code by sending interrupt */
1055                 iowrite32(0x00030003, pdo->prHPI_control);
1056                 hpios_delay_micro_seconds(10000);
1057
1058                 /* wait for a non-zero value in hostcmd -
1059                  * indicating initialization is complete
1060                  *
1061                  * Init could take a while if DSP checks SDRAM memory
1062                  * Was 200000. Increased to 2000000 for ASI8801 so we
1063                  * don't get 938 errors.
1064                  */
1065                 timeout = 2000000;
1066                 while (timeout) {
1067                         do {
1068                                 read = hpi_read_word(pdo,
1069                                         HPI_HIF_ADDR(host_cmd));
1070                         } while (--timeout
1071                                 && hpi6000_check_PCI2040_error_flag(pao,
1072                                         H6READ));
1073
1074                         if (read)
1075                                 break;
1076                         /* The following is a workaround for bug #94:
1077                          * Bluescreen on install and subsequent boots on a
1078                          * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1079                          * ServerWorks chipset. Without this delay the system
1080                          * locks up with a bluescreen (NOT GPF or pagefault).
1081                          */
1082                         else
1083                                 hpios_delay_micro_seconds(10000);
1084                 }
1085                 if (timeout == 0)
1086                         return HPI6000_ERROR_INIT_NOACK;
1087
1088                 /* read the DSP adapter Info from the */
1089                 /* hostmailbox structure after starting the DSP */
1090                 if (dsp_index == 0) {
1091                         /*u32 dwTestData=0; */
1092                         u32 mask = 0;
1093
1094                         adapter_info =
1095                                 hpi_read_word(pdo,
1096                                 HPI_HIF_ADDR(adapter_info));
1097                         if (HPI_ADAPTER_FAMILY_ASI
1098                                 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1099                                         (adapter_info)) ==
1100                                 HPI_ADAPTER_FAMILY_ASI(0x6200))
1101                                 /* all 6200 cards have this many DSPs */
1102                                 phw->num_dsp = 2;
1103
1104                         /* test that the PLD is programmed */
1105                         /* and we can read/write 24bits */
1106 #define PLD_BASE_ADDRESS 0x90000000L    /*for ASI6100/6200/8800 */
1107
1108                         switch (boot_load_family) {
1109                         case HPI_ADAPTER_FAMILY_ASI(0x6200):
1110                                 /* ASI6100/6200 has 24bit path to FPGA */
1111                                 mask = 0xFFFFFF00L;
1112                                 /* ASI5100 uses AX6 code, */
1113                                 /* but has no PLD r/w register to test */
1114                                 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1115                                                 subsystem_device) ==
1116                                         HPI_ADAPTER_FAMILY_ASI(0x5100))
1117                                         mask = 0x00000000L;
1118                                 /* ASI5200 uses AX6 code, */
1119                                 /* but has no PLD r/w register to test */
1120                                 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1121                                                 subsystem_device) ==
1122                                         HPI_ADAPTER_FAMILY_ASI(0x5200))
1123                                         mask = 0x00000000L;
1124                                 break;
1125                         case HPI_ADAPTER_FAMILY_ASI(0x8800):
1126                                 /* ASI8800 has 16bit path to FPGA */
1127                                 mask = 0xFFFF0000L;
1128                                 break;
1129                         }
1130                         test_data = 0xAAAAAA00L & mask;
1131                         /* write to 24 bit Debug register (D31-D8) */
1132                         hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1133                         read = hpi_read_word(pdo,
1134                                 PLD_BASE_ADDRESS + 4L) & mask;
1135                         if (read != test_data) {
1136                                 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1137                                         read);
1138                                 return HPI6000_ERROR_INIT_PLDTEST1;
1139                         }
1140                         test_data = 0x55555500L & mask;
1141                         hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1142                         read = hpi_read_word(pdo,
1143                                 PLD_BASE_ADDRESS + 4L) & mask;
1144                         if (read != test_data) {
1145                                 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1146                                         read);
1147                                 return HPI6000_ERROR_INIT_PLDTEST2;
1148                         }
1149                 }
1150         }       /* for numDSP */
1151         return 0;
1152 }
1153
1154 #define PCI_TIMEOUT 100
1155
1156 static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1157 {
1158         u32 timeout = PCI_TIMEOUT;
1159
1160         do {
1161                 iowrite32(address, pdo->prHPI_address);
1162         } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1163                         H6WRITE)
1164                 && --timeout);
1165
1166         if (timeout)
1167                 return 0;
1168
1169         return 1;
1170 }
1171
1172 /* write one word to the HPI port */
1173 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1174 {
1175         if (hpi_set_address(pdo, address))
1176                 return;
1177         iowrite32(data, pdo->prHPI_data);
1178 }
1179
1180 /* read one word from the HPI port */
1181 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1182 {
1183         u32 data = 0;
1184
1185         if (hpi_set_address(pdo, address))
1186                 return 0;       /*? No way to return error */
1187
1188         /* take care of errata in revB DSP (2.0.1) */
1189         data = ioread32(pdo->prHPI_data);
1190         return data;
1191 }
1192
1193 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1194 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1195         u32 length)
1196 {
1197         u16 length16 = length - 1;
1198
1199         if (length == 0)
1200                 return;
1201
1202         if (hpi_set_address(pdo, address))
1203                 return;
1204
1205         iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1206
1207         /* take care of errata in revB DSP (2.0.1) */
1208         /* must end with non auto-inc */
1209         iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1210 }
1211
1212 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1213  */
1214 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1215         u32 length)
1216 {
1217         u16 length16 = length - 1;
1218
1219         if (length == 0)
1220                 return;
1221
1222         if (hpi_set_address(pdo, address))
1223                 return;
1224
1225         ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1226
1227         /* take care of errata in revB DSP (2.0.1) */
1228         /* must end with non auto-inc */
1229         *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1230 }
1231
1232 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1233         u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1234 {
1235         struct dsp_obj *pdo =
1236                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1237         u32 time_out = PCI_TIMEOUT;
1238         int c6711_burst_size = 128;
1239         u32 local_hpi_address = hpi_address;
1240         int local_count = count;
1241         int xfer_size;
1242         u32 *pdata = source;
1243
1244         while (local_count) {
1245                 if (local_count > c6711_burst_size)
1246                         xfer_size = c6711_burst_size;
1247                 else
1248                         xfer_size = local_count;
1249
1250                 time_out = PCI_TIMEOUT;
1251                 do {
1252                         hpi_write_block(pdo, local_hpi_address, pdata,
1253                                 xfer_size);
1254                 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1255                         && --time_out);
1256
1257                 if (!time_out)
1258                         break;
1259                 pdata += xfer_size;
1260                 local_hpi_address += sizeof(u32) * xfer_size;
1261                 local_count -= xfer_size;
1262         }
1263
1264         if (time_out)
1265                 return 0;
1266         else
1267                 return 1;
1268 }
1269
1270 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1271         u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1272 {
1273         struct dsp_obj *pdo =
1274                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1275         u32 time_out = PCI_TIMEOUT;
1276         int c6711_burst_size = 16;
1277         u32 local_hpi_address = hpi_address;
1278         int local_count = count;
1279         int xfer_size;
1280         u32 *pdata = dest;
1281         u32 loop_count = 0;
1282
1283         while (local_count) {
1284                 if (local_count > c6711_burst_size)
1285                         xfer_size = c6711_burst_size;
1286                 else
1287                         xfer_size = local_count;
1288
1289                 time_out = PCI_TIMEOUT;
1290                 do {
1291                         hpi_read_block(pdo, local_hpi_address, pdata,
1292                                 xfer_size);
1293                 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1294                         && --time_out);
1295                 if (!time_out)
1296                         break;
1297
1298                 pdata += xfer_size;
1299                 local_hpi_address += sizeof(u32) * xfer_size;
1300                 local_count -= xfer_size;
1301                 loop_count++;
1302         }
1303
1304         if (time_out)
1305                 return 0;
1306         else
1307                 return 1;
1308 }
1309
1310 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1311         u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1312 {
1313         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1314         struct dsp_obj *pdo = &phw->ado[dsp_index];
1315         u32 timeout;
1316         u16 ack;
1317         u32 address;
1318         u32 length;
1319         u32 *p_data;
1320         u16 error = 0;
1321
1322         ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1323         if (ack & HPI_HIF_ERROR_MASK) {
1324                 pao->dsp_crashed++;
1325                 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1326         }
1327         pao->dsp_crashed = 0;
1328
1329         /* get the message address and size */
1330         if (phw->message_buffer_address_on_dsp == 0) {
1331                 timeout = TIMEOUT;
1332                 do {
1333                         address =
1334                                 hpi_read_word(pdo,
1335                                 HPI_HIF_ADDR(message_buffer_address));
1336                         phw->message_buffer_address_on_dsp = address;
1337                 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1338                         && --timeout);
1339                 if (!timeout)
1340                         return HPI6000_ERROR_MSG_GET_ADR;
1341         } else
1342                 address = phw->message_buffer_address_on_dsp;
1343
1344         length = phm->size;
1345
1346         /* send the message */
1347         p_data = (u32 *)phm;
1348         if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1349                         (u16)length / 4))
1350                 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1351
1352         if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1353                 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1354         hpi6000_send_dsp_interrupt(pdo);
1355
1356         ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1357         if (ack & HPI_HIF_ERROR_MASK)
1358                 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1359
1360         /* get the response address */
1361         if (phw->response_buffer_address_on_dsp == 0) {
1362                 timeout = TIMEOUT;
1363                 do {
1364                         address =
1365                                 hpi_read_word(pdo,
1366                                 HPI_HIF_ADDR(response_buffer_address));
1367                 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1368                         && --timeout);
1369                 phw->response_buffer_address_on_dsp = address;
1370
1371                 if (!timeout)
1372                         return HPI6000_ERROR_RESP_GET_ADR;
1373         } else
1374                 address = phw->response_buffer_address_on_dsp;
1375
1376         /* read the length of the response back from the DSP */
1377         timeout = TIMEOUT;
1378         do {
1379                 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1380         } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1381         if (!timeout)
1382                 length = sizeof(struct hpi_response);
1383
1384         /* get the response */
1385         p_data = (u32 *)phr;
1386         if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1387                         (u16)length / 4))
1388                 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1389
1390         /* set i/f back to idle */
1391         if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1392                 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1393         hpi6000_send_dsp_interrupt(pdo);
1394
1395         error = hpi_validate_response(phm, phr);
1396         return error;
1397 }
1398
1399 /* have to set up the below defines to match stuff in the MAP file */
1400
1401 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1402 #define MSG_LENGTH 11
1403 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1404 #define RESP_LENGTH 16
1405 #define QUEUE_START  (HPI_HIF_BASE+0x88)
1406 #define QUEUE_SIZE 0x8000
1407
1408 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1409 {
1410 /*#define CHECKING       // comment this line in to enable checking */
1411 #ifdef CHECKING
1412         if (address < (u32)MSG_ADDRESS)
1413                 return 0;
1414         if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1415                 return 0;
1416         if ((address + (length_in_dwords << 2)) >
1417                 (u32)(QUEUE_START + QUEUE_SIZE))
1418                 return 0;
1419 #else
1420         (void)address;
1421         (void)length_in_dwords;
1422         return 1;
1423 #endif
1424 }
1425
1426 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1427         struct hpi_message *phm, struct hpi_response *phr)
1428 {
1429         struct dsp_obj *pdo =
1430                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1431         u32 data_sent = 0;
1432         u16 ack;
1433         u32 length, address;
1434         u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1435         u16 time_out = 8;
1436
1437         (void)phr;
1438
1439         /* round dwDataSize down to nearest 4 bytes */
1440         while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1441                 && --time_out) {
1442                 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1443                 if (ack & HPI_HIF_ERROR_MASK)
1444                         return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1445
1446                 if (hpi6000_send_host_command(pao, dsp_index,
1447                                 HPI_HIF_SEND_DATA))
1448                         return HPI6000_ERROR_SEND_DATA_CMD;
1449
1450                 hpi6000_send_dsp_interrupt(pdo);
1451
1452                 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1453
1454                 if (ack & HPI_HIF_ERROR_MASK)
1455                         return HPI6000_ERROR_SEND_DATA_ACK;
1456
1457                 do {
1458                         /* get the address and size */
1459                         address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1460                         /* DSP returns number of DWORDS */
1461                         length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1462                 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1463
1464                 if (!hpi6000_send_data_check_adr(address, length))
1465                         return HPI6000_ERROR_SEND_DATA_ADR;
1466
1467                 /* send the data. break data into 512 DWORD blocks (2K bytes)
1468                  * and send using block write. 2Kbytes is the max as this is the
1469                  * memory window given to the HPI data register by the PCI2040
1470                  */
1471
1472                 {
1473                         u32 len = length;
1474                         u32 blk_len = 512;
1475                         while (len) {
1476                                 if (len < blk_len)
1477                                         blk_len = len;
1478                                 if (hpi6000_dsp_block_write32(pao, dsp_index,
1479                                                 address, p_data, blk_len))
1480                                         return HPI6000_ERROR_SEND_DATA_WRITE;
1481                                 address += blk_len * 4;
1482                                 p_data += blk_len;
1483                                 len -= blk_len;
1484                         }
1485                 }
1486
1487                 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1488                         return HPI6000_ERROR_SEND_DATA_IDLECMD;
1489
1490                 hpi6000_send_dsp_interrupt(pdo);
1491
1492                 data_sent += length * 4;
1493         }
1494         if (!time_out)
1495                 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1496         return 0;
1497 }
1498
1499 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1500         struct hpi_message *phm, struct hpi_response *phr)
1501 {
1502         struct dsp_obj *pdo =
1503                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1504         u32 data_got = 0;
1505         u16 ack;
1506         u32 length, address;
1507         u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1508
1509         (void)phr;      /* this parameter not used! */
1510
1511         /* round dwDataSize down to nearest 4 bytes */
1512         while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1513                 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1514                 if (ack & HPI_HIF_ERROR_MASK)
1515                         return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1516
1517                 if (hpi6000_send_host_command(pao, dsp_index,
1518                                 HPI_HIF_GET_DATA))
1519                         return HPI6000_ERROR_GET_DATA_CMD;
1520                 hpi6000_send_dsp_interrupt(pdo);
1521
1522                 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1523
1524                 if (ack & HPI_HIF_ERROR_MASK)
1525                         return HPI6000_ERROR_GET_DATA_ACK;
1526
1527                 /* get the address and size */
1528                 do {
1529                         address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1530                         length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1531                 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1532
1533                 /* read the data */
1534                 {
1535                         u32 len = length;
1536                         u32 blk_len = 512;
1537                         while (len) {
1538                                 if (len < blk_len)
1539                                         blk_len = len;
1540                                 if (hpi6000_dsp_block_read32(pao, dsp_index,
1541                                                 address, p_data, blk_len))
1542                                         return HPI6000_ERROR_GET_DATA_READ;
1543                                 address += blk_len * 4;
1544                                 p_data += blk_len;
1545                                 len -= blk_len;
1546                         }
1547                 }
1548
1549                 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1550                         return HPI6000_ERROR_GET_DATA_IDLECMD;
1551                 hpi6000_send_dsp_interrupt(pdo);
1552
1553                 data_got += length * 4;
1554         }
1555         return 0;
1556 }
1557
1558 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1559 {
1560         iowrite32(0x00030003, pdo->prHPI_control);      /* DSPINT */
1561 }
1562
1563 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1564         u16 dsp_index, u32 host_cmd)
1565 {
1566         struct dsp_obj *pdo =
1567                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1568         u32 timeout = TIMEOUT;
1569
1570         /* set command */
1571         do {
1572                 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1573                 /* flush the FIFO */
1574                 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1575         } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1576
1577         /* reset the interrupt bit */
1578         iowrite32(0x00040004, pdo->prHPI_control);
1579
1580         if (timeout)
1581                 return 0;
1582         else
1583                 return 1;
1584 }
1585
1586 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1587 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1588         u16 read_or_write)
1589 {
1590         u32 hPI_error;
1591
1592         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1593
1594         /* read the error bits from the PCI2040 */
1595         hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1596         if (hPI_error) {
1597                 /* reset the error flag */
1598                 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1599                 phw->pCI2040HPI_error_count++;
1600                 if (read_or_write == 1)
1601                         gw_pci_read_asserts++;     /************* inc global */
1602                 else
1603                         gw_pci_write_asserts++;
1604                 return 1;
1605         } else
1606                 return 0;
1607 }
1608
1609 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1610         u32 ack_value)
1611 {
1612         struct dsp_obj *pdo =
1613                 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1614         u32 ack = 0L;
1615         u32 timeout;
1616         u32 hPIC = 0L;
1617
1618         /* wait for host interrupt to signal ack is ready */
1619         timeout = TIMEOUT;
1620         while (--timeout) {
1621                 hPIC = ioread32(pdo->prHPI_control);
1622                 if (hPIC & 0x04)        /* 0x04 = HINT from DSP */
1623                         break;
1624         }
1625         if (timeout == 0)
1626                 return HPI_HIF_ERROR_MASK;
1627
1628         /* wait for dwAckValue */
1629         timeout = TIMEOUT;
1630         while (--timeout) {
1631                 /* read the ack mailbox */
1632                 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1633                 if (ack == ack_value)
1634                         break;
1635                 if ((ack & HPI_HIF_ERROR_MASK)
1636                         && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1637                         break;
1638                 /*for (i=0;i<1000;i++) */
1639                 /*      dwPause=i+1; */
1640         }
1641         if (ack & HPI_HIF_ERROR_MASK)
1642                 /* indicates bad read from DSP -
1643                    typically 0xffffff is read for some reason */
1644                 ack = HPI_HIF_ERROR_MASK;
1645
1646         if (timeout == 0)
1647                 ack = HPI_HIF_ERROR_MASK;
1648         return (short)ack;
1649 }
1650
1651 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1652         struct hpi_message *phm)
1653 {
1654         const u16 dsp_index = 0;
1655         struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1656         struct dsp_obj *pdo = &phw->ado[dsp_index];
1657         u32 timeout;
1658         u32 cache_dirty_flag;
1659         u16 err;
1660
1661         hpios_dsplock_lock(pao);
1662
1663         timeout = TIMEOUT;
1664         do {
1665                 cache_dirty_flag =
1666                         hpi_read_word((struct dsp_obj *)pdo,
1667                         HPI_HIF_ADDR(control_cache_is_dirty));
1668         } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1669         if (!timeout) {
1670                 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1671                 goto unlock;
1672         }
1673
1674         if (cache_dirty_flag) {
1675                 /* read the cached controls */
1676                 u32 address;
1677                 u32 length;
1678
1679                 timeout = TIMEOUT;
1680                 if (pdo->control_cache_address_on_dsp == 0) {
1681                         do {
1682                                 address =
1683                                         hpi_read_word((struct dsp_obj *)pdo,
1684                                         HPI_HIF_ADDR(control_cache_address));
1685
1686                                 length = hpi_read_word((struct dsp_obj *)pdo,
1687                                         HPI_HIF_ADDR
1688                                         (control_cache_size_in_bytes));
1689                         } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1690                                 && --timeout);
1691                         if (!timeout) {
1692                                 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1693                                 goto unlock;
1694                         }
1695                         pdo->control_cache_address_on_dsp = address;
1696                         pdo->control_cache_length_on_dsp = length;
1697                 } else {
1698                         address = pdo->control_cache_address_on_dsp;
1699                         length = pdo->control_cache_length_on_dsp;
1700                 }
1701
1702                 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1703                                 (u32 *)&phw->control_cache[0],
1704                                 length / sizeof(u32))) {
1705                         err = HPI6000_ERROR_CONTROL_CACHE_READ;
1706                         goto unlock;
1707                 }
1708                 do {
1709                         hpi_write_word((struct dsp_obj *)pdo,
1710                                 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1711                         /* flush the FIFO */
1712                         hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1713                 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1714                         && --timeout);
1715                 if (!timeout) {
1716                         err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1717                         goto unlock;
1718                 }
1719
1720         }
1721         err = 0;
1722
1723 unlock:
1724         hpios_dsplock_unlock(pao);
1725         return err;
1726 }
1727
1728 /** Get dsp index for multi DSP adapters only */
1729 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1730 {
1731         u16 ret = 0;
1732         switch (phm->object) {
1733         case HPI_OBJ_ISTREAM:
1734                 if (phm->obj_index < 2)
1735                         ret = 1;
1736                 break;
1737         case HPI_OBJ_PROFILE:
1738                 ret = phm->obj_index;
1739                 break;
1740         default:
1741                 break;
1742         }
1743         return ret;
1744 }
1745
1746 /** Complete transaction with DSP
1747
1748 Send message, get response, send or get stream data if any.
1749 */
1750 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1751         struct hpi_response *phr)
1752 {
1753         u16 error = 0;
1754         u16 dsp_index = 0;
1755         u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
1756
1757         if (num_dsp < 2)
1758                 dsp_index = 0;
1759         else {
1760                 dsp_index = get_dsp_index(pao, phm);
1761
1762                 /* is this  checked on the DSP anyway? */
1763                 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1764                         || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1765                         struct hpi_message hm;
1766                         u16 add_index;
1767                         hm.obj_index = phm->u.d.u.stream.stream_index;
1768                         hm.object = phm->u.d.u.stream.object_type;
1769                         add_index = get_dsp_index(pao, &hm);
1770                         if (add_index != dsp_index) {
1771                                 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1772                                 return;
1773                         }
1774                 }
1775         }
1776
1777         hpios_dsplock_lock(pao);
1778         error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1779
1780         if (error)      /* something failed in the HPI/DSP interface */
1781                 goto err;
1782
1783         if (phr->error) /* something failed in the DSP */
1784                 goto out;
1785
1786         switch (phm->function) {
1787         case HPI_OSTREAM_WRITE:
1788         case HPI_ISTREAM_ANC_WRITE:
1789                 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1790                 break;
1791         case HPI_ISTREAM_READ:
1792         case HPI_OSTREAM_ANC_READ:
1793                 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1794                 break;
1795         case HPI_ADAPTER_GET_ASSERT:
1796                 phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
1797                 if (num_dsp == 2) {
1798                         if (!phr->u.ax.assert.count) {
1799                                 /* no assert from dsp 0, check dsp 1 */
1800                                 error = hpi6000_message_response_sequence(pao,
1801                                         1, phm, phr);
1802                                 phr->u.ax.assert.dsp_index = 1;
1803                         }
1804                 }
1805         }
1806
1807 err:
1808         if (error) {
1809                 if (error >= HPI_ERROR_BACKEND_BASE) {
1810                         phr->error = HPI_ERROR_DSP_COMMUNICATION;
1811                         phr->specific_error = error;
1812                 } else {
1813                         phr->error = error;
1814                 }
1815
1816                 /* just the header of the response is valid */
1817                 phr->size = sizeof(struct hpi_response_header);
1818         }
1819 out:
1820         hpios_dsplock_unlock(pao);
1821         return;
1822 }