sound/oss/swarm_cs4297a.c

   1 /*******************************************************************************
   2 *
   3 *      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4 *
   5 *      Copyright (C) 2001  Broadcom Corporation.
   6 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   7 *            -- adapted from drivers by Thomas Sailer,
   8 *            -- but don't bug him; Problems should go to:
   9 *            -- tom woller (twoller@crystal.cirrus.com) or
  10 *               (audio@crystal.cirrus.com).
  11 *            -- adapted from cs4281 PCI driver for cs4297a on
  12 *               BCM1250 Synchronous Serial interface
  13 *               (Kip Walker, Broadcom Corp.)
  14 *      Copyright (C) 2004  Maciej W. Rozycki
  15 *      Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  16 *
  17 *      This program is free software; you can redistribute it and/or modify
  18 *      it under the terms of the GNU General Public License as published by
  19 *      the Free Software Foundation; either version 2 of the License, or
  20 *      (at your option) any later version.
  21 *
  22 *      This program is distributed in the hope that it will be useful,
  23 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *      GNU General Public License for more details.
  26 *
  27 *      You should have received a copy of the GNU General Public License
  28 *      along with this program; if not, write to the Free Software
  29 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 * Module command line parameters:
  32 *   none
  33 *
  34 *  Supported devices:
  35 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  36 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  37 *  /dev/midi   simple MIDI UART interface, no ioctl
  38 *
  39 * Modification History
  40 * 08/20/00 trw - silence and no stopping DAC until release
  41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  42 * 09/18/00 trw - added 16bit only record with conversion
  43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  44 *                capture/playback rates)
  45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  46 *                libOSSm.so)
  47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  53 * 12/08/00 trw - added PM support.
  54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  55 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  58 *                defaultorder-100 as power of 2 for the buffer size. example:
  59 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  60 *
  61 *******************************************************************************/
  62
  63 #include <linux/list.h>
  64 #include <linux/module.h>
  65 #include <linux/string.h>
  66 #include <linux/ioport.h>
  67 #include <linux/sched.h>
  68 #include <linux/delay.h>
  69 #include <linux/sound.h>
  70 #include <linux/slab.h>
  71 #include <linux/soundcard.h>
  72 #include <linux/pci.h>
  73 #include <linux/bitops.h>
  74 #include <linux/interrupt.h>
  75 #include <linux/init.h>
  76 #include <linux/poll.h>
  77 #include <linux/mutex.h>
  78 #include <linux/kernel.h>
  79
  80 #include <asm/byteorder.h>
  81 #include <asm/dma.h>
  82 #include <asm/io.h>
  83 #include <asm/uaccess.h>
  84
  85 #include <asm/sibyte/sb1250_regs.h>
  86 #include <asm/sibyte/sb1250_int.h>
  87 #include <asm/sibyte/sb1250_dma.h>
  88 #include <asm/sibyte/sb1250_scd.h>
  89 #include <asm/sibyte/sb1250_syncser.h>
  90 #include <asm/sibyte/sb1250_mac.h>
  91 #include <asm/sibyte/sb1250.h>
  92
  93 struct cs4297a_state;
  94
  95 static DEFINE_MUTEX(swarm_cs4297a_mutex);
  96 static void stop_dac(struct cs4297a_state *s);
  97 static void stop_adc(struct cs4297a_state *s);
  98 static void start_dac(struct cs4297a_state *s);
  99 static void start_adc(struct cs4297a_state *s);
 100 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 101
 102 // ---------------------------------------------------------------------
 103
 104 #define CS4297a_MAGIC           0xf00beef1
 105
 106 // buffer order determines the size of the dma buffer for the driver.
 107 // under Linux, a smaller buffer allows more responsiveness from many of the
 108 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 109 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 110 // rather than 64k as some of the games work more responsively.
 111 // log base 2( buff sz = 32k).
 112
 113 //
 114 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 115 //
 116 #define CSDEBUG 0
 117 #if CSDEBUG
 118 #define CSDEBUG_INTERFACE 1
 119 #else
 120 #undef CSDEBUG_INTERFACE
 121 #endif
 122 //
 123 // cs_debugmask areas
 124 //
 125 #define CS_INIT         0x00000001      // initialization and probe functions
 126 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 127 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 128 #define CS_FUNCTION     0x00000008      // enter/leave functions
 129 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 130 #define CS_WAVE_READ    0x00000020      // read information for wave
 131 #define CS_AC97         0x00000040      // AC97 register access
 132 #define CS_DESCR        0x00000080      // descriptor management
 133 #define CS_OPEN         0x00000400      // all open functions in the driver
 134 #define CS_RELEASE      0x00000800      // all release functions in the driver
 135 #define CS_PARMS        0x00001000      // functional and operational parameters
 136 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 137 #define CS_TMP          0x10000000      // tmp debug mask bit
 138
 139 //
 140 // CSDEBUG is usual mode is set to 1, then use the
 141 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 142 // Debug level of 1 has been defined to be kernel errors and info
 143 // that should be printed on any released driver.
 144 //
 145 #if CSDEBUG
 146 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 147 #else
 148 #define CS_DBGOUT(mask,level,x)
 149 #endif
 150
 151 #if CSDEBUG
 152 static unsigned long cs_debuglevel = 4; // levels range from 1-9
 153 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 154 module_param(cs_debuglevel, int, 0);
 155 module_param(cs_debugmask, int, 0);
 156 #endif
 157 #define CS_TRUE         1
 158 #define CS_FALSE        0
 159
 160 #define CS_TYPE_ADC 0
 161 #define CS_TYPE_DAC 1
 162
 163 #define SER_BASE    (A_SER_BASE_1 + KSEG1)
 164 #define SS_CSR(t)   (SER_BASE+t)
 165 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 166 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 167
 168 #define FRAME_BYTES            32
 169 #define FRAME_SAMPLE_BYTES      4
 170
 171 /* Should this be variable? */
 172 #define SAMPLE_BUF_SIZE        (16*1024)
 173 #define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 174 /* The driver can explode/shrink the frames to/from a smaller sample
 175    buffer */
 176 #define DMA_BLOAT_FACTOR       1
 177 #define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 178 #define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 179
 180 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
 181 #define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 182
 183 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
 184 #define REG_LATENCY            150
 185
 186 #define FRAME_TX_US             20
 187
 188 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 189
 190 static const char invalid_magic[] =
 191     KERN_CRIT "cs4297a: invalid magic value\n";
 192
 193 #define VALIDATE_STATE(s)                          \
 194 ({                                                 \
 195         if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 196                 printk(invalid_magic);             \
 197                 return -ENXIO;                     \
 198         }                                          \
 199 })
 200
 201 /* AC97 registers */
 202 #define AC97_MASTER_VOL_STEREO   0x0002      /* Line Out                */
 203 #define AC97_PCBEEP_VOL          0x000a      /* none                    */
 204 #define AC97_PHONE_VOL           0x000c      /* TAD Input (mono)        */
 205 #define AC97_MIC_VOL             0x000e      /* MIC Input (mono)        */
 206 #define AC97_LINEIN_VOL          0x0010      /* Line Input (stereo)     */
 207 #define AC97_CD_VOL              0x0012      /* CD Input (stereo)       */
 208 #define AC97_AUX_VOL             0x0016      /* Aux Input (stereo)      */
 209 #define AC97_PCMOUT_VOL          0x0018      /* Wave Output (stereo)    */
 210 #define AC97_RECORD_SELECT       0x001a      /*                 */
 211 #define AC97_RECORD_GAIN         0x001c
 212 #define AC97_GENERAL_PURPOSE     0x0020
 213 #define AC97_3D_CONTROL          0x0022
 214 #define AC97_POWER_CONTROL       0x0026
 215 #define AC97_VENDOR_ID1           0x007c
 216
 217 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 218
 219 typedef struct serdma_descr_s {
 220         u64 descr_a;
 221         u64 descr_b;
 222 } serdma_descr_t;
 223
 224 typedef unsigned long paddr_t;
 225
 226 typedef struct serdma_s {
 227         unsigned         ringsz;
 228         serdma_descr_t  *descrtab;
 229         serdma_descr_t  *descrtab_end;
 230         paddr_t          descrtab_phys;
 231
 232         serdma_descr_t  *descr_add;
 233         serdma_descr_t  *descr_rem;
 234
 235         u64  *dma_buf;           // buffer for DMA contents (frames)
 236         paddr_t          dma_buf_phys;
 237         u16  *sample_buf;               // tmp buffer for sample conversions
 238         u16  *sb_swptr;
 239         u16  *sb_hwptr;
 240         u16  *sb_end;
 241
 242         dma_addr_t dmaaddr;
 243 //        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 244         unsigned numfrag;       // # of 'fragments' in the buffer.
 245         unsigned fragshift;     // Log base 2 of fragment size.
 246         unsigned hwptr, swptr;
 247         unsigned total_bytes;   // # bytes process since open.
 248         unsigned blocks;        // last returned blocks value GETOPTR
 249         unsigned wakeup;        // interrupt occurred on block
 250         int count;
 251         unsigned underrun;      // underrun flag
 252         unsigned error; // over/underrun
 253         wait_queue_head_t wait;
 254         wait_queue_head_t reg_wait;
 255         // redundant, but makes calculations easier
 256         unsigned fragsize;      // 2**fragshift..
 257         unsigned sbufsz;        // 2**buforder.
 258         unsigned fragsamples;
 259         // OSS stuff
 260         unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 261         unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 262         unsigned endcleared:1;
 263         unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 264         unsigned ossfragshift;
 265         int ossmaxfrags;
 266         unsigned subdivision;
 267 } serdma_t;
 268
 269 struct cs4297a_state {
 270         // magic
 271         unsigned int magic;
 272
 273         struct list_head list;
 274
 275         // soundcore stuff
 276         int dev_audio;
 277         int dev_mixer;
 278
 279         // hardware resources
 280         unsigned int irq;
 281
 282         struct {
 283                 unsigned int rx_ovrrn; /* FIFO */
 284                 unsigned int rx_overflow; /* staging buffer */
 285                 unsigned int tx_underrun;
 286                 unsigned int rx_bad;
 287                 unsigned int rx_good;
 288         } stats;
 289
 290         // mixer registers
 291         struct {
 292                 unsigned short vol[10];
 293                 unsigned int recsrc;
 294                 unsigned int modcnt;
 295                 unsigned short micpreamp;
 296         } mix;
 297
 298         // wave stuff
 299         struct properties {
 300                 unsigned fmt;
 301                 unsigned fmt_original;  // original requested format
 302                 unsigned channels;
 303                 unsigned rate;
 304         } prop_dac, prop_adc;
 305         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 306         unsigned ena;
 307         spinlock_t lock;
 308         struct mutex open_mutex;
 309         struct mutex open_sem_adc;
 310         struct mutex open_sem_dac;
 311         fmode_t open_mode;
 312         wait_queue_head_t open_wait;
 313         wait_queue_head_t open_wait_adc;
 314         wait_queue_head_t open_wait_dac;
 315
 316         dma_addr_t dmaaddr_sample_buf;
 317         unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 318
 319         serdma_t dma_dac, dma_adc;
 320
 321         volatile u16 read_value;
 322         volatile u16 read_reg;
 323         volatile u64 reg_request;
 324 };
 325
 326 #if 1
 327 #define prog_codec(a,b)
 328 #define dealloc_dmabuf(a,b);
 329 #endif
 330
 331 static int prog_dmabuf_adc(struct cs4297a_state *s)
 332 {
 333         s->dma_adc.ready = 1;
 334         return 0;
 335 }
 336
 337
 338 static int prog_dmabuf_dac(struct cs4297a_state *s)
 339 {
 340         s->dma_dac.ready = 1;
 341         return 0;
 342 }
 343
 344 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 345                           unsigned len, unsigned char c)
 346 {
 347         if (bptr + len > bsize) {
 348                 unsigned x = bsize - bptr;
 349                 memset(((char *) buf) + bptr, c, x);
 350                 bptr = 0;
 351                 len -= x;
 352         }
 353         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 354                 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 355                         (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 356         memset(((char *) buf) + bptr, c, len);
 357 }
 358
 359 #if CSDEBUG
 360
 361 // DEBUG ROUTINES
 362
 363 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 364 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 365 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 366 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 367
 368 static void cs_printioctl(unsigned int x)
 369 {
 370         unsigned int i;
 371         unsigned char vidx;
 372         // Index of mixtable1[] member is Device ID
 373         // and must be <= SOUND_MIXER_NRDEVICES.
 374         // Value of array member is index into s->mix.vol[]
 375         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 376                 [SOUND_MIXER_PCM] = 1,  // voice
 377                 [SOUND_MIXER_LINE1] = 2,        // AUX
 378                 [SOUND_MIXER_CD] = 3,   // CD
 379                 [SOUND_MIXER_LINE] = 4, // Line
 380                 [SOUND_MIXER_SYNTH] = 5,        // FM
 381                 [SOUND_MIXER_MIC] = 6,  // Mic
 382                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 383                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 384                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 385         };
 386
 387         switch (x) {
 388         case SOUND_MIXER_CS_GETDBGMASK:
 389                 CS_DBGOUT(CS_IOCTL, 4,
 390                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 391                 break;
 392         case SOUND_MIXER_CS_GETDBGLEVEL:
 393                 CS_DBGOUT(CS_IOCTL, 4,
 394                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 395                 break;
 396         case SOUND_MIXER_CS_SETDBGMASK:
 397                 CS_DBGOUT(CS_IOCTL, 4,
 398                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 399                 break;
 400         case SOUND_MIXER_CS_SETDBGLEVEL:
 401                 CS_DBGOUT(CS_IOCTL, 4,
 402                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 403                 break;
 404         case OSS_GETVERSION:
 405                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 406                 break;
 407         case SNDCTL_DSP_SYNC:
 408                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 409                 break;
 410         case SNDCTL_DSP_SETDUPLEX:
 411                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 412                 break;
 413         case SNDCTL_DSP_GETCAPS:
 414                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 415                 break;
 416         case SNDCTL_DSP_RESET:
 417                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 418                 break;
 419         case SNDCTL_DSP_SPEED:
 420                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 421                 break;
 422         case SNDCTL_DSP_STEREO:
 423                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 424                 break;
 425         case SNDCTL_DSP_CHANNELS:
 426                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 427                 break;
 428         case SNDCTL_DSP_GETFMTS:
 429                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 430                 break;
 431         case SNDCTL_DSP_SETFMT:
 432                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 433                 break;
 434         case SNDCTL_DSP_POST:
 435                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 436                 break;
 437         case SNDCTL_DSP_GETTRIGGER:
 438                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 439                 break;
 440         case SNDCTL_DSP_SETTRIGGER:
 441                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 442                 break;
 443         case SNDCTL_DSP_GETOSPACE:
 444                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 445                 break;
 446         case SNDCTL_DSP_GETISPACE:
 447                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 448                 break;
 449         case SNDCTL_DSP_NONBLOCK:
 450                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 451                 break;
 452         case SNDCTL_DSP_GETODELAY:
 453                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 454                 break;
 455         case SNDCTL_DSP_GETIPTR:
 456                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 457                 break;
 458         case SNDCTL_DSP_GETOPTR:
 459                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 460                 break;
 461         case SNDCTL_DSP_GETBLKSIZE:
 462                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 463                 break;
 464         case SNDCTL_DSP_SETFRAGMENT:
 465                 CS_DBGOUT(CS_IOCTL, 4,
 466                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 467                 break;
 468         case SNDCTL_DSP_SUBDIVIDE:
 469                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 470                 break;
 471         case SOUND_PCM_READ_RATE:
 472                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 473                 break;
 474         case SOUND_PCM_READ_CHANNELS:
 475                 CS_DBGOUT(CS_IOCTL, 4,
 476                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 477                 break;
 478         case SOUND_PCM_READ_BITS:
 479                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 480                 break;
 481         case SOUND_PCM_WRITE_FILTER:
 482                 CS_DBGOUT(CS_IOCTL, 4,
 483                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 484                 break;
 485         case SNDCTL_DSP_SETSYNCRO:
 486                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 487                 break;
 488         case SOUND_PCM_READ_FILTER:
 489                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 490                 break;
 491         case SOUND_MIXER_PRIVATE1:
 492                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 493                 break;
 494         case SOUND_MIXER_PRIVATE2:
 495                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 496                 break;
 497         case SOUND_MIXER_PRIVATE3:
 498                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 499                 break;
 500         case SOUND_MIXER_PRIVATE4:
 501                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 502                 break;
 503         case SOUND_MIXER_PRIVATE5:
 504                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 505                 break;
 506         case SOUND_MIXER_INFO:
 507                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 508                 break;
 509         case SOUND_OLD_MIXER_INFO:
 510                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 511                 break;
 512
 513         default:
 514                 switch (_IOC_NR(x)) {
 515                 case SOUND_MIXER_VOLUME:
 516                         CS_DBGOUT(CS_IOCTL, 4,
 517                                   printk("SOUND_MIXER_VOLUME:\n"));
 518                         break;
 519                 case SOUND_MIXER_SPEAKER:
 520                         CS_DBGOUT(CS_IOCTL, 4,
 521                                   printk("SOUND_MIXER_SPEAKER:\n"));
 522                         break;
 523                 case SOUND_MIXER_RECLEV:
 524                         CS_DBGOUT(CS_IOCTL, 4,
 525                                   printk("SOUND_MIXER_RECLEV:\n"));
 526                         break;
 527                 case SOUND_MIXER_MIC:
 528                         CS_DBGOUT(CS_IOCTL, 4,
 529                                   printk("SOUND_MIXER_MIC:\n"));
 530                         break;
 531                 case SOUND_MIXER_SYNTH:
 532                         CS_DBGOUT(CS_IOCTL, 4,
 533                                   printk("SOUND_MIXER_SYNTH:\n"));
 534                         break;
 535                 case SOUND_MIXER_RECSRC:
 536                         CS_DBGOUT(CS_IOCTL, 4,
 537                                   printk("SOUND_MIXER_RECSRC:\n"));
 538                         break;
 539                 case SOUND_MIXER_DEVMASK:
 540                         CS_DBGOUT(CS_IOCTL, 4,
 541                                   printk("SOUND_MIXER_DEVMASK:\n"));
 542                         break;
 543                 case SOUND_MIXER_RECMASK:
 544                         CS_DBGOUT(CS_IOCTL, 4,
 545                                   printk("SOUND_MIXER_RECMASK:\n"));
 546                         break;
 547                 case SOUND_MIXER_STEREODEVS:
 548                         CS_DBGOUT(CS_IOCTL, 4,
 549                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 550                         break;
 551                 case SOUND_MIXER_CAPS:
 552                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 553                         break;
 554                 default:
 555                         i = _IOC_NR(x);
 556                         if (i >= SOUND_MIXER_NRDEVICES
 557                             || !(vidx = mixtable1[i])) {
 558                                 CS_DBGOUT(CS_IOCTL, 4, printk
 559                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 560                                                 x, i));
 561                         } else {
 562                                 CS_DBGOUT(CS_IOCTL, 4, printk
 563                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 564                                                 x, i));
 565                         }
 566                         break;
 567                 }
 568         }
 569 }
 570 #endif
 571
 572
 573 static int ser_init(struct cs4297a_state *s)
 574 {
 575         int i;
 576
 577         CS_DBGOUT(CS_INIT, 2,
 578                   printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 579
 580         __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 581
 582         __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 583         __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
 584         __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
 585
 586         __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
 587         __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
 588         __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
 589
 590         /* This looks good from experimentation */
 591         __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 592                M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 593               SS_CSR(R_SER_LINE_MODE));
 594
 595         /* This looks good from experimentation */
 596         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 597               SS_TXTBL(0));
 598         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 599               SS_TXTBL(1));
 600         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 601               SS_TXTBL(2));
 602         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 603               M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 604
 605         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 606               SS_RXTBL(0));
 607         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 608               SS_RXTBL(1));
 609         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 610               SS_RXTBL(2));
 611         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 612               M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 613
 614         for (i=4; i<16; i++) {
 615                 /* Just in case... */
 616                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 617                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 618         }
 619
 620         return 0;
 621 }
 622
 623 static int init_serdma(serdma_t *dma)
 624 {
 625         CS_DBGOUT(CS_INIT, 2,
 626                   printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 627                          DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 628
 629         /* Descriptors */
 630         dma->ringsz = DMA_DESCR;
 631         dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 632         if (!dma->descrtab) {
 633                 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
 634                 return -1;
 635         }
 636         dma->descrtab_end = dma->descrtab + dma->ringsz;
 637         /* XXX bloddy mess, use proper DMA API here ...  */
 638         dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
 639         dma->descr_add = dma->descr_rem = dma->descrtab;
 640
 641         /* Frame buffer area */
 642         dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
 643         if (!dma->dma_buf) {
 644                 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
 645                 kfree(dma->descrtab);
 646                 return -1;
 647         }
 648         dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
 649
 650         /* Samples buffer area */
 651         dma->sbufsz = SAMPLE_BUF_SIZE;
 652         dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 653         if (!dma->sample_buf) {
 654                 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 655                 kfree(dma->descrtab);
 656                 kfree(dma->dma_buf);
 657                 return -1;
 658         }
 659         dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 660         dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 661         dma->fragsize = dma->sbufsz >> 1;
 662
 663         CS_DBGOUT(CS_INIT, 4,
 664                   printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 665                          (int)dma->descrtab, (int)dma->dma_buf,
 666                          (int)dma->sample_buf));
 667
 668         return 0;
 669 }
 670
 671 static int dma_init(struct cs4297a_state *s)
 672 {
 673         int i;
 674
 675         CS_DBGOUT(CS_INIT, 2,
 676                   printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 677
 678         if (init_serdma(&s->dma_adc) ||
 679             init_serdma(&s->dma_dac))
 680                 return -1;
 681
 682         if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 683             __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 684                 panic("DMA state corrupted?!");
 685         }
 686
 687         /* Initialize now - the descr/buffer pairings will never
 688            change... */
 689         for (i=0; i<DMA_DESCR; i++) {
 690                 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
 691                         (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 692                 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 693                 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 694                         (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 695                 s->dma_adc.descrtab[i].descr_b = 0;
 696         }
 697
 698         __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 699                V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 700               SS_CSR(R_SER_DMA_CONFIG0_RX));
 701         __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 702         __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 703
 704         __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 705         __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 706         __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 707
 708         /* Prep the receive DMA descriptor ring */
 709         __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 710
 711         __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 712
 713         __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 714               SS_CSR(R_SER_INT_MASK));
 715
 716         /* Enable the rx/tx; let the codec warm up to the sync and
 717            start sending good frames before the receive FIFO is
 718            enabled */
 719         __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 720         udelay(1000);
 721         __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 722
 723         /* XXXKW is this magic? (the "1" part) */
 724         while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 725                 ;
 726
 727         CS_DBGOUT(CS_INIT, 4,
 728                   printk(KERN_INFO "cs4297a: status: %08x\n",
 729                          (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 730
 731         return 0;
 732 }
 733
 734 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 735 {
 736         serdma_t *d = &s->dma_dac;
 737         u64 *data_p;
 738         unsigned swptr;
 739         unsigned long flags;
 740         serdma_descr_t *descr;
 741
 742         if (s->reg_request) {
 743                 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 744                 return -1;
 745         }
 746
 747         if (s->ena & FMODE_WRITE) {
 748                 /* Since a writer has the DSP open, we have to mux the
 749                    request in */
 750                 s->reg_request = data;
 751                 interruptible_sleep_on(&s->dma_dac.reg_wait);
 752                 /* XXXKW how can I deal with the starvation case where
 753                    the opener isn't writing? */
 754         } else {
 755                 /* Be safe when changing ring pointers */
 756                 spin_lock_irqsave(&s->lock, flags);
 757                 if (d->hwptr != d->swptr) {
 758                         printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 759                                d->hwptr, d->swptr);
 760                         spin_unlock_irqrestore(&s->lock, flags);
 761                         return -1;
 762                 }
 763                 swptr = d->swptr;
 764                 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 765                 spin_unlock_irqrestore(&s->lock, flags);
 766
 767                 descr = &d->descrtab[swptr];
 768                 data_p = &d->dma_buf[swptr * 4];
 769                 *data_p = cpu_to_be64(data);
 770                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 771                 CS_DBGOUT(CS_DESCR, 4,
 772                           printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 773                                  data_p, swptr, d->hwptr));
 774         }
 775
 776         CS_DBGOUT(CS_FUNCTION, 6,
 777                   printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 778
 779         return 0;
 780 }
 781
 782 //****************************************************************************
 783 // "cs4297a_read_ac97" -- Reads an AC97 register
 784 //****************************************************************************
 785 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 786                             u32 * value)
 787 {
 788         CS_DBGOUT(CS_AC97, 1,
 789                   printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 790         if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 791                 return -1;
 792
 793         interruptible_sleep_on(&s->dma_adc.reg_wait);
 794         *value = s->read_value;
 795         CS_DBGOUT(CS_AC97, 2,
 796                   printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 797
 798         return 0;
 799 }
 800
 801
 802 //****************************************************************************
 803 // "cs4297a_write_ac97()"-- writes an AC97 register
 804 //****************************************************************************
 805 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 806                              u32 value)
 807 {
 808         CS_DBGOUT(CS_AC97, 1,
 809                   printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 810         return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 811 }
 812
 813 static void stop_dac(struct cs4297a_state *s)
 814 {
 815         unsigned long flags;
 816
 817         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 818         spin_lock_irqsave(&s->lock, flags);
 819         s->ena &= ~FMODE_WRITE;
 820 #if 0
 821         /* XXXKW what do I really want here?  My theory for now is
 822            that I just flip the "ena" bit, and the interrupt handler
 823            will stop processing the xmit channel */
 824         __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 825               SS_CSR(R_SER_DMA_ENABLE));
 826 #endif
 827
 828         spin_unlock_irqrestore(&s->lock, flags);
 829 }
 830
 831
 832 static void start_dac(struct cs4297a_state *s)
 833 {
 834         unsigned long flags;
 835
 836         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 837         spin_lock_irqsave(&s->lock, flags);
 838         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 839                                         (s->dma_dac.count > 0
 840                                         && s->dma_dac.ready))) {
 841                 s->ena |= FMODE_WRITE;
 842                 /* XXXKW what do I really want here?  My theory for
 843                    now is that I just flip the "ena" bit, and the
 844                    interrupt handler will start processing the xmit
 845                    channel */
 846
 847                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 848                         "cs4297a: start_dac(): start dma\n"));
 849
 850         }
 851         spin_unlock_irqrestore(&s->lock, flags);
 852         CS_DBGOUT(CS_FUNCTION, 3,
 853                   printk(KERN_INFO "cs4297a: start_dac()-\n"));
 854 }
 855
 856
 857 static void stop_adc(struct cs4297a_state *s)
 858 {
 859         unsigned long flags;
 860
 861         CS_DBGOUT(CS_FUNCTION, 3,
 862                   printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 863
 864         spin_lock_irqsave(&s->lock, flags);
 865         s->ena &= ~FMODE_READ;
 866
 867         if (s->conversion == 1) {
 868                 s->conversion = 0;
 869                 s->prop_adc.fmt = s->prop_adc.fmt_original;
 870         }
 871         /* Nothing to do really, I need to keep the DMA going
 872            XXXKW when do I get here, and is there more I should do? */
 873         spin_unlock_irqrestore(&s->lock, flags);
 874         CS_DBGOUT(CS_FUNCTION, 3,
 875                   printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 876 }
 877
 878
 879 static void start_adc(struct cs4297a_state *s)
 880 {
 881         unsigned long flags;
 882
 883         CS_DBGOUT(CS_FUNCTION, 2,
 884                   printk(KERN_INFO "cs4297a: start_adc()+\n"));
 885
 886         if (!(s->ena & FMODE_READ) &&
 887             (s->dma_adc.mapped || s->dma_adc.count <=
 888              (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 889             && s->dma_adc.ready) {
 890                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 891                         //
 892                         // now only use 16 bit capture, due to truncation issue
 893                         // in the chip, noticeable distortion occurs.
 894                         // allocate buffer and then convert from 16 bit to
 895                         // 8 bit for the user buffer.
 896                         //
 897                         s->prop_adc.fmt_original = s->prop_adc.fmt;
 898                         if (s->prop_adc.fmt & AFMT_S8) {
 899                                 s->prop_adc.fmt &= ~AFMT_S8;
 900                                 s->prop_adc.fmt |= AFMT_S16_LE;
 901                         }
 902                         if (s->prop_adc.fmt & AFMT_U8) {
 903                                 s->prop_adc.fmt &= ~AFMT_U8;
 904                                 s->prop_adc.fmt |= AFMT_U16_LE;
 905                         }
 906                         //
 907                         // prog_dmabuf_adc performs a stop_adc() but that is
 908                         // ok since we really haven't started the DMA yet.
 909                         //
 910                         prog_codec(s, CS_TYPE_ADC);
 911
 912                         prog_dmabuf_adc(s);
 913                         s->conversion = 1;
 914                 }
 915                 spin_lock_irqsave(&s->lock, flags);
 916                 s->ena |= FMODE_READ;
 917                 /* Nothing to do really, I am probably already
 918                    DMAing...  XXXKW when do I get here, and is there
 919                    more I should do? */
 920                 spin_unlock_irqrestore(&s->lock, flags);
 921
 922                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 923                          "cs4297a: start_adc(): start adc\n"));
 924         }
 925         CS_DBGOUT(CS_FUNCTION, 2,
 926                   printk(KERN_INFO "cs4297a: start_adc()-\n"));
 927
 928 }
 929
 930
 931 // call with spinlock held!
 932 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 933 {
 934         int good_diff, diff, diff2;
 935         u64 *data_p, data;
 936         u32 *s_ptr;
 937         unsigned hwptr;
 938         u32 status;
 939         serdma_t *d;
 940         serdma_descr_t *descr;
 941
 942         // update ADC pointer
 943         status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
 944
 945         if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 946                 d = &s->dma_adc;
 947                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 948                                      d->descrtab_phys) / sizeof(serdma_descr_t));
 949
 950                 if (s->ena & FMODE_READ) {
 951                         CS_DBGOUT(CS_FUNCTION, 2,
 952                                   printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 953                                          d->swptr, d->hwptr, hwptr, intflag));
 954                         /* Number of DMA buffers available for software: */
 955                         diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 956                         d->hwptr = hwptr;
 957                         good_diff = 0;
 958                         s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 959                         descr = &d->descrtab[d->swptr];
 960                         while (diff2--) {
 961                                 u64 data = be64_to_cpu(*(u64 *)s_ptr);
 962                                 u64 descr_a;
 963                                 u16 left, right;
 964                                 descr_a = descr->descr_a;
 965                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
 966                                 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
 967                                         printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 968                                 }
 969                                 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 970                                     (!(descr_a & M_DMA_SERRX_SOP)) ||
 971                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 972                                         s->stats.rx_bad++;
 973                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 974                                         continue;
 975                                 }
 976                                 s->stats.rx_good++;
 977                                 if ((data >> 61) == 7) {
 978                                         s->read_value = (data >> 12) & 0xffff;
 979                                         s->read_reg = (data >> 40) & 0x7f;
 980                                         wake_up(&d->reg_wait);
 981                                 }
 982                                 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 983                                         s->stats.rx_overflow++;
 984                                         printk(KERN_DEBUG "cs4297a: RX overflow\n");
 985                                         continue;
 986                                 }
 987                                 good_diff++;
 988                                 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
 989                                        ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
 990                                 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
 991                                 *d->sb_hwptr++ = cpu_to_be16(left);
 992                                 *d->sb_hwptr++ = cpu_to_be16(right);
 993                                 if (d->sb_hwptr == d->sb_end)
 994                                         d->sb_hwptr = d->sample_buf;
 995                                 descr++;
 996                                 if (descr == d->descrtab_end) {
 997                                         descr = d->descrtab;
 998                                         s_ptr = (u32 *)s->dma_adc.dma_buf;
 999                                 } else {
1000                                         s_ptr += 8;
1001                                 }
1002                         }
1003                         d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
1004                         d->count += good_diff * FRAME_SAMPLE_BYTES;
1005                         if (d->count > d->sbufsz) {
1006                                 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
1007                         }
1008                         d->swptr = (d->swptr + diff) % d->ringsz;
1009                         __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1010                         if (d->mapped) {
1011                                 if (d->count >= (signed) d->fragsize)
1012                                         wake_up(&d->wait);
1013                         } else {
1014                                 if (d->count > 0) {
1015                                         CS_DBGOUT(CS_WAVE_READ, 4,
1016                                                   printk(KERN_INFO
1017                                                          "cs4297a: update count -> %d\n", d->count));
1018                                         wake_up(&d->wait);
1019                                 }
1020                         }
1021                 } else {
1022                         /* Receive is going even if no one is
1023                            listening (for register accesses and to
1024                            avoid FIFO overrun) */
1025                         diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1026                         if (!diff) {
1027                                 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1028                         }
1029
1030                         descr = &d->descrtab[d->swptr];
1031                         data_p = &d->dma_buf[d->swptr*4];
1032
1033                         /* Force this to happen at least once; I got
1034                            here because of an interrupt, so there must
1035                            be a buffer to process. */
1036                         do {
1037                                 data = be64_to_cpu(*data_p);
1038                                 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1039                                         printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1040                                                (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1041                                                (long)CPHYSADDR((long)data_p));
1042                                 }
1043                                 if (!(data & (1LL << 63)) ||
1044                                     !(descr->descr_a & M_DMA_SERRX_SOP) ||
1045                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1046                                         s->stats.rx_bad++;
1047                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1048                                 } else {
1049                                         s->stats.rx_good++;
1050                                         if ((data >> 61) == 7) {
1051                                                 s->read_value = (data >> 12) & 0xffff;
1052                                                 s->read_reg = (data >> 40) & 0x7f;
1053                                                 wake_up(&d->reg_wait);
1054                                         }
1055                                 }
1056                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
1057                                 descr++;
1058                                 d->swptr++;
1059                                 data_p += 4;
1060                                 if (descr == d->descrtab_end) {
1061                                         descr = d->descrtab;
1062                                         d->swptr = 0;
1063                                         data_p = d->dma_buf;
1064                                 }
1065                                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1066                         } while (--diff);
1067                         d->hwptr = hwptr;
1068
1069                         CS_DBGOUT(CS_DESCR, 6,
1070                                   printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1071                 }
1072
1073                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1074                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1075                                 (unsigned)s, d->hwptr,
1076                                 d->total_bytes, d->count));
1077         }
1078
1079         /* XXXKW worry about s->reg_request -- there is a starvation
1080            case if s->ena has FMODE_WRITE on, but the client isn't
1081            doing writes */
1082
1083         // update DAC pointer
1084         //
1085         // check for end of buffer, means that we are going to wait for another interrupt
1086         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1087         //
1088         if (s->ena & FMODE_WRITE) {
1089                 serdma_t *d = &s->dma_dac;
1090                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1091                                      d->descrtab_phys) / sizeof(serdma_descr_t));
1092                 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1093                 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1094                                                    "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1095                                                    d->hwptr, hwptr, d->swptr, diff, d->count));
1096                 d->hwptr = hwptr;
1097                 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1098                 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1099                 if (d->mapped) {
1100                         d->count += diff * FRAME_SAMPLE_BYTES;
1101                         if (d->count >= d->fragsize) {
1102                                 d->wakeup = 1;
1103                                 wake_up(&d->wait);
1104                                 if (d->count > d->sbufsz)
1105                                         d->count &= d->sbufsz - 1;
1106                         }
1107                 } else {
1108                         d->count -= diff * FRAME_SAMPLE_BYTES;
1109                         if (d->count <= 0) {
1110                                 //
1111                                 // fill with silence, and do not shut down the DAC.
1112                                 // Continue to play silence until the _release.
1113                                 //
1114                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1115                                         "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1116                                                 (unsigned)(s->prop_dac.fmt &
1117                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1118                                                 (unsigned)d->dma_buf,
1119                                                 d->ringsz));
1120                                 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1121                                 if (d->count < 0) {
1122                                         d->underrun = 1;
1123                                         s->stats.tx_underrun++;
1124                                         d->count = 0;
1125                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1126                                          "cs4297a: cs4297a_update_ptr(): underrun\n"));
1127                                 }
1128                         } else if (d->count <=
1129                                    (signed) d->fragsize
1130                                    && !d->endcleared) {
1131                           /* XXXKW what is this for? */
1132                                 clear_advance(d->dma_buf,
1133                                               d->sbufsz,
1134                                               d->swptr,
1135                                               d->fragsize,
1136                                               0);
1137                                 d->endcleared = 1;
1138                         }
1139                         if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1140                         {
1141                                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1142                                           printk(KERN_INFO
1143                                                  "cs4297a: update count -> %d\n", d->count));
1144                                 wake_up(&d->wait);
1145                         }
1146                 }
1147                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1148                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1149                                 (unsigned) s, d->hwptr,
1150                                 d->total_bytes, d->count));
1151         }
1152 }
1153
1154 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1155                        unsigned long arg)
1156 {
1157         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1158         // Value of array member is recording source Device ID Mask.
1159         static const unsigned int mixer_src[8] = {
1160                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1161                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1162         };
1163
1164         // Index of mixtable1[] member is Device ID
1165         // and must be <= SOUND_MIXER_NRDEVICES.
1166         // Value of array member is index into s->mix.vol[]
1167         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1168                 [SOUND_MIXER_PCM] = 1,  // voice
1169                 [SOUND_MIXER_LINE1] = 2,        // AUX
1170                 [SOUND_MIXER_CD] = 3,   // CD
1171                 [SOUND_MIXER_LINE] = 4, // Line
1172                 [SOUND_MIXER_SYNTH] = 5,        // FM
1173                 [SOUND_MIXER_MIC] = 6,  // Mic
1174                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
1175                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
1176                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
1177         };
1178
1179         static const unsigned mixreg[] = {
1180                 AC97_PCMOUT_VOL,
1181                 AC97_AUX_VOL,
1182                 AC97_CD_VOL,
1183                 AC97_LINEIN_VOL
1184         };
1185         unsigned char l, r, rl, rr, vidx;
1186         unsigned char attentbl[11] =
1187             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1188         unsigned temp1;
1189         int i, val;
1190
1191         VALIDATE_STATE(s);
1192         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1193                  "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1194                          (unsigned) s, cmd));
1195 #if CSDEBUG
1196         cs_printioctl(cmd);
1197 #endif
1198 #if CSDEBUG_INTERFACE
1199
1200         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1201             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1202             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1203             (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1204         {
1205                 switch (cmd) {
1206
1207                 case SOUND_MIXER_CS_GETDBGMASK:
1208                         return put_user(cs_debugmask,
1209                                         (unsigned long *) arg);
1210
1211                 case SOUND_MIXER_CS_GETDBGLEVEL:
1212                         return put_user(cs_debuglevel,
1213                                         (unsigned long *) arg);
1214
1215                 case SOUND_MIXER_CS_SETDBGMASK:
1216                         if (get_user(val, (unsigned long *) arg))
1217                                 return -EFAULT;
1218                         cs_debugmask = val;
1219                         return 0;
1220
1221                 case SOUND_MIXER_CS_SETDBGLEVEL:
1222                         if (get_user(val, (unsigned long *) arg))
1223                                 return -EFAULT;
1224                         cs_debuglevel = val;
1225                         return 0;
1226                 default:
1227                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1228                                 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1229                         return 0;
1230                 }
1231         }
1232 #endif
1233
1234         if (cmd == SOUND_MIXER_PRIVATE1) {
1235                 return -EINVAL;
1236         }
1237         if (cmd == SOUND_MIXER_PRIVATE2) {
1238                 // enable/disable/query spatializer
1239                 if (get_user(val, (int *) arg))
1240                         return -EFAULT;
1241                 if (val != -1) {
1242                         temp1 = (val & 0x3f) >> 2;
1243                         cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1244                         cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1245                                          &temp1);
1246                         cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1247                                           temp1 | 0x2000);
1248                 }
1249                 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1250                 return put_user((temp1 << 2) | 3, (int *) arg);
1251         }
1252         if (cmd == SOUND_MIXER_INFO) {
1253                 mixer_info info;
1254                 memset(&info, 0, sizeof(info));
1255                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1256                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1257                 info.modify_counter = s->mix.modcnt;
1258                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1259                         return -EFAULT;
1260                 return 0;
1261         }
1262         if (cmd == SOUND_OLD_MIXER_INFO) {
1263                 _old_mixer_info info;
1264                 memset(&info, 0, sizeof(info));
1265                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1266                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1267                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1268                         return -EFAULT;
1269                 return 0;
1270         }
1271         if (cmd == OSS_GETVERSION)
1272                 return put_user(SOUND_VERSION, (int *) arg);
1273
1274         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1275                 return -EINVAL;
1276
1277         // If ioctl has only the SIOC_READ bit(bit 31)
1278         // on, process the only-read commands.
1279         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1280                 switch (_IOC_NR(cmd)) {
1281                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1282                         cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1283                                          &temp1);
1284                         return put_user(mixer_src[temp1 & 7], (int *) arg);
1285
1286                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
1287                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1288                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1289                                         (int *) arg);
1290
1291                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
1292                         return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1293                                         (int *) arg);
1294
1295                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
1296                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1297                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1298                                         (int *) arg);
1299
1300                 case SOUND_MIXER_CAPS:
1301                         return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1302
1303                 default:
1304                         i = _IOC_NR(cmd);
1305                         if (i >= SOUND_MIXER_NRDEVICES
1306                             || !(vidx = mixtable1[i]))
1307                                 return -EINVAL;
1308                         return put_user(s->mix.vol[vidx - 1], (int *) arg);
1309                 }
1310         }
1311         // If ioctl doesn't have both the SIOC_READ and
1312         // the SIOC_WRITE bit set, return invalid.
1313         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1314                 return -EINVAL;
1315
1316         // Increment the count of volume writes.
1317         s->mix.modcnt++;
1318
1319         // Isolate the command; it must be a write.
1320         switch (_IOC_NR(cmd)) {
1321
1322         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1323                 if (get_user(val, (int *) arg))
1324                         return -EFAULT;
1325                 i = hweight32(val);     // i = # bits on in val.
1326                 if (i != 1)     // One & only 1 bit must be on.
1327                         return 0;
1328                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1329                         if (val == mixer_src[i]) {
1330                                 temp1 = (i << 8) | i;
1331                                 cs4297a_write_ac97(s,
1332                                                   AC97_RECORD_SELECT,
1333                                                   temp1);
1334                                 return 0;
1335                         }
1336                 }
1337                 return 0;
1338
1339         case SOUND_MIXER_VOLUME:
1340                 if (get_user(val, (int *) arg))
1341                         return -EFAULT;
1342                 l = val & 0xff;
1343                 if (l > 100)
1344                         l = 100;        // Max soundcard.h vol is 100.
1345                 if (l < 6) {
1346                         rl = 63;
1347                         l = 0;
1348                 } else
1349                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1350
1351                 r = (val >> 8) & 0xff;
1352                 if (r > 100)
1353                         r = 100;        // Max right volume is 100, too
1354                 if (r < 6) {
1355                         rr = 63;
1356                         r = 0;
1357                 } else
1358                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1359
1360                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
1361                         temp1 = 0x8000; //  turn on the mute bit.
1362                 else
1363                         temp1 = 0;
1364
1365                 temp1 |= (rl << 8) | rr;
1366
1367                 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1368                 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1369
1370 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1371                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1372 #else
1373                 s->mix.vol[8] = val;
1374 #endif
1375                 return put_user(s->mix.vol[8], (int *) arg);
1376
1377         case SOUND_MIXER_SPEAKER:
1378                 if (get_user(val, (int *) arg))
1379                         return -EFAULT;
1380                 l = val & 0xff;
1381                 if (l > 100)
1382                         l = 100;
1383                 if (l < 3) {
1384                         rl = 0;
1385                         l = 0;
1386                 } else {
1387                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1388                         l = (rl * 13 + 5) / 2;
1389                 }
1390
1391                 if (rl < 3) {
1392                         temp1 = 0x8000;
1393                         rl = 0;
1394                 } else
1395                         temp1 = 0;
1396                 rl = 15 - rl;   // Convert volume to attenuation.
1397                 temp1 |= rl << 1;
1398                 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1399
1400 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1401                 s->mix.vol[6] = l << 8;
1402 #else
1403                 s->mix.vol[6] = val;
1404 #endif
1405                 return put_user(s->mix.vol[6], (int *) arg);
1406
1407         case SOUND_MIXER_RECLEV:
1408                 if (get_user(val, (int *) arg))
1409                         return -EFAULT;
1410                 l = val & 0xff;
1411                 if (l > 100)
1412                         l = 100;
1413                 r = (val >> 8) & 0xff;
1414                 if (r > 100)
1415                         r = 100;
1416                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1417                 rr = (r * 2 - 5) / 13;
1418                 if (rl < 3 && rr < 3)
1419                         temp1 = 0x8000;
1420                 else
1421                         temp1 = 0;
1422
1423                 temp1 = temp1 | (rl << 8) | rr;
1424                 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1425
1426 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1427                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1428 #else
1429                 s->mix.vol[7] = val;
1430 #endif
1431                 return put_user(s->mix.vol[7], (int *) arg);
1432
1433         case SOUND_MIXER_MIC:
1434                 if (get_user(val, (int *) arg))
1435                         return -EFAULT;
1436                 l = val & 0xff;
1437                 if (l > 100)
1438                         l = 100;
1439                 if (l < 1) {
1440                         l = 0;
1441                         rl = 0;
1442                 } else {
1443                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1444                         l = (rl * 16 + 4) / 5;
1445                 }
1446                 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1447                 temp1 &= 0x40;  // Isolate 20db gain bit.
1448                 if (rl < 3) {
1449                         temp1 |= 0x8000;
1450                         rl = 0;
1451                 }
1452                 rl = 31 - rl;   // Convert volume to attenuation.
1453                 temp1 |= rl;
1454                 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1455
1456 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1457                 s->mix.vol[5] = val << 8;
1458 #else
1459                 s->mix.vol[5] = val;
1460 #endif
1461                 return put_user(s->mix.vol[5], (int *) arg);
1462
1463
1464         case SOUND_MIXER_SYNTH:
1465                 if (get_user(val, (int *) arg))
1466                         return -EFAULT;
1467                 l = val & 0xff;
1468                 if (l > 100)
1469                         l = 100;
1470                 if (get_user(val, (int *) arg))
1471                         return -EFAULT;
1472                 r = (val >> 8) & 0xff;
1473                 if (r > 100)
1474                         r = 100;
1475                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1476                 rr = (r * 2 - 11) / 3;
1477                 if (rl < 3)     // If l is low, turn on
1478                         temp1 = 0x0080; //  the mute bit.
1479                 else
1480                         temp1 = 0;
1481
1482                 rl = 63 - rl;   // Convert vol to attenuation.
1483 //              writel(temp1 | rl, s->pBA0 + FMLVC);
1484                 if (rr < 3)     //  If rr is low, turn on
1485                         temp1 = 0x0080; //   the mute bit.
1486                 else
1487                         temp1 = 0;
1488                 rr = 63 - rr;   // Convert vol to attenuation.
1489 //              writel(temp1 | rr, s->pBA0 + FMRVC);
1490
1491 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1492                 s->mix.vol[4] = (r << 8) | l;
1493 #else
1494                 s->mix.vol[4] = val;
1495 #endif
1496                 return put_user(s->mix.vol[4], (int *) arg);
1497
1498
1499         default:
1500                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1501                         "cs4297a: mixer_ioctl(): default\n"));
1502
1503                 i = _IOC_NR(cmd);
1504                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1505                         return -EINVAL;
1506                 if (get_user(val, (int *) arg))
1507                         return -EFAULT;
1508                 l = val & 0xff;
1509                 if (l > 100)
1510                         l = 100;
1511                 if (l < 1) {
1512                         l = 0;
1513                         rl = 31;
1514                 } else
1515                         rl = (attentbl[(l * 10) / 100]) >> 1;
1516
1517                 r = (val >> 8) & 0xff;
1518                 if (r > 100)
1519                         r = 100;
1520                 if (r < 1) {
1521                         r = 0;
1522                         rr = 31;
1523                 } else
1524                         rr = (attentbl[(r * 10) / 100]) >> 1;
1525                 if ((rl > 30) && (rr > 30))
1526                         temp1 = 0x8000;
1527                 else
1528                         temp1 = 0;
1529                 temp1 = temp1 | (rl << 8) | rr;
1530                 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1531
1532 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1533                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1534 #else
1535                 s->mix.vol[vidx - 1] = val;
1536 #endif
1537                 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1538         }
1539 }
1540
1541
1542 // ---------------------------------------------------------------------
1543
1544 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1545 {
1546         int minor = iminor(inode);
1547         struct cs4297a_state *s=NULL;
1548         struct list_head *entry;
1549
1550         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1551                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1552
1553         mutex_lock(&swarm_cs4297a_mutex);
1554         list_for_each(entry, &cs4297a_devs)
1555         {
1556                 s = list_entry(entry, struct cs4297a_state, list);
1557                 if(s->dev_mixer == minor)
1558                         break;
1559         }
1560         if (!s)
1561         {
1562                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1563                         printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1564
1565                 mutex_unlock(&swarm_cs4297a_mutex);
1566                 return -ENODEV;
1567         }
1568         VALIDATE_STATE(s);
1569         file->private_data = s;
1570
1571         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1572                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1573         mutex_unlock(&swarm_cs4297a_mutex);
1574
1575         return nonseekable_open(inode, file);
1576 }
1577
1578
1579 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1580 {
1581         struct cs4297a_state *s =
1582             (struct cs4297a_state *) file->private_data;
1583
1584         VALIDATE_STATE(s);
1585         return 0;
1586 }
1587
1588
1589 static int cs4297a_ioctl_mixdev(struct file *file,
1590                                unsigned int cmd, unsigned long arg)
1591 {
1592         int ret;
1593         mutex_lock(&swarm_cs4297a_mutex);
1594         ret = mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1595                            arg);
1596         mutex_unlock(&swarm_cs4297a_mutex);
1597         return ret;
1598 }
1599
1600
1601 // ******************************************************************************************
1602 //   Mixer file operations struct.
1603 // ******************************************************************************************
1604 static const struct file_operations cs4297a_mixer_fops = {
1605         .owner          = THIS_MODULE,
1606         .llseek         = no_llseek,
1607         .unlocked_ioctl = cs4297a_ioctl_mixdev,
1608         .open           = cs4297a_open_mixdev,
1609         .release        = cs4297a_release_mixdev,
1610 };
1611
1612 // ---------------------------------------------------------------------
1613
1614
1615 static int drain_adc(struct cs4297a_state *s, int nonblock)
1616 {
1617         /* This routine serves no purpose currently - any samples
1618            sitting in the receive queue will just be processed by the
1619            background consumer.  This would be different if DMA
1620            actually stopped when there were no clients. */
1621         return 0;
1622 }
1623
1624 static int drain_dac(struct cs4297a_state *s, int nonblock)
1625 {
1626         DECLARE_WAITQUEUE(wait, current);
1627         unsigned long flags;
1628         unsigned hwptr;
1629         unsigned tmo;
1630         int count;
1631
1632         if (s->dma_dac.mapped)
1633                 return 0;
1634         if (nonblock)
1635                 return -EBUSY;
1636         add_wait_queue(&s->dma_dac.wait, &wait);
1637         while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1638                (s->dma_dac.count > 0)) {
1639                 if (!signal_pending(current)) {
1640                         set_current_state(TASK_INTERRUPTIBLE);
1641                         /* XXXKW is this calculation working? */
1642                         tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1643                         schedule_timeout(tmo + 1);
1644                 } else {
1645                         /* XXXKW do I care if there is a signal pending? */
1646                 }
1647         }
1648         spin_lock_irqsave(&s->lock, flags);
1649         /* Reset the bookkeeping */
1650         hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1651                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1652         s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1653         spin_unlock_irqrestore(&s->lock, flags);
1654         remove_wait_queue(&s->dma_dac.wait, &wait);
1655         current->state = TASK_RUNNING;
1656         return 0;
1657 }
1658
1659
1660 // ---------------------------------------------------------------------
1661
1662 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1663                            loff_t * ppos)
1664 {
1665         struct cs4297a_state *s =
1666             (struct cs4297a_state *) file->private_data;
1667         ssize_t ret;
1668         unsigned long flags;
1669         int cnt, count_fr, cnt_by;
1670         unsigned copied = 0;
1671
1672         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1673                   printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1674
1675         VALIDATE_STATE(s);
1676         if (s->dma_adc.mapped)
1677                 return -ENXIO;
1678         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1679                 return ret;
1680         if (!access_ok(VERIFY_WRITE, buffer, count))
1681                 return -EFAULT;
1682         ret = 0;
1683 //
1684 // "count" is the amount of bytes to read (from app), is decremented each loop
1685 //      by the amount of bytes that have been returned to the user buffer.
1686 // "cnt" is the running total of each read from the buffer (changes each loop)
1687 // "buffer" points to the app's buffer
1688 // "ret" keeps a running total of the amount of bytes that have been copied
1689 //      to the user buffer.
1690 // "copied" is the total bytes copied into the user buffer for each loop.
1691 //
1692         while (count > 0) {
1693                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1694                         "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1695                                 count, s->dma_adc.count,
1696                                 s->dma_adc.swptr, s->dma_adc.hwptr));
1697                 spin_lock_irqsave(&s->lock, flags);
1698
1699                 /* cnt will be the number of available samples (16-bit
1700                    stereo); it starts out as the maxmimum consequetive
1701                    samples */
1702                 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1703                 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1704
1705                 // dma_adc.count is the current total bytes that have not been read.
1706                 // if the amount of unread bytes from the current sw pointer to the
1707                 // end of the buffer is greater than the current total bytes that
1708                 // have not been read, then set the "cnt" (unread bytes) to the
1709                 // amount of unread bytes.
1710
1711                 if (count_fr < cnt)
1712                         cnt = count_fr;
1713                 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1714                 spin_unlock_irqrestore(&s->lock, flags);
1715                 //
1716                 // if we are converting from 8/16 then we need to copy
1717                 // twice the number of 16 bit bytes then 8 bit bytes.
1718                 //
1719                 if (s->conversion) {
1720                         if (cnt_by > (count * 2)) {
1721                                 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1722                                 cnt_by = count * 2;
1723                         }
1724                 } else {
1725                         if (cnt_by > count) {
1726                                 cnt = count / FRAME_SAMPLE_BYTES;
1727                                 cnt_by = count;
1728                         }
1729                 }
1730                 //
1731                 // "cnt" NOW is the smaller of the amount that will be read,
1732                 // and the amount that is requested in this read (or partial).
1733                 // if there are no bytes in the buffer to read, then start the
1734                 // ADC and wait for the interrupt handler to wake us up.
1735                 //
1736                 if (cnt <= 0) {
1737
1738                         // start up the dma engine and then continue back to the top of
1739                         // the loop when wake up occurs.
1740                         start_adc(s);
1741                         if (file->f_flags & O_NONBLOCK)
1742                                 return ret ? ret : -EAGAIN;
1743                         interruptible_sleep_on(&s->dma_adc.wait);
1744                         if (signal_pending(current))
1745                                 return ret ? ret : -ERESTARTSYS;
1746                         continue;
1747                 }
1748                 // there are bytes in the buffer to read.
1749                 // copy from the hw buffer over to the user buffer.
1750                 // user buffer is designated by "buffer"
1751                 // virtual address to copy from is dma_buf+swptr
1752                 // the "cnt" is the number of bytes to read.
1753
1754                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1755                         "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1756                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1757                          " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1758                                  s->dma_adc.sbufsz, s->dma_adc.count,
1759                                  (unsigned) buffer, ret));
1760
1761                 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1762                         return ret ? ret : -EFAULT;
1763                 copied = cnt_by;
1764
1765                 /* Return the descriptors */
1766                 spin_lock_irqsave(&s->lock, flags);
1767                 CS_DBGOUT(CS_FUNCTION, 2,
1768                           printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1769                 s->dma_adc.count -= cnt_by;
1770                 s->dma_adc.sb_swptr += cnt * 2;
1771                 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1772                         s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1773                 spin_unlock_irqrestore(&s->lock, flags);
1774                 count -= copied;
1775                 buffer += copied;
1776                 ret += copied;
1777                 start_adc(s);
1778         }
1779         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1780                   printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1781         return ret;
1782 }
1783
1784
1785 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1786                             size_t count, loff_t * ppos)
1787 {
1788         struct cs4297a_state *s =
1789             (struct cs4297a_state *) file->private_data;
1790         ssize_t ret;
1791         unsigned long flags;
1792         unsigned swptr, hwptr;
1793         int cnt;
1794
1795         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1796                   printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1797                          count));
1798         VALIDATE_STATE(s);
1799
1800         if (s->dma_dac.mapped)
1801                 return -ENXIO;
1802         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1803                 return ret;
1804         if (!access_ok(VERIFY_READ, buffer, count))
1805                 return -EFAULT;
1806         ret = 0;
1807         while (count > 0) {
1808                 serdma_t *d = &s->dma_dac;
1809                 int copy_cnt;
1810                 u32 *s_tmpl;
1811                 u32 *t_tmpl;
1812                 u32 left, right;
1813                 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1814
1815                 /* XXXXXX this is broken for BLOAT_FACTOR */
1816                 spin_lock_irqsave(&s->lock, flags);
1817                 if (d->count < 0) {
1818                         d->count = 0;
1819                         d->swptr = d->hwptr;
1820                 }
1821                 if (d->underrun) {
1822                         d->underrun = 0;
1823                         hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1824                                              d->descrtab_phys) / sizeof(serdma_descr_t));
1825                         d->swptr = d->hwptr = hwptr;
1826                 }
1827                 swptr = d->swptr;
1828                 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1829                 /* Will this write fill up the buffer? */
1830                 if (d->count + cnt > d->sbufsz)
1831                         cnt = d->sbufsz - d->count;
1832                 spin_unlock_irqrestore(&s->lock, flags);
1833                 if (cnt > count)
1834                         cnt = count;
1835                 if (cnt <= 0) {
1836                         start_dac(s);
1837                         if (file->f_flags & O_NONBLOCK)
1838                                 return ret ? ret : -EAGAIN;
1839                         interruptible_sleep_on(&d->wait);
1840                         if (signal_pending(current))
1841                                 return ret ? ret : -ERESTARTSYS;
1842                         continue;
1843                 }
1844                 if (copy_from_user(d->sample_buf, buffer, cnt))
1845                         return ret ? ret : -EFAULT;
1846
1847                 copy_cnt = cnt;
1848                 s_tmpl = (u32 *)d->sample_buf;
1849                 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1850
1851                 /* XXXKW assuming 16-bit stereo! */
1852                 do {
1853                         u32 tmp;
1854
1855                         t_tmpl[0] = cpu_to_be32(0x98000000);
1856
1857                         tmp = be32_to_cpu(s_tmpl[0]);
1858                         left = tmp & 0xffff;
1859                         right = tmp >> 16;
1860                         if (swap) {
1861                                 left = swab16(left);
1862                                 right = swab16(right);
1863                         }
1864                         t_tmpl[1] = cpu_to_be32(left >> 8);
1865                         t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1866                                                 (right << 4));
1867
1868                         s_tmpl++;
1869                         t_tmpl += 8;
1870                         copy_cnt -= 4;
1871                 } while (copy_cnt);
1872
1873                 /* Mux in any pending read/write accesses */
1874                 if (s->reg_request) {
1875                         *(u64 *)(d->dma_buf + (swptr * 4)) |=
1876                                 cpu_to_be64(s->reg_request);
1877                         s->reg_request = 0;
1878                         wake_up(&s->dma_dac.reg_wait);
1879                 }
1880
1881                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1882                           printk(KERN_INFO
1883                                  "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1884
1885                 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1886                 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1887                 spin_lock_irqsave(&s->lock, flags);
1888                 d->swptr = swptr;
1889                 d->count += cnt;
1890                 d->endcleared = 0;
1891                 spin_unlock_irqrestore(&s->lock, flags);
1892                 count -= cnt;
1893                 buffer += cnt;
1894                 ret += cnt;
1895                 start_dac(s);
1896         }
1897         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1898                   printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1899         return ret;
1900 }
1901
1902
1903 static unsigned int cs4297a_poll(struct file *file,
1904                                 struct poll_table_struct *wait)
1905 {
1906         struct cs4297a_state *s =
1907             (struct cs4297a_state *) file->private_data;
1908         unsigned long flags;
1909         unsigned int mask = 0;
1910
1911         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1912                   printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1913         VALIDATE_STATE(s);
1914         if (file->f_mode & FMODE_WRITE) {
1915                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1916                           printk(KERN_INFO
1917                                  "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1918                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1919                         return 0;
1920                 poll_wait(file, &s->dma_dac.wait, wait);
1921         }
1922         if (file->f_mode & FMODE_READ) {
1923                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1924                           printk(KERN_INFO
1925                                  "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1926                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1927                         return 0;
1928                 poll_wait(file, &s->dma_adc.wait, wait);
1929         }
1930         spin_lock_irqsave(&s->lock, flags);
1931         cs4297a_update_ptr(s,CS_FALSE);
1932         if (file->f_mode & FMODE_WRITE) {
1933                 if (s->dma_dac.mapped) {
1934                         if (s->dma_dac.count >=
1935                             (signed) s->dma_dac.fragsize) {
1936                                 if (s->dma_dac.wakeup)
1937                                         mask |= POLLOUT | POLLWRNORM;
1938                                 else
1939                                         mask = 0;
1940                                 s->dma_dac.wakeup = 0;
1941                         }
1942                 } else {
1943                         if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1944                                 mask |= POLLOUT | POLLWRNORM;
1945                 }
1946         } else if (file->f_mode & FMODE_READ) {
1947                 if (s->dma_adc.mapped) {
1948                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1949                                 mask |= POLLIN | POLLRDNORM;
1950                 } else {
1951                         if (s->dma_adc.count > 0)
1952                                 mask |= POLLIN | POLLRDNORM;
1953                 }
1954         }
1955         spin_unlock_irqrestore(&s->lock, flags);
1956         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1957                   printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1958                          mask));
1959         return mask;
1960 }
1961
1962
1963 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1964 {
1965         /* XXXKW currently no mmap support */
1966         return -EINVAL;
1967         return 0;
1968 }
1969
1970
1971 static int cs4297a_ioctl(struct file *file,
1972                         unsigned int cmd, unsigned long arg)
1973 {
1974         struct cs4297a_state *s =
1975             (struct cs4297a_state *) file->private_data;
1976         unsigned long flags;
1977         audio_buf_info abinfo;
1978         count_info cinfo;
1979         int val, mapped, ret;
1980
1981         CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1982                  "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1983                          (unsigned) file, cmd));
1984 #if CSDEBUG
1985         cs_printioctl(cmd);
1986 #endif
1987         VALIDATE_STATE(s);
1988         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1989             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1990         switch (cmd) {
1991         case OSS_GETVERSION:
1992                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1993                         "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1994                                  SOUND_VERSION));
1995                 return put_user(SOUND_VERSION, (int *) arg);
1996
1997         case SNDCTL_DSP_SYNC:
1998                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1999                          "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
2000                 if (file->f_mode & FMODE_WRITE)
2001                         return drain_dac(s,
2002                                          0 /*file->f_flags & O_NONBLOCK */
2003                                          );
2004                 return 0;
2005
2006         case SNDCTL_DSP_SETDUPLEX:
2007                 return 0;
2008
2009         case SNDCTL_DSP_GETCAPS:
2010                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2011                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2012                                 (int *) arg);
2013
2014         case SNDCTL_DSP_RESET:
2015                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2016                          "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
2017                 if (file->f_mode & FMODE_WRITE) {
2018                         stop_dac(s);
2019                         synchronize_irq(s->irq);
2020                         s->dma_dac.count = s->dma_dac.total_bytes =
2021                                 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2022                         s->dma_dac.swptr = s->dma_dac.hwptr =
2023                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2024                                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2025                 }
2026                 if (file->f_mode & FMODE_READ) {
2027                         stop_adc(s);
2028                         synchronize_irq(s->irq);
2029                         s->dma_adc.count = s->dma_adc.total_bytes =
2030                                 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2031                         s->dma_adc.swptr = s->dma_adc.hwptr =
2032                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2033                                        s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2034                 }
2035                 return 0;
2036
2037         case SNDCTL_DSP_SPEED:
2038                 if (get_user(val, (int *) arg))
2039                         return -EFAULT;
2040                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2041                          "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2042                 val = 48000;
2043                 return put_user(val, (int *) arg);
2044
2045         case SNDCTL_DSP_STEREO:
2046                 if (get_user(val, (int *) arg))
2047                         return -EFAULT;
2048                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2049                          "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2050                 if (file->f_mode & FMODE_READ) {
2051                         stop_adc(s);
2052                         s->dma_adc.ready = 0;
2053                         s->prop_adc.channels = val ? 2 : 1;
2054                 }
2055                 if (file->f_mode & FMODE_WRITE) {
2056                         stop_dac(s);
2057                         s->dma_dac.ready = 0;
2058                         s->prop_dac.channels = val ? 2 : 1;
2059                 }
2060                 return 0;
2061
2062         case SNDCTL_DSP_CHANNELS:
2063                 if (get_user(val, (int *) arg))
2064                         return -EFAULT;
2065                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2066                          "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2067                                  val));
2068                 if (val != 0) {
2069                         if (file->f_mode & FMODE_READ) {
2070                                 stop_adc(s);
2071                                 s->dma_adc.ready = 0;
2072                                 if (val >= 2)
2073                                         s->prop_adc.channels = 2;
2074                                 else
2075                                         s->prop_adc.channels = 1;
2076                         }
2077                         if (file->f_mode & FMODE_WRITE) {
2078                                 stop_dac(s);
2079                                 s->dma_dac.ready = 0;
2080                                 if (val >= 2)
2081                                         s->prop_dac.channels = 2;
2082                                 else
2083                                         s->prop_dac.channels = 1;
2084                         }
2085                 }
2086
2087                 if (file->f_mode & FMODE_WRITE)
2088                         val = s->prop_dac.channels;
2089                 else if (file->f_mode & FMODE_READ)
2090                         val = s->prop_adc.channels;
2091
2092                 return put_user(val, (int *) arg);
2093
2094         case SNDCTL_DSP_GETFMTS:        // Returns a mask
2095                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2096                         "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2097                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2098                                  AFMT_U8));
2099                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2100                                 AFMT_U8, (int *) arg);
2101
2102         case SNDCTL_DSP_SETFMT:
2103                 if (get_user(val, (int *) arg))
2104                         return -EFAULT;
2105                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2106                          "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2107                                  val));
2108                 if (val != AFMT_QUERY) {
2109                         if (file->f_mode & FMODE_READ) {
2110                                 stop_adc(s);
2111                                 s->dma_adc.ready = 0;
2112                                 if (val != AFMT_S16_LE
2113                                     && val != AFMT_U16_LE && val != AFMT_S8
2114                                     && val != AFMT_U8)
2115                                         val = AFMT_U8;
2116                                 s->prop_adc.fmt = val;
2117                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2118                         }
2119                         if (file->f_mode & FMODE_WRITE) {
2120                                 stop_dac(s);
2121                                 s->dma_dac.ready = 0;
2122                                 if (val != AFMT_S16_LE
2123                                     && val != AFMT_U16_LE && val != AFMT_S8
2124                                     && val != AFMT_U8)
2125                                         val = AFMT_U8;
2126                                 s->prop_dac.fmt = val;
2127                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2128                         }
2129                 } else {
2130                         if (file->f_mode & FMODE_WRITE)
2131                                 val = s->prop_dac.fmt_original;
2132                         else if (file->f_mode & FMODE_READ)
2133                                 val = s->prop_adc.fmt_original;
2134                 }
2135                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2136                   "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2137                         val));
2138                 return put_user(val, (int *) arg);
2139
2140         case SNDCTL_DSP_POST:
2141                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2142                          "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2143                 return 0;
2144
2145         case SNDCTL_DSP_GETTRIGGER:
2146                 val = 0;
2147                 if (file->f_mode & s->ena & FMODE_READ)
2148                         val |= PCM_ENABLE_INPUT;
2149                 if (file->f_mode & s->ena & FMODE_WRITE)
2150                         val |= PCM_ENABLE_OUTPUT;
2151                 return put_user(val, (int *) arg);
2152
2153         case SNDCTL_DSP_SETTRIGGER:
2154                 if (get_user(val, (int *) arg))
2155                         return -EFAULT;
2156                 if (file->f_mode & FMODE_READ) {
2157                         if (val & PCM_ENABLE_INPUT) {
2158                                 if (!s->dma_adc.ready
2159                                     && (ret = prog_dmabuf_adc(s)))
2160                                         return ret;
2161                                 start_adc(s);
2162                         } else
2163                                 stop_adc(s);
2164                 }
2165                 if (file->f_mode & FMODE_WRITE) {
2166                         if (val & PCM_ENABLE_OUTPUT) {
2167                                 if (!s->dma_dac.ready
2168                                     && (ret = prog_dmabuf_dac(s)))
2169                                         return ret;
2170                                 start_dac(s);
2171                         } else
2172                                 stop_dac(s);
2173                 }
2174                 return 0;
2175
2176         case SNDCTL_DSP_GETOSPACE:
2177                 if (!(file->f_mode & FMODE_WRITE))
2178                         return -EINVAL;
2179                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2180                         return val;
2181                 spin_lock_irqsave(&s->lock, flags);
2182                 cs4297a_update_ptr(s,CS_FALSE);
2183                 abinfo.fragsize = s->dma_dac.fragsize;
2184                 if (s->dma_dac.mapped)
2185                         abinfo.bytes = s->dma_dac.sbufsz;
2186                 else
2187                         abinfo.bytes =
2188                             s->dma_dac.sbufsz - s->dma_dac.count;
2189                 abinfo.fragstotal = s->dma_dac.numfrag;
2190                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2191                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2192                         "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2193                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2194                                 abinfo.fragments));
2195                 spin_unlock_irqrestore(&s->lock, flags);
2196                 return copy_to_user((void *) arg, &abinfo,
2197                                     sizeof(abinfo)) ? -EFAULT : 0;
2198
2199         case SNDCTL_DSP_GETISPACE:
2200                 if (!(file->f_mode & FMODE_READ))
2201                         return -EINVAL;
2202                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2203                         return val;
2204                 spin_lock_irqsave(&s->lock, flags);
2205                 cs4297a_update_ptr(s,CS_FALSE);
2206                 if (s->conversion) {
2207                         abinfo.fragsize = s->dma_adc.fragsize / 2;
2208                         abinfo.bytes = s->dma_adc.count / 2;
2209                         abinfo.fragstotal = s->dma_adc.numfrag;
2210                         abinfo.fragments =
2211                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
2212                 } else {
2213                         abinfo.fragsize = s->dma_adc.fragsize;
2214                         abinfo.bytes = s->dma_adc.count;
2215                         abinfo.fragstotal = s->dma_adc.numfrag;
2216                         abinfo.fragments =
2217                             abinfo.bytes >> s->dma_adc.fragshift;
2218                 }
2219                 spin_unlock_irqrestore(&s->lock, flags);
2220                 return copy_to_user((void *) arg, &abinfo,
2221                                     sizeof(abinfo)) ? -EFAULT : 0;
2222
2223         case SNDCTL_DSP_NONBLOCK:
2224                 spin_lock(&file->f_lock);
2225                 file->f_flags |= O_NONBLOCK;
2226                 spin_unlock(&file->f_lock);
2227                 return 0;
2228
2229         case SNDCTL_DSP_GETODELAY:
2230                 if (!(file->f_mode & FMODE_WRITE))
2231                         return -EINVAL;
2232                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2233                         return 0;
2234                 spin_lock_irqsave(&s->lock, flags);
2235                 cs4297a_update_ptr(s,CS_FALSE);
2236                 val = s->dma_dac.count;
2237                 spin_unlock_irqrestore(&s->lock, flags);
2238                 return put_user(val, (int *) arg);
2239
2240         case SNDCTL_DSP_GETIPTR:
2241                 if (!(file->f_mode & FMODE_READ))
2242                         return -EINVAL;
2243                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2244                         return 0;
2245                 spin_lock_irqsave(&s->lock, flags);
2246                 cs4297a_update_ptr(s,CS_FALSE);
2247                 cinfo.bytes = s->dma_adc.total_bytes;
2248                 if (s->dma_adc.mapped) {
2249                         cinfo.blocks =
2250                             (cinfo.bytes >> s->dma_adc.fragshift) -
2251                             s->dma_adc.blocks;
2252                         s->dma_adc.blocks =
2253                             cinfo.bytes >> s->dma_adc.fragshift;
2254                 } else {
2255                         if (s->conversion) {
2256                                 cinfo.blocks =
2257                                     s->dma_adc.count /
2258                                     2 >> (s->dma_adc.fragshift - 1);
2259                         } else
2260                                 cinfo.blocks =
2261                                     s->dma_adc.count >> s->dma_adc.
2262                                     fragshift;
2263                 }
2264                 if (s->conversion)
2265                         cinfo.ptr = s->dma_adc.hwptr / 2;
2266                 else
2267                         cinfo.ptr = s->dma_adc.hwptr;
2268                 if (s->dma_adc.mapped)
2269                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
2270                 spin_unlock_irqrestore(&s->lock, flags);
2271                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2272
2273         case SNDCTL_DSP_GETOPTR:
2274                 if (!(file->f_mode & FMODE_WRITE))
2275                         return -EINVAL;
2276                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2277                         return 0;
2278                 spin_lock_irqsave(&s->lock, flags);
2279                 cs4297a_update_ptr(s,CS_FALSE);
2280                 cinfo.bytes = s->dma_dac.total_bytes;
2281                 if (s->dma_dac.mapped) {
2282                         cinfo.blocks =
2283                             (cinfo.bytes >> s->dma_dac.fragshift) -
2284                             s->dma_dac.blocks;
2285                         s->dma_dac.blocks =
2286                             cinfo.bytes >> s->dma_dac.fragshift;
2287                 } else {
2288                         cinfo.blocks =
2289                             s->dma_dac.count >> s->dma_dac.fragshift;
2290                 }
2291                 cinfo.ptr = s->dma_dac.hwptr;
2292                 if (s->dma_dac.mapped)
2293                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
2294                 spin_unlock_irqrestore(&s->lock, flags);
2295                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2296
2297         case SNDCTL_DSP_GETBLKSIZE:
2298                 if (file->f_mode & FMODE_WRITE) {
2299                         if ((val = prog_dmabuf_dac(s)))
2300                                 return val;
2301                         return put_user(s->dma_dac.fragsize, (int *) arg);
2302                 }
2303                 if ((val = prog_dmabuf_adc(s)))
2304                         return val;
2305                 if (s->conversion)
2306                         return put_user(s->dma_adc.fragsize / 2,
2307                                         (int *) arg);
2308                 else
2309                         return put_user(s->dma_adc.fragsize, (int *) arg);
2310
2311         case SNDCTL_DSP_SETFRAGMENT:
2312                 if (get_user(val, (int *) arg))
2313                         return -EFAULT;
2314                 return 0;       // Say OK, but do nothing.
2315
2316         case SNDCTL_DSP_SUBDIVIDE:
2317                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2318                     || (file->f_mode & FMODE_WRITE
2319                         && s->dma_dac.subdivision)) return -EINVAL;
2320                 if (get_user(val, (int *) arg))
2321                         return -EFAULT;
2322                 if (val != 1 && val != 2 && val != 4)
2323                         return -EINVAL;
2324                 if (file->f_mode & FMODE_READ)
2325                         s->dma_adc.subdivision = val;
2326                 else if (file->f_mode & FMODE_WRITE)
2327                         s->dma_dac.subdivision = val;
2328                 return 0;
2329
2330         case SOUND_PCM_READ_RATE:
2331                 if (file->f_mode & FMODE_READ)
2332                         return put_user(s->prop_adc.rate, (int *) arg);
2333                 else if (file->f_mode & FMODE_WRITE)
2334                         return put_user(s->prop_dac.rate, (int *) arg);
2335
2336         case SOUND_PCM_READ_CHANNELS:
2337                 if (file->f_mode & FMODE_READ)
2338                         return put_user(s->prop_adc.channels, (int *) arg);
2339                 else if (file->f_mode & FMODE_WRITE)
2340                         return put_user(s->prop_dac.channels, (int *) arg);
2341
2342         case SOUND_PCM_READ_BITS:
2343                 if (file->f_mode & FMODE_READ)
2344                         return
2345                             put_user(
2346                                      (s->prop_adc.
2347                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2348                                      (int *) arg);
2349                 else if (file->f_mode & FMODE_WRITE)
2350                         return
2351                             put_user(
2352                                      (s->prop_dac.
2353                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2354                                      (int *) arg);
2355
2356         case SOUND_PCM_WRITE_FILTER:
2357         case SNDCTL_DSP_SETSYNCRO:
2358         case SOUND_PCM_READ_FILTER:
2359                 return -EINVAL;
2360         }
2361         return mixer_ioctl(s, cmd, arg);
2362 }
2363
2364 static long cs4297a_unlocked_ioctl(struct file *file, u_int cmd, u_long arg)
2365 {
2366         int ret;
2367
2368         mutex_lock(&swarm_cs4297a_mutex);
2369         ret = cs4297a_ioctl(file, cmd, arg);
2370         mutex_unlock(&swarm_cs4297a_mutex);
2371
2372         return ret;
2373 }
2374
2375 static int cs4297a_release(struct inode *inode, struct file *file)
2376 {
2377         struct cs4297a_state *s =
2378             (struct cs4297a_state *) file->private_data;
2379
2380         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2381                  "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2382                          (unsigned) inode, (unsigned) file, file->f_mode));
2383         VALIDATE_STATE(s);
2384
2385         if (file->f_mode & FMODE_WRITE) {
2386                 drain_dac(s, file->f_flags & O_NONBLOCK);
2387                 mutex_lock(&s->open_sem_dac);
2388                 stop_dac(s);
2389                 dealloc_dmabuf(s, &s->dma_dac);
2390                 s->open_mode &= ~FMODE_WRITE;
2391                 mutex_unlock(&s->open_sem_dac);
2392                 wake_up(&s->open_wait_dac);
2393         }
2394         if (file->f_mode & FMODE_READ) {
2395                 drain_adc(s, file->f_flags & O_NONBLOCK);
2396                 mutex_lock(&s->open_sem_adc);
2397                 stop_adc(s);
2398                 dealloc_dmabuf(s, &s->dma_adc);
2399                 s->open_mode &= ~FMODE_READ;
2400                 mutex_unlock(&s->open_sem_adc);
2401                 wake_up(&s->open_wait_adc);
2402         }
2403         return 0;
2404 }
2405
2406 static int cs4297a_locked_open(struct inode *inode, struct file *file)
2407 {
2408         int minor = iminor(inode);
2409         struct cs4297a_state *s=NULL;
2410         struct list_head *entry;
2411
2412         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2413                 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2414                         (unsigned) inode, (unsigned) file, file->f_mode));
2415         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2416                 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2417
2418         list_for_each(entry, &cs4297a_devs)
2419         {
2420                 s = list_entry(entry, struct cs4297a_state, list);
2421
2422                 if (!((s->dev_audio ^ minor) & ~0xf))
2423                         break;
2424         }
2425         if (entry == &cs4297a_devs)
2426                 return -ENODEV;
2427         if (!s) {
2428                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2429                         "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2430                 return -ENODEV;
2431         }
2432         VALIDATE_STATE(s);
2433         file->private_data = s;
2434
2435         // wait for device to become free
2436         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2437                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2438                          "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2439                 return -ENODEV;
2440         }
2441         if (file->f_mode & FMODE_WRITE) {
2442                 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2443                         printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2444                         while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2445                                 ;
2446                 }
2447
2448                 mutex_lock(&s->open_sem_dac);
2449                 while (s->open_mode & FMODE_WRITE) {
2450                         if (file->f_flags & O_NONBLOCK) {
2451                                 mutex_unlock(&s->open_sem_dac);
2452                                 return -EBUSY;
2453                         }
2454                         mutex_unlock(&s->open_sem_dac);
2455                         interruptible_sleep_on(&s->open_wait_dac);
2456
2457                         if (signal_pending(current)) {
2458                                 printk("open - sig pending\n");
2459                                 return -ERESTARTSYS;
2460                         }
2461                         mutex_lock(&s->open_sem_dac);
2462                 }
2463         }
2464         if (file->f_mode & FMODE_READ) {
2465                 mutex_lock(&s->open_sem_adc);
2466                 while (s->open_mode & FMODE_READ) {
2467                         if (file->f_flags & O_NONBLOCK) {
2468                                 mutex_unlock(&s->open_sem_adc);
2469                                 return -EBUSY;
2470                         }
2471                         mutex_unlock(&s->open_sem_adc);
2472                         interruptible_sleep_on(&s->open_wait_adc);
2473
2474                         if (signal_pending(current)) {
2475                                 printk("open - sig pending\n");
2476                                 return -ERESTARTSYS;
2477                         }
2478                         mutex_lock(&s->open_sem_adc);
2479                 }
2480         }
2481         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2482         if (file->f_mode & FMODE_READ) {
2483                 s->prop_adc.fmt = AFMT_S16_BE;
2484                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2485                 s->prop_adc.channels = 2;
2486                 s->prop_adc.rate = 48000;
2487                 s->conversion = 0;
2488                 s->ena &= ~FMODE_READ;
2489                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2490                     s->dma_adc.subdivision = 0;
2491                 mutex_unlock(&s->open_sem_adc);
2492
2493                 if (prog_dmabuf_adc(s)) {
2494                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2495                                 "cs4297a: adc Program dmabufs failed.\n"));
2496                         cs4297a_release(inode, file);
2497                         return -ENOMEM;
2498                 }
2499         }
2500         if (file->f_mode & FMODE_WRITE) {
2501                 s->prop_dac.fmt = AFMT_S16_BE;
2502                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2503                 s->prop_dac.channels = 2;
2504                 s->prop_dac.rate = 48000;
2505                 s->conversion = 0;
2506                 s->ena &= ~FMODE_WRITE;
2507                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2508                     s->dma_dac.subdivision = 0;
2509                 mutex_unlock(&s->open_sem_dac);
2510
2511                 if (prog_dmabuf_dac(s)) {
2512                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2513                                 "cs4297a: dac Program dmabufs failed.\n"));
2514                         cs4297a_release(inode, file);
2515                         return -ENOMEM;
2516                 }
2517         }
2518         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2519                   printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2520         return nonseekable_open(inode, file);
2521 }
2522
2523 static int cs4297a_open(struct inode *inode, struct file *file)
2524 {
2525         int ret;
2526
2527         mutex_lock(&swarm_cs4297a_mutex);
2528         ret = cs4297a_open(inode, file);
2529         mutex_unlock(&swarm_cs4297a_mutex);
2530
2531         return ret;
2532 }
2533
2534 // ******************************************************************************************
2535 //   Wave (audio) file operations struct.
2536 // ******************************************************************************************
2537 static const struct file_operations cs4297a_audio_fops = {
2538         .owner          = THIS_MODULE,
2539         .llseek         = no_llseek,
2540         .read           = cs4297a_read,
2541         .write          = cs4297a_write,
2542         .poll           = cs4297a_poll,
2543         .unlocked_ioctl = cs4297a_unlocked_ioctl,
2544         .mmap           = cs4297a_mmap,
2545         .open           = cs4297a_open,
2546         .release        = cs4297a_release,
2547 };
2548
2549 static void cs4297a_interrupt(int irq, void *dev_id)
2550 {
2551         struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2552         u32 status;
2553
2554         status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2555
2556         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2557                  "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2558
2559 #if 0
2560         /* XXXKW what check *should* be done here? */
2561         if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2562                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2563                 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2564                 return;
2565         }
2566 #endif
2567
2568         if (status & M_SYNCSER_RX_SYNC_ERR) {
2569                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2570                 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2571                 return;
2572         }
2573
2574         if (status & M_SYNCSER_RX_OVERRUN) {
2575                 int newptr, i;
2576                 s->stats.rx_ovrrn++;
2577                 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2578
2579                 /* Fix things up: get the receive descriptor pool
2580                    clean and give them back to the hardware */
2581                 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2582                         ;
2583                 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2584                                      s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2585                 for (i=0; i<DMA_DESCR; i++) {
2586                         s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2587                 }
2588                 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2589                 s->dma_adc.count = 0;
2590                 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2591                 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2592         }
2593
2594         spin_lock(&s->lock);
2595         cs4297a_update_ptr(s,CS_TRUE);
2596         spin_unlock(&s->lock);
2597
2598         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2599                   "cs4297a: cs4297a_interrupt()-\n"));
2600 }
2601
2602 #if 0
2603 static struct initvol {
2604         int mixch;
2605         int vol;
2606 } initvol[] __initdata = {
2607
2608         {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2609         {SOUND_MIXER_WRITE_PCM, 0x4040},
2610         {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2611         {SOUND_MIXER_WRITE_CD, 0x4040},
2612         {SOUND_MIXER_WRITE_LINE, 0x4040},
2613         {SOUND_MIXER_WRITE_LINE1, 0x4040},
2614         {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2615         {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2616         {SOUND_MIXER_WRITE_MIC, 0x0000}
2617 };
2618 #endif
2619
2620 static int __init cs4297a_init(void)
2621 {
2622         struct cs4297a_state *s;
2623         u32 pwr, id;
2624         mm_segment_t fs;
2625         int rval;
2626 #ifndef CONFIG_BCM_CS4297A_CSWARM
2627         u64 cfg;
2628         int mdio_val;
2629 #endif
2630
2631         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2632                 "cs4297a: cs4297a_init_module()+ \n"));
2633
2634 #ifndef CONFIG_BCM_CS4297A_CSWARM
2635         mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2636                 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2637
2638         /* Check syscfg for synchronous serial on port 1 */
2639         cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2640         if (!(cfg & M_SYS_SER1_ENABLE)) {
2641                 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2642                 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2643                 if (!(cfg & M_SYS_SER1_ENABLE)) {
2644                   printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2645                   return -1;
2646                 }
2647
2648                 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2649
2650                 /* Force the codec (on SWARM) to reset by clearing
2651                    GENO, preserving MDIO (no effect on CSWARM) */
2652                 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2653                 udelay(10);
2654         }
2655
2656         /* Now set GENO */
2657         __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2658         /* Give the codec some time to finish resetting (start the bit clock) */
2659         udelay(100);
2660 #endif
2661
2662         if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2663                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2664                       "cs4297a: probe() no memory for state struct.\n"));
2665                 return -1;
2666         }
2667         s->magic = CS4297a_MAGIC;
2668         init_waitqueue_head(&s->dma_adc.wait);
2669         init_waitqueue_head(&s->dma_dac.wait);
2670         init_waitqueue_head(&s->dma_adc.reg_wait);
2671         init_waitqueue_head(&s->dma_dac.reg_wait);
2672         init_waitqueue_head(&s->open_wait);
2673         init_waitqueue_head(&s->open_wait_adc);
2674         init_waitqueue_head(&s->open_wait_dac);
2675         mutex_init(&s->open_sem_adc);
2676         mutex_init(&s->open_sem_dac);
2677         spin_lock_init(&s->lock);
2678
2679         s->irq = K_INT_SER_1;
2680
2681         if (request_irq
2682             (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2683                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2684                           printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2685                 goto err_irq;
2686         }
2687         if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2688             0) {
2689                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2690                          "cs4297a: probe() register_sound_dsp() failed.\n"));
2691                 goto err_dev1;
2692         }
2693         if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2694             0) {
2695                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2696                          "cs4297a: probe() register_sound_mixer() failed.\n"));
2697                 goto err_dev2;
2698         }
2699
2700         if (ser_init(s) || dma_init(s)) {
2701                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2702                          "cs4297a: ser_init failed.\n"));
2703                 goto err_dev3;
2704         }
2705
2706         do {
2707                 udelay(4000);
2708                 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2709         } while (!rval && (pwr != 0xf));
2710
2711         if (!rval) {
2712                 char *sb1250_duart_present;
2713
2714                 fs = get_fs();
2715                 set_fs(KERNEL_DS);
2716 #if 0
2717                 val = SOUND_MASK_LINE;
2718                 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2719                 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
2720                         val = initvol[i].vol;
2721                         mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2722                 }
2723 //                cs4297a_write_ac97(s, 0x18, 0x0808);
2724 #else
2725                 //                cs4297a_write_ac97(s, 0x5e, 0x180);
2726                 cs4297a_write_ac97(s, 0x02, 0x0808);
2727                 cs4297a_write_ac97(s, 0x18, 0x0808);
2728 #endif
2729                 set_fs(fs);
2730
2731                 list_add(&s->list, &cs4297a_devs);
2732
2733                 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2734
2735                 sb1250_duart_present = symbol_get(sb1250_duart_present);
2736                 if (sb1250_duart_present)
2737                         sb1250_duart_present[1] = 0;
2738
2739                 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2740
2741                 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2742                           printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2743
2744                 return 0;
2745         }
2746
2747  err_dev3:
2748         unregister_sound_mixer(s->dev_mixer);
2749  err_dev2:
2750         unregister_sound_dsp(s->dev_audio);
2751  err_dev1:
2752         free_irq(s->irq, s);
2753  err_irq:
2754         kfree(s);
2755
2756         printk(KERN_INFO "cs4297a: initialization failed\n");
2757
2758         return -1;
2759 }
2760
2761 static void __exit cs4297a_cleanup(void)
2762 {
2763         /*
2764           XXXKW
2765            disable_irq, free_irq
2766            drain DMA queue
2767            disable DMA
2768            disable TX/RX
2769            free memory
2770         */
2771         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2772                   printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2773 }
2774
2775 // ---------------------------------------------------------------------
2776
2777 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2778 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2779
2780 // ---------------------------------------------------------------------
2781
2782 module_init(cs4297a_init);
2783 module_exit(cs4297a_cleanup);