sound/oss/au1550_ac97.c

   1 /*
   2  * au1550_ac97.c  --  Sound driver for Alchemy Au1550 MIPS Internet Edge
   3  *                    Processor.
   4  *
   5  * Copyright 2004 Embedded Edge, LLC
   6  *      dan@embeddededge.com
   7  *
   8  * Mostly copied from the au1000.c driver and some from the
   9  * PowerMac dbdma driver.
  10  * We assume the processor can do memory coherent DMA.
  11  *
  12  * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13  *
  14  *  This program is free software; you can redistribute  it and/or modify it
  15  *  under  the terms of  the GNU General  Public License as published by the
  16  *  Free Software Foundation;  either version 2 of the  License, or (at your
  17  *  option) any later version.
  18  *
  19  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  20  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  21  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  22  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  23  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  25  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  27  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  *  You should have received a copy of the  GNU General Public License along
  31  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  32  *  675 Mass Ave, Cambridge, MA 02139, USA.
  33  *
  34  */
  35
  36 #undef DEBUG
  37
  38 #include <linux/module.h>
  39 #include <linux/string.h>
  40 #include <linux/ioport.h>
  41 #include <linux/sched.h>
  42 #include <linux/delay.h>
  43 #include <linux/sound.h>
  44 #include <linux/slab.h>
  45 #include <linux/soundcard.h>
  46 #include <linux/init.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/kernel.h>
  49 #include <linux/poll.h>
  50 #include <linux/pci.h>
  51 #include <linux/bitops.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/smp_lock.h>
  54 #include <linux/ac97_codec.h>
  55 #include <asm/io.h>
  56 #include <asm/uaccess.h>
  57 #include <asm/hardirq.h>
  58 #include <asm/mach-au1x00/au1000.h>
  59 #include <asm/mach-au1x00/au1xxx_psc.h>
  60 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  61
  62 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  63
  64 /* misc stuff */
  65 #define POLL_COUNT   0x50000
  66 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  67
  68 /* The number of DBDMA ring descriptors to allocate.  No sense making
  69  * this too large....if you can't keep up with a few you aren't likely
  70  * to be able to with lots of them, either.
  71  */
  72 #define NUM_DBDMA_DESCRIPTORS 4
  73
  74 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  75
  76 /* Boot options
  77  * 0 = no VRA, 1 = use VRA if codec supports it
  78  */
  79 static int      vra = 1;
  80 MODULE_PARM(vra, "i");
  81 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  82
  83 static struct au1550_state {
  84         /* soundcore stuff */
  85         int             dev_audio;
  86
  87         struct ac97_codec *codec;
  88         unsigned        codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  89         unsigned        codec_ext_caps;  /* AC'97 reg 28h, "Extended Audio ID" */
  90         int             no_vra;         /* do not use VRA */
  91
  92         spinlock_t      lock;
  93         struct semaphore open_sem;
  94         struct semaphore sem;
  95         mode_t          open_mode;
  96         wait_queue_head_t open_wait;
  97
  98         struct dmabuf {
  99                 u32             dmanr;
 100                 unsigned        sample_rate;
 101                 unsigned        src_factor;
 102                 unsigned        sample_size;
 103                 int             num_channels;
 104                 int             dma_bytes_per_sample;
 105                 int             user_bytes_per_sample;
 106                 int             cnt_factor;
 107
 108                 void            *rawbuf;
 109                 unsigned        buforder;
 110                 unsigned        numfrag;
 111                 unsigned        fragshift;
 112                 void            *nextIn;
 113                 void            *nextOut;
 114                 int             count;
 115                 unsigned        total_bytes;
 116                 unsigned        error;
 117                 wait_queue_head_t wait;
 118
 119                 /* redundant, but makes calculations easier */
 120                 unsigned        fragsize;
 121                 unsigned        dma_fragsize;
 122                 unsigned        dmasize;
 123                 unsigned        dma_qcount;
 124
 125                 /* OSS stuff */
 126                 unsigned        mapped:1;
 127                 unsigned        ready:1;
 128                 unsigned        stopped:1;
 129                 unsigned        ossfragshift;
 130                 int             ossmaxfrags;
 131                 unsigned        subdivision;
 132         } dma_dac, dma_adc;
 133 } au1550_state;
 134
 135 static unsigned
 136 ld2(unsigned int x)
 137 {
 138         unsigned        r = 0;
 139
 140         if (x >= 0x10000) {
 141                 x >>= 16;
 142                 r += 16;
 143         }
 144         if (x >= 0x100) {
 145                 x >>= 8;
 146                 r += 8;
 147         }
 148         if (x >= 0x10) {
 149                 x >>= 4;
 150                 r += 4;
 151         }
 152         if (x >= 4) {
 153                 x >>= 2;
 154                 r += 2;
 155         }
 156         if (x >= 2)
 157                 r++;
 158         return r;
 159 }
 160
 161 static void
 162 au1550_delay(int msec)
 163 {
 164         unsigned long   tmo;
 165         signed long     tmo2;
 166
 167         if (in_interrupt())
 168                 return;
 169
 170         tmo = jiffies + (msec * HZ) / 1000;
 171         for (;;) {
 172                 tmo2 = tmo - jiffies;
 173                 if (tmo2 <= 0)
 174                         break;
 175                 schedule_timeout(tmo2);
 176         }
 177 }
 178
 179 static u16
 180 rdcodec(struct ac97_codec *codec, u8 addr)
 181 {
 182         struct au1550_state *s = (struct au1550_state *)codec->private_data;
 183         unsigned long   flags;
 184         u32             cmd, val;
 185         u16             data;
 186         int             i;
 187
 188         spin_lock_irqsave(&s->lock, flags);
 189
 190         for (i = 0; i < POLL_COUNT; i++) {
 191                 val = au_readl(PSC_AC97STAT);
 192                 au_sync();
 193                 if (!(val & PSC_AC97STAT_CP))
 194                         break;
 195         }
 196         if (i == POLL_COUNT)
 197                 err("rdcodec: codec cmd pending expired!");
 198
 199         cmd = (u32)PSC_AC97CDC_INDX(addr);
 200         cmd |= PSC_AC97CDC_RD;  /* read command */
 201         au_writel(cmd, PSC_AC97CDC);
 202         au_sync();
 203
 204         /* now wait for the data
 205         */
 206         for (i = 0; i < POLL_COUNT; i++) {
 207                 val = au_readl(PSC_AC97STAT);
 208                 au_sync();
 209                 if (!(val & PSC_AC97STAT_CP))
 210                         break;
 211         }
 212         if (i == POLL_COUNT) {
 213                 err("rdcodec: read poll expired!");
 214                 return 0;
 215         }
 216
 217         /* wait for command done?
 218         */
 219         for (i = 0; i < POLL_COUNT; i++) {
 220                 val = au_readl(PSC_AC97EVNT);
 221                 au_sync();
 222                 if (val & PSC_AC97EVNT_CD)
 223                         break;
 224         }
 225         if (i == POLL_COUNT) {
 226                 err("rdcodec: read cmdwait expired!");
 227                 return 0;
 228         }
 229
 230         data = au_readl(PSC_AC97CDC) & 0xffff;
 231         au_sync();
 232
 233         /* Clear command done event.
 234         */
 235         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
 236         au_sync();
 237
 238         spin_unlock_irqrestore(&s->lock, flags);
 239
 240         return data;
 241 }
 242
 243
 244 static void
 245 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
 246 {
 247         struct au1550_state *s = (struct au1550_state *)codec->private_data;
 248         unsigned long   flags;
 249         u32             cmd, val;
 250         int             i;
 251
 252         spin_lock_irqsave(&s->lock, flags);
 253
 254         for (i = 0; i < POLL_COUNT; i++) {
 255                 val = au_readl(PSC_AC97STAT);
 256                 au_sync();
 257                 if (!(val & PSC_AC97STAT_CP))
 258                         break;
 259         }
 260         if (i == POLL_COUNT)
 261                 err("wrcodec: codec cmd pending expired!");
 262
 263         cmd = (u32)PSC_AC97CDC_INDX(addr);
 264         cmd |= (u32)data;
 265         au_writel(cmd, PSC_AC97CDC);
 266         au_sync();
 267
 268         for (i = 0; i < POLL_COUNT; i++) {
 269                 val = au_readl(PSC_AC97STAT);
 270                 au_sync();
 271                 if (!(val & PSC_AC97STAT_CP))
 272                         break;
 273         }
 274         if (i == POLL_COUNT)
 275                 err("wrcodec: codec cmd pending expired!");
 276
 277         for (i = 0; i < POLL_COUNT; i++) {
 278                 val = au_readl(PSC_AC97EVNT);
 279                 au_sync();
 280                 if (val & PSC_AC97EVNT_CD)
 281                         break;
 282         }
 283         if (i == POLL_COUNT)
 284                 err("wrcodec: read cmdwait expired!");
 285
 286         /* Clear command done event.
 287         */
 288         au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
 289         au_sync();
 290
 291         spin_unlock_irqrestore(&s->lock, flags);
 292 }
 293
 294 static void
 295 waitcodec(struct ac97_codec *codec)
 296 {
 297         u16     temp;
 298         u32     val;
 299         int     i;
 300
 301         /* codec_wait is used to wait for a ready state after
 302          * an AC97C_RESET.
 303          */
 304         au1550_delay(10);
 305
 306         /* first poll the CODEC_READY tag bit
 307         */
 308         for (i = 0; i < POLL_COUNT; i++) {
 309                 val = au_readl(PSC_AC97STAT);
 310                 au_sync();
 311                 if (val & PSC_AC97STAT_CR)
 312                         break;
 313         }
 314         if (i == POLL_COUNT) {
 315                 err("waitcodec: CODEC_READY poll expired!");
 316                 return;
 317         }
 318
 319         /* get AC'97 powerdown control/status register
 320         */
 321         temp = rdcodec(codec, AC97_POWER_CONTROL);
 322
 323         /* If anything is powered down, power'em up
 324         */
 325         if (temp & 0x7f00) {
 326                 /* Power on
 327                 */
 328                 wrcodec(codec, AC97_POWER_CONTROL, 0);
 329                 au1550_delay(100);
 330
 331                 /* Reread
 332                 */
 333                 temp = rdcodec(codec, AC97_POWER_CONTROL);
 334         }
 335
 336         /* Check if Codec REF,ANL,DAC,ADC ready
 337         */
 338         if ((temp & 0x7f0f) != 0x000f)
 339                 err("codec reg 26 status (0x%x) not ready!!", temp);
 340 }
 341
 342 /* stop the ADC before calling */
 343 static void
 344 set_adc_rate(struct au1550_state *s, unsigned rate)
 345 {
 346         struct dmabuf  *adc = &s->dma_adc;
 347         struct dmabuf  *dac = &s->dma_dac;
 348         unsigned        adc_rate, dac_rate;
 349         u16             ac97_extstat;
 350
 351         if (s->no_vra) {
 352                 /* calc SRC factor
 353                 */
 354                 adc->src_factor = ((96000 / rate) + 1) >> 1;
 355                 adc->sample_rate = 48000 / adc->src_factor;
 356                 return;
 357         }
 358
 359         adc->src_factor = 1;
 360
 361         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
 362
 363         rate = rate > 48000 ? 48000 : rate;
 364
 365         /* enable VRA
 366         */
 367         wrcodec(s->codec, AC97_EXTENDED_STATUS,
 368                 ac97_extstat | AC97_EXTSTAT_VRA);
 369
 370         /* now write the sample rate
 371         */
 372         wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
 373
 374         /* read it back for actual supported rate
 375         */
 376         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
 377
 378         pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
 379
 380         /* some codec's don't allow unequal DAC and ADC rates, in which case
 381          * writing one rate reg actually changes both.
 382          */
 383         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
 384         if (dac->num_channels > 2)
 385                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
 386         if (dac->num_channels > 4)
 387                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
 388
 389         adc->sample_rate = adc_rate;
 390         dac->sample_rate = dac_rate;
 391 }
 392
 393 /* stop the DAC before calling */
 394 static void
 395 set_dac_rate(struct au1550_state *s, unsigned rate)
 396 {
 397         struct dmabuf  *dac = &s->dma_dac;
 398         struct dmabuf  *adc = &s->dma_adc;
 399         unsigned        adc_rate, dac_rate;
 400         u16             ac97_extstat;
 401
 402         if (s->no_vra) {
 403                 /* calc SRC factor
 404                 */
 405                 dac->src_factor = ((96000 / rate) + 1) >> 1;
 406                 dac->sample_rate = 48000 / dac->src_factor;
 407                 return;
 408         }
 409
 410         dac->src_factor = 1;
 411
 412         ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
 413
 414         rate = rate > 48000 ? 48000 : rate;
 415
 416         /* enable VRA
 417         */
 418         wrcodec(s->codec, AC97_EXTENDED_STATUS,
 419                 ac97_extstat | AC97_EXTSTAT_VRA);
 420
 421         /* now write the sample rate
 422         */
 423         wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
 424
 425         /* I don't support different sample rates for multichannel,
 426          * so make these channels the same.
 427          */
 428         if (dac->num_channels > 2)
 429                 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
 430         if (dac->num_channels > 4)
 431                 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
 432         /* read it back for actual supported rate
 433         */
 434         dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
 435
 436         pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
 437
 438         /* some codec's don't allow unequal DAC and ADC rates, in which case
 439          * writing one rate reg actually changes both.
 440          */
 441         adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
 442
 443         dac->sample_rate = dac_rate;
 444         adc->sample_rate = adc_rate;
 445 }
 446
 447 static void
 448 stop_dac(struct au1550_state *s)
 449 {
 450         struct dmabuf  *db = &s->dma_dac;
 451         u32             stat;
 452         unsigned long   flags;
 453
 454         if (db->stopped)
 455                 return;
 456
 457         spin_lock_irqsave(&s->lock, flags);
 458
 459         au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
 460         au_sync();
 461
 462         /* Wait for Transmit Busy to show disabled.
 463         */
 464         do {
 465                 stat = readl((void *)PSC_AC97STAT);
 466                 au_sync();
 467         } while ((stat & PSC_AC97STAT_TB) != 0);
 468
 469         au1xxx_dbdma_reset(db->dmanr);
 470
 471         db->stopped = 1;
 472
 473         spin_unlock_irqrestore(&s->lock, flags);
 474 }
 475
 476 static void
 477 stop_adc(struct au1550_state *s)
 478 {
 479         struct dmabuf  *db = &s->dma_adc;
 480         unsigned long   flags;
 481         u32             stat;
 482
 483         if (db->stopped)
 484                 return;
 485
 486         spin_lock_irqsave(&s->lock, flags);
 487
 488         au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
 489         au_sync();
 490
 491         /* Wait for Receive Busy to show disabled.
 492         */
 493         do {
 494                 stat = readl((void *)PSC_AC97STAT);
 495                 au_sync();
 496         } while ((stat & PSC_AC97STAT_RB) != 0);
 497
 498         au1xxx_dbdma_reset(db->dmanr);
 499
 500         db->stopped = 1;
 501
 502         spin_unlock_irqrestore(&s->lock, flags);
 503 }
 504
 505
 506 static void
 507 set_xmit_slots(int num_channels)
 508 {
 509         u32     ac97_config, stat;
 510
 511         ac97_config = au_readl(PSC_AC97CFG);
 512         au_sync();
 513         ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
 514         au_writel(ac97_config, PSC_AC97CFG);
 515         au_sync();
 516
 517         switch (num_channels) {
 518         case 6:         /* stereo with surround and center/LFE,
 519                          * slots 3,4,6,7,8,9
 520                          */
 521                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
 522                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
 523
 524         case 4:         /* stereo with surround, slots 3,4,7,8 */
 525                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
 526                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
 527
 528         case 2:         /* stereo, slots 3,4 */
 529         case 1:         /* mono */
 530                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
 531                 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
 532         }
 533
 534         au_writel(ac97_config, PSC_AC97CFG);
 535         au_sync();
 536
 537         ac97_config |= PSC_AC97CFG_DE_ENABLE;
 538         au_writel(ac97_config, PSC_AC97CFG);
 539         au_sync();
 540
 541         /* Wait for Device ready.
 542         */
 543         do {
 544                 stat = readl((void *)PSC_AC97STAT);
 545                 au_sync();
 546         } while ((stat & PSC_AC97STAT_DR) == 0);
 547 }
 548
 549 static void
 550 set_recv_slots(int num_channels)
 551 {
 552         u32     ac97_config, stat;
 553
 554         ac97_config = au_readl(PSC_AC97CFG);
 555         au_sync();
 556         ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
 557         au_writel(ac97_config, PSC_AC97CFG);
 558         au_sync();
 559
 560         /* Always enable slots 3 and 4 (stereo). Slot 6 is
 561          * optional Mic ADC, which we don't support yet.
 562          */
 563         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
 564         ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
 565
 566         au_writel(ac97_config, PSC_AC97CFG);
 567         au_sync();
 568
 569         ac97_config |= PSC_AC97CFG_DE_ENABLE;
 570         au_writel(ac97_config, PSC_AC97CFG);
 571         au_sync();
 572
 573         /* Wait for Device ready.
 574         */
 575         do {
 576                 stat = readl((void *)PSC_AC97STAT);
 577                 au_sync();
 578         } while ((stat & PSC_AC97STAT_DR) == 0);
 579 }
 580
 581 static void
 582 start_dac(struct au1550_state *s)
 583 {
 584         struct dmabuf  *db = &s->dma_dac;
 585         unsigned long   flags;
 586
 587         if (!db->stopped)
 588                 return;
 589
 590         spin_lock_irqsave(&s->lock, flags);
 591
 592         set_xmit_slots(db->num_channels);
 593         au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
 594         au_sync();
 595         au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
 596         au_sync();
 597
 598         au1xxx_dbdma_start(db->dmanr);
 599
 600         db->stopped = 0;
 601
 602         spin_unlock_irqrestore(&s->lock, flags);
 603 }
 604
 605 static void
 606 start_adc(struct au1550_state *s)
 607 {
 608         struct dmabuf  *db = &s->dma_adc;
 609         int     i;
 610
 611         if (!db->stopped)
 612                 return;
 613
 614         /* Put two buffers on the ring to get things started.
 615         */
 616         for (i=0; i<2; i++) {
 617                 au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
 618
 619                 db->nextIn += db->dma_fragsize;
 620                 if (db->nextIn >= db->rawbuf + db->dmasize)
 621                         db->nextIn -= db->dmasize;
 622         }
 623
 624         set_recv_slots(db->num_channels);
 625         au1xxx_dbdma_start(db->dmanr);
 626         au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
 627         au_sync();
 628         au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
 629         au_sync();
 630
 631         db->stopped = 0;
 632 }
 633
 634 static int
 635 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
 636 {
 637         unsigned user_bytes_per_sec;
 638         unsigned        bufs;
 639         unsigned        rate = db->sample_rate;
 640
 641         if (!db->rawbuf) {
 642                 db->ready = db->mapped = 0;
 643                 db->buforder = 5;       /* 32 * PAGE_SIZE */
 644                 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
 645                 if (!db->rawbuf)
 646                         return -ENOMEM;
 647         }
 648
 649         db->cnt_factor = 1;
 650         if (db->sample_size == 8)
 651                 db->cnt_factor *= 2;
 652         if (db->num_channels == 1)
 653                 db->cnt_factor *= 2;
 654         db->cnt_factor *= db->src_factor;
 655
 656         db->count = 0;
 657         db->dma_qcount = 0;
 658         db->nextIn = db->nextOut = db->rawbuf;
 659
 660         db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
 661         db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
 662                                         2 : db->num_channels);
 663
 664         user_bytes_per_sec = rate * db->user_bytes_per_sample;
 665         bufs = PAGE_SIZE << db->buforder;
 666         if (db->ossfragshift) {
 667                 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
 668                         db->fragshift = ld2(user_bytes_per_sec/1000);
 669                 else
 670                         db->fragshift = db->ossfragshift;
 671         } else {
 672                 db->fragshift = ld2(user_bytes_per_sec / 100 /
 673                                     (db->subdivision ? db->subdivision : 1));
 674                 if (db->fragshift < 3)
 675                         db->fragshift = 3;
 676         }
 677
 678         db->fragsize = 1 << db->fragshift;
 679         db->dma_fragsize = db->fragsize * db->cnt_factor;
 680         db->numfrag = bufs / db->dma_fragsize;
 681
 682         while (db->numfrag < 4 && db->fragshift > 3) {
 683                 db->fragshift--;
 684                 db->fragsize = 1 << db->fragshift;
 685                 db->dma_fragsize = db->fragsize * db->cnt_factor;
 686                 db->numfrag = bufs / db->dma_fragsize;
 687         }
 688
 689         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
 690                 db->numfrag = db->ossmaxfrags;
 691
 692         db->dmasize = db->dma_fragsize * db->numfrag;
 693         memset(db->rawbuf, 0, bufs);
 694
 695         pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
 696             rate, db->sample_size, db->num_channels);
 697         pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
 698             db->fragsize, db->cnt_factor, db->dma_fragsize);
 699         pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
 700
 701         db->ready = 1;
 702         return 0;
 703 }
 704
 705 static int
 706 prog_dmabuf_adc(struct au1550_state *s)
 707 {
 708         stop_adc(s);
 709         return prog_dmabuf(s, &s->dma_adc);
 710
 711 }
 712
 713 static int
 714 prog_dmabuf_dac(struct au1550_state *s)
 715 {
 716         stop_dac(s);
 717         return prog_dmabuf(s, &s->dma_dac);
 718 }
 719
 720
 721 /* hold spinlock for the following */
 722 static void
 723 dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 724 {
 725         struct au1550_state *s = (struct au1550_state *) dev_id;
 726         struct dmabuf  *db = &s->dma_dac;
 727         u32     ac97c_stat;
 728
 729         ac97c_stat = au_readl(PSC_AC97STAT);
 730         if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
 731                 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
 732         db->dma_qcount--;
 733
 734         if (db->count >= db->fragsize) {
 735                 if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
 736                                                         db->fragsize) == 0) {
 737                         err("qcount < 2 and no ring room!");
 738                 }
 739                 db->nextOut += db->fragsize;
 740                 if (db->nextOut >= db->rawbuf + db->dmasize)
 741                         db->nextOut -= db->dmasize;
 742                 db->count -= db->fragsize;
 743                 db->total_bytes += db->dma_fragsize;
 744                 db->dma_qcount++;
 745         }
 746
 747         /* wake up anybody listening */
 748         if (waitqueue_active(&db->wait))
 749                 wake_up(&db->wait);
 750 }
 751
 752
 753 static void
 754 adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 755 {
 756         struct  au1550_state *s = (struct au1550_state *)dev_id;
 757         struct  dmabuf  *dp = &s->dma_adc;
 758         u32     obytes;
 759         char    *obuf;
 760
 761         /* Pull the buffer from the dma queue.
 762         */
 763         au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
 764
 765         if ((dp->count + obytes) > dp->dmasize) {
 766                 /* Overrun. Stop ADC and log the error
 767                 */
 768                 stop_adc(s);
 769                 dp->error++;
 770                 err("adc overrun");
 771                 return;
 772         }
 773
 774         /* Put a new empty buffer on the destination DMA.
 775         */
 776         au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
 777
 778         dp->nextIn += dp->dma_fragsize;
 779         if (dp->nextIn >= dp->rawbuf + dp->dmasize)
 780                 dp->nextIn -= dp->dmasize;
 781
 782         dp->count += obytes;
 783         dp->total_bytes += obytes;
 784
 785         /* wake up anybody listening
 786         */
 787         if (waitqueue_active(&dp->wait))
 788                 wake_up(&dp->wait);
 789
 790 }
 791
 792 static loff_t
 793 au1550_llseek(struct file *file, loff_t offset, int origin)
 794 {
 795         return -ESPIPE;
 796 }
 797
 798
 799 static int
 800 au1550_open_mixdev(struct inode *inode, struct file *file)
 801 {
 802         file->private_data = &au1550_state;
 803         return 0;
 804 }
 805
 806 static int
 807 au1550_release_mixdev(struct inode *inode, struct file *file)
 808 {
 809         return 0;
 810 }
 811
 812 static int
 813 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
 814                         unsigned long arg)
 815 {
 816         return codec->mixer_ioctl(codec, cmd, arg);
 817 }
 818
 819 static int
 820 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
 821                                unsigned int cmd, unsigned long arg)
 822 {
 823         struct au1550_state *s = (struct au1550_state *)file->private_data;
 824         struct ac97_codec *codec = s->codec;
 825
 826         return mixdev_ioctl(codec, cmd, arg);
 827 }
 828
 829 static /*const */ struct file_operations au1550_mixer_fops = {
 830         owner:THIS_MODULE,
 831         llseek:au1550_llseek,
 832         ioctl:au1550_ioctl_mixdev,
 833         open:au1550_open_mixdev,
 834         release:au1550_release_mixdev,
 835 };
 836
 837 static int
 838 drain_dac(struct au1550_state *s, int nonblock)
 839 {
 840         unsigned long   flags;
 841         int             count, tmo;
 842
 843         if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
 844                 return 0;
 845
 846         for (;;) {
 847                 spin_lock_irqsave(&s->lock, flags);
 848                 count = s->dma_dac.count;
 849                 spin_unlock_irqrestore(&s->lock, flags);
 850                 if (count <= s->dma_dac.fragsize)
 851                         break;
 852                 if (signal_pending(current))
 853                         break;
 854                 if (nonblock)
 855                         return -EBUSY;
 856                 tmo = 1000 * count / (s->no_vra ?
 857                                       48000 : s->dma_dac.sample_rate);
 858                 tmo /= s->dma_dac.dma_bytes_per_sample;
 859                 au1550_delay(tmo);
 860         }
 861         if (signal_pending(current))
 862                 return -ERESTARTSYS;
 863         return 0;
 864 }
 865
 866 static inline u8 S16_TO_U8(s16 ch)
 867 {
 868         return (u8) (ch >> 8) + 0x80;
 869 }
 870 static inline s16 U8_TO_S16(u8 ch)
 871 {
 872         return (s16) (ch - 0x80) << 8;
 873 }
 874
 875 /*
 876  * Translates user samples to dma buffer suitable for AC'97 DAC data:
 877  *     If mono, copy left channel to right channel in dma buffer.
 878  *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
 879  *     If interpolating (no VRA), duplicate every audio frame src_factor times.
 880  */
 881 static int
 882 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
 883                                                                int dmacount)
 884 {
 885         int             sample, i;
 886         int             interp_bytes_per_sample;
 887         int             num_samples;
 888         int             mono = (db->num_channels == 1);
 889         char            usersample[12];
 890         s16             ch, dmasample[6];
 891
 892         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
 893                 /* no translation necessary, just copy
 894                 */
 895                 if (copy_from_user(dmabuf, userbuf, dmacount))
 896                         return -EFAULT;
 897                 return dmacount;
 898         }
 899
 900         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
 901         num_samples = dmacount / interp_bytes_per_sample;
 902
 903         for (sample = 0; sample < num_samples; sample++) {
 904                 if (copy_from_user(usersample, userbuf,
 905                                    db->user_bytes_per_sample)) {
 906                         return -EFAULT;
 907                 }
 908
 909                 for (i = 0; i < db->num_channels; i++) {
 910                         if (db->sample_size == 8)
 911                                 ch = U8_TO_S16(usersample[i]);
 912                         else
 913                                 ch = *((s16 *) (&usersample[i * 2]));
 914                         dmasample[i] = ch;
 915                         if (mono)
 916                                 dmasample[i + 1] = ch;  /* right channel */
 917                 }
 918
 919                 /* duplicate every audio frame src_factor times
 920                 */
 921                 for (i = 0; i < db->src_factor; i++)
 922                         memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
 923
 924                 userbuf += db->user_bytes_per_sample;
 925                 dmabuf += interp_bytes_per_sample;
 926         }
 927
 928         return num_samples * interp_bytes_per_sample;
 929 }
 930
 931 /*
 932  * Translates AC'97 ADC samples to user buffer:
 933  *     If mono, send only left channel to user buffer.
 934  *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
 935  *     If decimating (no VRA), skip over src_factor audio frames.
 936  */
 937 static int
 938 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
 939                                                              int dmacount)
 940 {
 941         int             sample, i;
 942         int             interp_bytes_per_sample;
 943         int             num_samples;
 944         int             mono = (db->num_channels == 1);
 945         char            usersample[12];
 946
 947         if (db->sample_size == 16 && !mono && db->src_factor == 1) {
 948                 /* no translation necessary, just copy
 949                 */
 950                 if (copy_to_user(userbuf, dmabuf, dmacount))
 951                         return -EFAULT;
 952                 return dmacount;
 953         }
 954
 955         interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
 956         num_samples = dmacount / interp_bytes_per_sample;
 957
 958         for (sample = 0; sample < num_samples; sample++) {
 959                 for (i = 0; i < db->num_channels; i++) {
 960                         if (db->sample_size == 8)
 961                                 usersample[i] =
 962                                         S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
 963                         else
 964                                 *((s16 *) (&usersample[i * 2])) =
 965                                         *((s16 *) (&dmabuf[i * 2]));
 966                 }
 967
 968                 if (copy_to_user(userbuf, usersample,
 969                                  db->user_bytes_per_sample)) {
 970                         return -EFAULT;
 971                 }
 972
 973                 userbuf += db->user_bytes_per_sample;
 974                 dmabuf += interp_bytes_per_sample;
 975         }
 976
 977         return num_samples * interp_bytes_per_sample;
 978 }
 979
 980 /*
 981  * Copy audio data to/from user buffer from/to dma buffer, taking care
 982  * that we wrap when reading/writing the dma buffer. Returns actual byte
 983  * count written to or read from the dma buffer.
 984  */
 985 static int
 986 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
 987 {
 988         char           *bufptr = to_user ? db->nextOut : db->nextIn;
 989         char           *bufend = db->rawbuf + db->dmasize;
 990         int             cnt, ret;
 991
 992         if (bufptr + count > bufend) {
 993                 int             partial = (int) (bufend - bufptr);
 994                 if (to_user) {
 995                         if ((cnt = translate_to_user(db, userbuf,
 996                                                      bufptr, partial)) < 0)
 997                                 return cnt;
 998                         ret = cnt;
 999                         if ((cnt = translate_to_user(db, userbuf + partial,
1000                                                      db->rawbuf,
1001                                                      count - partial)) < 0)
1002                                 return cnt;
1003                         ret += cnt;
1004                 } else {
1005                         if ((cnt = translate_from_user(db, bufptr, userbuf,
1006                                                        partial)) < 0)
1007                                 return cnt;
1008                         ret = cnt;
1009                         if ((cnt = translate_from_user(db, db->rawbuf,
1010                                                        userbuf + partial,
1011                                                        count - partial)) < 0)
1012                                 return cnt;
1013                         ret += cnt;
1014                 }
1015         } else {
1016                 if (to_user)
1017                         ret = translate_to_user(db, userbuf, bufptr, count);
1018                 else
1019                         ret = translate_from_user(db, bufptr, userbuf, count);
1020         }
1021
1022         return ret;
1023 }
1024
1025
1026 static ssize_t
1027 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1028 {
1029         struct au1550_state *s = (struct au1550_state *)file->private_data;
1030         struct dmabuf  *db = &s->dma_adc;
1031         DECLARE_WAITQUEUE(wait, current);
1032         ssize_t         ret;
1033         unsigned long   flags;
1034         int             cnt, usercnt, avail;
1035
1036         if (db->mapped)
1037                 return -ENXIO;
1038         if (!access_ok(VERIFY_WRITE, buffer, count))
1039                 return -EFAULT;
1040         ret = 0;
1041
1042         count *= db->cnt_factor;
1043
1044         down(&s->sem);
1045         add_wait_queue(&db->wait, &wait);
1046
1047         while (count > 0) {
1048                 /* wait for samples in ADC dma buffer
1049                 */
1050                 do {
1051                         if (db->stopped)
1052                                 start_adc(s);
1053                         spin_lock_irqsave(&s->lock, flags);
1054                         avail = db->count;
1055                         if (avail <= 0)
1056                                 __set_current_state(TASK_INTERRUPTIBLE);
1057                         spin_unlock_irqrestore(&s->lock, flags);
1058                         if (avail <= 0) {
1059                                 if (file->f_flags & O_NONBLOCK) {
1060                                         if (!ret)
1061                                                 ret = -EAGAIN;
1062                                         goto out;
1063                                 }
1064                                 up(&s->sem);
1065                                 schedule();
1066                                 if (signal_pending(current)) {
1067                                         if (!ret)
1068                                                 ret = -ERESTARTSYS;
1069                                         goto out2;
1070                                 }
1071                                 down(&s->sem);
1072                         }
1073                 } while (avail <= 0);
1074
1075                 /* copy from nextOut to user
1076                 */
1077                 if ((cnt = copy_dmabuf_user(db, buffer,
1078                                             count > avail ?
1079                                             avail : count, 1)) < 0) {
1080                         if (!ret)
1081                                 ret = -EFAULT;
1082                         goto out;
1083                 }
1084
1085                 spin_lock_irqsave(&s->lock, flags);
1086                 db->count -= cnt;
1087                 db->nextOut += cnt;
1088                 if (db->nextOut >= db->rawbuf + db->dmasize)
1089                         db->nextOut -= db->dmasize;
1090                 spin_unlock_irqrestore(&s->lock, flags);
1091
1092                 count -= cnt;
1093                 usercnt = cnt / db->cnt_factor;
1094                 buffer += usercnt;
1095                 ret += usercnt;
1096         }                       /* while (count > 0) */
1097
1098 out:
1099         up(&s->sem);
1100 out2:
1101         remove_wait_queue(&db->wait, &wait);
1102         set_current_state(TASK_RUNNING);
1103         return ret;
1104 }
1105
1106 static ssize_t
1107 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1108 {
1109         struct au1550_state *s = (struct au1550_state *)file->private_data;
1110         struct dmabuf  *db = &s->dma_dac;
1111         DECLARE_WAITQUEUE(wait, current);
1112         ssize_t         ret = 0;
1113         unsigned long   flags;
1114         int             cnt, usercnt, avail;
1115
1116         pr_debug("write: count=%d\n", count);
1117
1118         if (db->mapped)
1119                 return -ENXIO;
1120         if (!access_ok(VERIFY_READ, buffer, count))
1121                 return -EFAULT;
1122
1123         count *= db->cnt_factor;
1124
1125         down(&s->sem);
1126         add_wait_queue(&db->wait, &wait);
1127
1128         while (count > 0) {
1129                 /* wait for space in playback buffer
1130                 */
1131                 do {
1132                         spin_lock_irqsave(&s->lock, flags);
1133                         avail = (int) db->dmasize - db->count;
1134                         if (avail <= 0)
1135                                 __set_current_state(TASK_INTERRUPTIBLE);
1136                         spin_unlock_irqrestore(&s->lock, flags);
1137                         if (avail <= 0) {
1138                                 if (file->f_flags & O_NONBLOCK) {
1139                                         if (!ret)
1140                                                 ret = -EAGAIN;
1141                                         goto out;
1142                                 }
1143                                 up(&s->sem);
1144                                 schedule();
1145                                 if (signal_pending(current)) {
1146                                         if (!ret)
1147                                                 ret = -ERESTARTSYS;
1148                                         goto out2;
1149                                 }
1150                                 down(&s->sem);
1151                         }
1152                 } while (avail <= 0);
1153
1154                 /* copy from user to nextIn
1155                 */
1156                 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1157                                             count > avail ?
1158                                             avail : count, 0)) < 0) {
1159                         if (!ret)
1160                                 ret = -EFAULT;
1161                         goto out;
1162                 }
1163
1164                 spin_lock_irqsave(&s->lock, flags);
1165                 db->count += cnt;
1166                 db->nextIn += cnt;
1167                 if (db->nextIn >= db->rawbuf + db->dmasize)
1168                         db->nextIn -= db->dmasize;
1169
1170                 /* If the data is available, we want to keep two buffers
1171                  * on the dma queue.  If the queue count reaches zero,
1172                  * we know the dma has stopped.
1173                  */
1174                 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1175                         if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
1176                                                         db->fragsize) == 0) {
1177                                 err("qcount < 2 and no ring room!");
1178                         }
1179                         db->nextOut += db->fragsize;
1180                         if (db->nextOut >= db->rawbuf + db->dmasize)
1181                                 db->nextOut -= db->dmasize;
1182                         db->total_bytes += db->dma_fragsize;
1183                         if (db->dma_qcount == 0)
1184                                 start_dac(s);
1185                         db->dma_qcount++;
1186                 }
1187                 spin_unlock_irqrestore(&s->lock, flags);
1188
1189                 count -= cnt;
1190                 usercnt = cnt / db->cnt_factor;
1191                 buffer += usercnt;
1192                 ret += usercnt;
1193         }                       /* while (count > 0) */
1194
1195 out:
1196         up(&s->sem);
1197 out2:
1198         remove_wait_queue(&db->wait, &wait);
1199         set_current_state(TASK_RUNNING);
1200         return ret;
1201 }
1202
1203
1204 /* No kernel lock - we have our own spinlock */
1205 static unsigned int
1206 au1550_poll(struct file *file, struct poll_table_struct *wait)
1207 {
1208         struct au1550_state *s = (struct au1550_state *)file->private_data;
1209         unsigned long   flags;
1210         unsigned int    mask = 0;
1211
1212         if (file->f_mode & FMODE_WRITE) {
1213                 if (!s->dma_dac.ready)
1214                         return 0;
1215                 poll_wait(file, &s->dma_dac.wait, wait);
1216         }
1217         if (file->f_mode & FMODE_READ) {
1218                 if (!s->dma_adc.ready)
1219                         return 0;
1220                 poll_wait(file, &s->dma_adc.wait, wait);
1221         }
1222
1223         spin_lock_irqsave(&s->lock, flags);
1224
1225         if (file->f_mode & FMODE_READ) {
1226                 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1227                         mask |= POLLIN | POLLRDNORM;
1228         }
1229         if (file->f_mode & FMODE_WRITE) {
1230                 if (s->dma_dac.mapped) {
1231                         if (s->dma_dac.count >=
1232                             (signed)s->dma_dac.dma_fragsize)
1233                                 mask |= POLLOUT | POLLWRNORM;
1234                 } else {
1235                         if ((signed) s->dma_dac.dmasize >=
1236                             s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1237                                 mask |= POLLOUT | POLLWRNORM;
1238                 }
1239         }
1240         spin_unlock_irqrestore(&s->lock, flags);
1241         return mask;
1242 }
1243
1244 static int
1245 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1246 {
1247         struct au1550_state *s = (struct au1550_state *)file->private_data;
1248         struct dmabuf  *db;
1249         unsigned long   size;
1250         int ret = 0;
1251
1252         lock_kernel();
1253         down(&s->sem);
1254         if (vma->vm_flags & VM_WRITE)
1255                 db = &s->dma_dac;
1256         else if (vma->vm_flags & VM_READ)
1257                 db = &s->dma_adc;
1258         else {
1259                 ret = -EINVAL;
1260                 goto out;
1261         }
1262         if (vma->vm_pgoff != 0) {
1263                 ret = -EINVAL;
1264                 goto out;
1265         }
1266         size = vma->vm_end - vma->vm_start;
1267         if (size > (PAGE_SIZE << db->buforder)) {
1268                 ret = -EINVAL;
1269                 goto out;
1270         }
1271         if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1272                              size, vma->vm_page_prot)) {
1273                 ret = -EAGAIN;
1274                 goto out;
1275         }
1276         vma->vm_flags &= ~VM_IO;
1277         db->mapped = 1;
1278 out:
1279         up(&s->sem);
1280         unlock_kernel();
1281         return ret;
1282 }
1283
1284 #ifdef DEBUG
1285 static struct ioctl_str_t {
1286         unsigned int    cmd;
1287         const char     *str;
1288 } ioctl_str[] = {
1289         {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1290         {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1291         {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1292         {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1293         {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1294         {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1295         {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1296         {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1297         {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1298         {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1299         {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1300         {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1301         {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1302         {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1303         {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1304         {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1305         {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1306         {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1307         {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1308         {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1309         {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1310         {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1311         {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1312         {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1313         {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1314         {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1315         {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1316         {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1317         {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1318         {OSS_GETVERSION, "OSS_GETVERSION"},
1319         {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1320         {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1321         {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1322         {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1323 };
1324 #endif
1325
1326 static int
1327 dma_count_done(struct dmabuf *db)
1328 {
1329         if (db->stopped)
1330                 return 0;
1331
1332         return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1333 }
1334
1335
1336 static int
1337 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1338                                                         unsigned long arg)
1339 {
1340         struct au1550_state *s = (struct au1550_state *)file->private_data;
1341         unsigned long   flags;
1342         audio_buf_info  abinfo;
1343         count_info      cinfo;
1344         int             count;
1345         int             val, mapped, ret, diff;
1346
1347         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1348                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1349
1350 #ifdef DEBUG
1351         for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1352                 if (ioctl_str[count].cmd == cmd)
1353                         break;
1354         }
1355         if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1356                 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1357         else
1358                 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1359 #endif
1360
1361         switch (cmd) {
1362         case OSS_GETVERSION:
1363                 return put_user(SOUND_VERSION, (int *) arg);
1364
1365         case SNDCTL_DSP_SYNC:
1366                 if (file->f_mode & FMODE_WRITE)
1367                         return drain_dac(s, file->f_flags & O_NONBLOCK);
1368                 return 0;
1369
1370         case SNDCTL_DSP_SETDUPLEX:
1371                 return 0;
1372
1373         case SNDCTL_DSP_GETCAPS:
1374                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1375                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1376
1377         case SNDCTL_DSP_RESET:
1378                 if (file->f_mode & FMODE_WRITE) {
1379                         stop_dac(s);
1380                         synchronize_irq();
1381                         s->dma_dac.count = s->dma_dac.total_bytes = 0;
1382                         s->dma_dac.nextIn = s->dma_dac.nextOut =
1383                                 s->dma_dac.rawbuf;
1384                 }
1385                 if (file->f_mode & FMODE_READ) {
1386                         stop_adc(s);
1387                         synchronize_irq();
1388                         s->dma_adc.count = s->dma_adc.total_bytes = 0;
1389                         s->dma_adc.nextIn = s->dma_adc.nextOut =
1390                                 s->dma_adc.rawbuf;
1391                 }
1392                 return 0;
1393
1394         case SNDCTL_DSP_SPEED:
1395                 if (get_user(val, (int *) arg))
1396                         return -EFAULT;
1397                 if (val >= 0) {
1398                         if (file->f_mode & FMODE_READ) {
1399                                 stop_adc(s);
1400                                 set_adc_rate(s, val);
1401                         }
1402                         if (file->f_mode & FMODE_WRITE) {
1403                                 stop_dac(s);
1404                                 set_dac_rate(s, val);
1405                         }
1406                         if (s->open_mode & FMODE_READ)
1407                                 if ((ret = prog_dmabuf_adc(s)))
1408                                         return ret;
1409                         if (s->open_mode & FMODE_WRITE)
1410                                 if ((ret = prog_dmabuf_dac(s)))
1411                                         return ret;
1412                 }
1413                 return put_user((file->f_mode & FMODE_READ) ?
1414                                 s->dma_adc.sample_rate :
1415                                 s->dma_dac.sample_rate,
1416                                 (int *)arg);
1417
1418         case SNDCTL_DSP_STEREO:
1419                 if (get_user(val, (int *) arg))
1420                         return -EFAULT;
1421                 if (file->f_mode & FMODE_READ) {
1422                         stop_adc(s);
1423                         s->dma_adc.num_channels = val ? 2 : 1;
1424                         if ((ret = prog_dmabuf_adc(s)))
1425                                 return ret;
1426                 }
1427                 if (file->f_mode & FMODE_WRITE) {
1428                         stop_dac(s);
1429                         s->dma_dac.num_channels = val ? 2 : 1;
1430                         if (s->codec_ext_caps & AC97_EXT_DACS) {
1431                                 /* disable surround and center/lfe in AC'97
1432                                 */
1433                                 u16 ext_stat = rdcodec(s->codec,
1434                                                        AC97_EXTENDED_STATUS);
1435                                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1436                                         ext_stat | (AC97_EXTSTAT_PRI |
1437                                                     AC97_EXTSTAT_PRJ |
1438                                                     AC97_EXTSTAT_PRK));
1439                         }
1440                         if ((ret = prog_dmabuf_dac(s)))
1441                                 return ret;
1442                 }
1443                 return 0;
1444
1445         case SNDCTL_DSP_CHANNELS:
1446                 if (get_user(val, (int *) arg))
1447                         return -EFAULT;
1448                 if (val != 0) {
1449                         if (file->f_mode & FMODE_READ) {
1450                                 if (val < 0 || val > 2)
1451                                         return -EINVAL;
1452                                 stop_adc(s);
1453                                 s->dma_adc.num_channels = val;
1454                                 if ((ret = prog_dmabuf_adc(s)))
1455                                         return ret;
1456                         }
1457                         if (file->f_mode & FMODE_WRITE) {
1458                                 switch (val) {
1459                                 case 1:
1460                                 case 2:
1461                                         break;
1462                                 case 3:
1463                                 case 5:
1464                                         return -EINVAL;
1465                                 case 4:
1466                                         if (!(s->codec_ext_caps &
1467                                               AC97_EXTID_SDAC))
1468                                                 return -EINVAL;
1469                                         break;
1470                                 case 6:
1471                                         if ((s->codec_ext_caps &
1472                                              AC97_EXT_DACS) != AC97_EXT_DACS)
1473                                                 return -EINVAL;
1474                                         break;
1475                                 default:
1476                                         return -EINVAL;
1477                                 }
1478
1479                                 stop_dac(s);
1480                                 if (val <= 2 &&
1481                                     (s->codec_ext_caps & AC97_EXT_DACS)) {
1482                                         /* disable surround and center/lfe
1483                                          * channels in AC'97
1484                                          */
1485                                         u16             ext_stat =
1486                                                 rdcodec(s->codec,
1487                                                         AC97_EXTENDED_STATUS);
1488                                         wrcodec(s->codec,
1489                                                 AC97_EXTENDED_STATUS,
1490                                                 ext_stat | (AC97_EXTSTAT_PRI |
1491                                                             AC97_EXTSTAT_PRJ |
1492                                                             AC97_EXTSTAT_PRK));
1493                                 } else if (val >= 4) {
1494                                         /* enable surround, center/lfe
1495                                          * channels in AC'97
1496                                          */
1497                                         u16             ext_stat =
1498                                                 rdcodec(s->codec,
1499                                                         AC97_EXTENDED_STATUS);
1500                                         ext_stat &= ~AC97_EXTSTAT_PRJ;
1501                                         if (val == 6)
1502                                                 ext_stat &=
1503                                                         ~(AC97_EXTSTAT_PRI |
1504                                                           AC97_EXTSTAT_PRK);
1505                                         wrcodec(s->codec,
1506                                                 AC97_EXTENDED_STATUS,
1507                                                 ext_stat);
1508                                 }
1509
1510                                 s->dma_dac.num_channels = val;
1511                                 if ((ret = prog_dmabuf_dac(s)))
1512                                         return ret;
1513                         }
1514                 }
1515                 return put_user(val, (int *) arg);
1516
1517         case SNDCTL_DSP_GETFMTS:        /* Returns a mask */
1518                 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1519
1520         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1521                 if (get_user(val, (int *) arg))
1522                         return -EFAULT;
1523                 if (val != AFMT_QUERY) {
1524                         if (file->f_mode & FMODE_READ) {
1525                                 stop_adc(s);
1526                                 if (val == AFMT_S16_LE)
1527                                         s->dma_adc.sample_size = 16;
1528                                 else {
1529                                         val = AFMT_U8;
1530                                         s->dma_adc.sample_size = 8;
1531                                 }
1532                                 if ((ret = prog_dmabuf_adc(s)))
1533                                         return ret;
1534                         }
1535                         if (file->f_mode & FMODE_WRITE) {
1536                                 stop_dac(s);
1537                                 if (val == AFMT_S16_LE)
1538                                         s->dma_dac.sample_size = 16;
1539                                 else {
1540                                         val = AFMT_U8;
1541                                         s->dma_dac.sample_size = 8;
1542                                 }
1543                                 if ((ret = prog_dmabuf_dac(s)))
1544                                         return ret;
1545                         }
1546                 } else {
1547                         if (file->f_mode & FMODE_READ)
1548                                 val = (s->dma_adc.sample_size == 16) ?
1549                                         AFMT_S16_LE : AFMT_U8;
1550                         else
1551                                 val = (s->dma_dac.sample_size == 16) ?
1552                                         AFMT_S16_LE : AFMT_U8;
1553                 }
1554                 return put_user(val, (int *) arg);
1555
1556         case SNDCTL_DSP_POST:
1557                 return 0;
1558
1559         case SNDCTL_DSP_GETTRIGGER:
1560                 val = 0;
1561                 spin_lock_irqsave(&s->lock, flags);
1562                 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1563                         val |= PCM_ENABLE_INPUT;
1564                 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1565                         val |= PCM_ENABLE_OUTPUT;
1566                 spin_unlock_irqrestore(&s->lock, flags);
1567                 return put_user(val, (int *) arg);
1568
1569         case SNDCTL_DSP_SETTRIGGER:
1570                 if (get_user(val, (int *) arg))
1571                         return -EFAULT;
1572                 if (file->f_mode & FMODE_READ) {
1573                         if (val & PCM_ENABLE_INPUT)
1574                                 start_adc(s);
1575                         else
1576                                 stop_adc(s);
1577                 }
1578                 if (file->f_mode & FMODE_WRITE) {
1579                         if (val & PCM_ENABLE_OUTPUT)
1580                                 start_dac(s);
1581                         else
1582                                 stop_dac(s);
1583                 }
1584                 return 0;
1585
1586         case SNDCTL_DSP_GETOSPACE:
1587                 if (!(file->f_mode & FMODE_WRITE))
1588                         return -EINVAL;
1589                 abinfo.fragsize = s->dma_dac.fragsize;
1590                 spin_lock_irqsave(&s->lock, flags);
1591                 count = s->dma_dac.count;
1592                 count -= dma_count_done(&s->dma_dac);
1593                 spin_unlock_irqrestore(&s->lock, flags);
1594                 if (count < 0)
1595                         count = 0;
1596                 abinfo.bytes = (s->dma_dac.dmasize - count) /
1597                         s->dma_dac.cnt_factor;
1598                 abinfo.fragstotal = s->dma_dac.numfrag;
1599                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1600                 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1601                 return copy_to_user((void *) arg, &abinfo,
1602                                     sizeof(abinfo)) ? -EFAULT : 0;
1603
1604         case SNDCTL_DSP_GETISPACE:
1605                 if (!(file->f_mode & FMODE_READ))
1606                         return -EINVAL;
1607                 abinfo.fragsize = s->dma_adc.fragsize;
1608                 spin_lock_irqsave(&s->lock, flags);
1609                 count = s->dma_adc.count;
1610                 count += dma_count_done(&s->dma_adc);
1611                 spin_unlock_irqrestore(&s->lock, flags);
1612                 if (count < 0)
1613                         count = 0;
1614                 abinfo.bytes = count / s->dma_adc.cnt_factor;
1615                 abinfo.fragstotal = s->dma_adc.numfrag;
1616                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1617                 return copy_to_user((void *) arg, &abinfo,
1618                                     sizeof(abinfo)) ? -EFAULT : 0;
1619
1620         case SNDCTL_DSP_NONBLOCK:
1621                 file->f_flags |= O_NONBLOCK;
1622                 return 0;
1623
1624         case SNDCTL_DSP_GETODELAY:
1625                 if (!(file->f_mode & FMODE_WRITE))
1626                         return -EINVAL;
1627                 spin_lock_irqsave(&s->lock, flags);
1628                 count = s->dma_dac.count;
1629                 count -= dma_count_done(&s->dma_dac);
1630                 spin_unlock_irqrestore(&s->lock, flags);
1631                 if (count < 0)
1632                         count = 0;
1633                 count /= s->dma_dac.cnt_factor;
1634                 return put_user(count, (int *) arg);
1635
1636         case SNDCTL_DSP_GETIPTR:
1637                 if (!(file->f_mode & FMODE_READ))
1638                         return -EINVAL;
1639                 spin_lock_irqsave(&s->lock, flags);
1640                 cinfo.bytes = s->dma_adc.total_bytes;
1641                 count = s->dma_adc.count;
1642                 if (!s->dma_adc.stopped) {
1643                         diff = dma_count_done(&s->dma_adc);
1644                         count += diff;
1645                         cinfo.bytes += diff;
1646                         cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
1647                                 virt_to_phys(s->dma_adc.rawbuf);
1648                 } else
1649                         cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1650                                 virt_to_phys(s->dma_adc.rawbuf);
1651                 if (s->dma_adc.mapped)
1652                         s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1653                 spin_unlock_irqrestore(&s->lock, flags);
1654                 if (count < 0)
1655                         count = 0;
1656                 cinfo.blocks = count >> s->dma_adc.fragshift;
1657                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1658
1659         case SNDCTL_DSP_GETOPTR:
1660                 if (!(file->f_mode & FMODE_READ))
1661                         return -EINVAL;
1662                 spin_lock_irqsave(&s->lock, flags);
1663                 cinfo.bytes = s->dma_dac.total_bytes;
1664                 count = s->dma_dac.count;
1665                 if (!s->dma_dac.stopped) {
1666                         diff = dma_count_done(&s->dma_dac);
1667                         count -= diff;
1668                         cinfo.bytes += diff;
1669                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1670                                 virt_to_phys(s->dma_dac.rawbuf);
1671                 } else
1672                         cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1673                                 virt_to_phys(s->dma_dac.rawbuf);
1674                 if (s->dma_dac.mapped)
1675                         s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1676                 spin_unlock_irqrestore(&s->lock, flags);
1677                 if (count < 0)
1678                         count = 0;
1679                 cinfo.blocks = count >> s->dma_dac.fragshift;
1680                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1681
1682         case SNDCTL_DSP_GETBLKSIZE:
1683                 if (file->f_mode & FMODE_WRITE)
1684                         return put_user(s->dma_dac.fragsize, (int *) arg);
1685                 else
1686                         return put_user(s->dma_adc.fragsize, (int *) arg);
1687
1688         case SNDCTL_DSP_SETFRAGMENT:
1689                 if (get_user(val, (int *) arg))
1690                         return -EFAULT;
1691                 if (file->f_mode & FMODE_READ) {
1692                         stop_adc(s);
1693                         s->dma_adc.ossfragshift = val & 0xffff;
1694                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1695                         if (s->dma_adc.ossfragshift < 4)
1696                                 s->dma_adc.ossfragshift = 4;
1697                         if (s->dma_adc.ossfragshift > 15)
1698                                 s->dma_adc.ossfragshift = 15;
1699                         if (s->dma_adc.ossmaxfrags < 4)
1700                                 s->dma_adc.ossmaxfrags = 4;
1701                         if ((ret = prog_dmabuf_adc(s)))
1702                                 return ret;
1703                 }
1704                 if (file->f_mode & FMODE_WRITE) {
1705                         stop_dac(s);
1706                         s->dma_dac.ossfragshift = val & 0xffff;
1707                         s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1708                         if (s->dma_dac.ossfragshift < 4)
1709                                 s->dma_dac.ossfragshift = 4;
1710                         if (s->dma_dac.ossfragshift > 15)
1711                                 s->dma_dac.ossfragshift = 15;
1712                         if (s->dma_dac.ossmaxfrags < 4)
1713                                 s->dma_dac.ossmaxfrags = 4;
1714                         if ((ret = prog_dmabuf_dac(s)))
1715                                 return ret;
1716                 }
1717                 return 0;
1718
1719         case SNDCTL_DSP_SUBDIVIDE:
1720                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1721                     (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1722                         return -EINVAL;
1723                 if (get_user(val, (int *) arg))
1724                         return -EFAULT;
1725                 if (val != 1 && val != 2 && val != 4)
1726                         return -EINVAL;
1727                 if (file->f_mode & FMODE_READ) {
1728                         stop_adc(s);
1729                         s->dma_adc.subdivision = val;
1730                         if ((ret = prog_dmabuf_adc(s)))
1731                                 return ret;
1732                 }
1733                 if (file->f_mode & FMODE_WRITE) {
1734                         stop_dac(s);
1735                         s->dma_dac.subdivision = val;
1736                         if ((ret = prog_dmabuf_dac(s)))
1737                                 return ret;
1738                 }
1739                 return 0;
1740
1741         case SOUND_PCM_READ_RATE:
1742                 return put_user((file->f_mode & FMODE_READ) ?
1743                                 s->dma_adc.sample_rate :
1744                                 s->dma_dac.sample_rate,
1745                                 (int *)arg);
1746
1747         case SOUND_PCM_READ_CHANNELS:
1748                 if (file->f_mode & FMODE_READ)
1749                         return put_user(s->dma_adc.num_channels, (int *)arg);
1750                 else
1751                         return put_user(s->dma_dac.num_channels, (int *)arg);
1752
1753         case SOUND_PCM_READ_BITS:
1754                 if (file->f_mode & FMODE_READ)
1755                         return put_user(s->dma_adc.sample_size, (int *)arg);
1756                 else
1757                         return put_user(s->dma_dac.sample_size, (int *)arg);
1758
1759         case SOUND_PCM_WRITE_FILTER:
1760         case SNDCTL_DSP_SETSYNCRO:
1761         case SOUND_PCM_READ_FILTER:
1762                 return -EINVAL;
1763         }
1764
1765         return mixdev_ioctl(s->codec, cmd, arg);
1766 }
1767
1768
1769 static int
1770 au1550_open(struct inode *inode, struct file *file)
1771 {
1772         int             minor = MINOR(inode->i_rdev);
1773         DECLARE_WAITQUEUE(wait, current);
1774         struct au1550_state *s = &au1550_state;
1775         int             ret;
1776
1777 #ifdef DEBUG
1778         if (file->f_flags & O_NONBLOCK)
1779                 pr_debug("open: non-blocking\n");
1780         else
1781                 pr_debug("open: blocking\n");
1782 #endif
1783
1784         file->private_data = s;
1785         /* wait for device to become free */
1786         down(&s->open_sem);
1787         while (s->open_mode & file->f_mode) {
1788                 if (file->f_flags & O_NONBLOCK) {
1789                         up(&s->open_sem);
1790                         return -EBUSY;
1791                 }
1792                 add_wait_queue(&s->open_wait, &wait);
1793                 __set_current_state(TASK_INTERRUPTIBLE);
1794                 up(&s->open_sem);
1795                 schedule();
1796                 remove_wait_queue(&s->open_wait, &wait);
1797                 set_current_state(TASK_RUNNING);
1798                 if (signal_pending(current))
1799                         return -ERESTARTSYS;
1800                 down(&s->open_sem);
1801         }
1802
1803         stop_dac(s);
1804         stop_adc(s);
1805
1806         if (file->f_mode & FMODE_READ) {
1807                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1808                         s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1809                 s->dma_adc.num_channels = 1;
1810                 s->dma_adc.sample_size = 8;
1811                 set_adc_rate(s, 8000);
1812                 if ((minor & 0xf) == SND_DEV_DSP16)
1813                         s->dma_adc.sample_size = 16;
1814         }
1815
1816         if (file->f_mode & FMODE_WRITE) {
1817                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1818                         s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1819                 s->dma_dac.num_channels = 1;
1820                 s->dma_dac.sample_size = 8;
1821                 set_dac_rate(s, 8000);
1822                 if ((minor & 0xf) == SND_DEV_DSP16)
1823                         s->dma_dac.sample_size = 16;
1824         }
1825
1826         if (file->f_mode & FMODE_READ) {
1827                 if ((ret = prog_dmabuf_adc(s)))
1828                         return ret;
1829         }
1830         if (file->f_mode & FMODE_WRITE) {
1831                 if ((ret = prog_dmabuf_dac(s)))
1832                         return ret;
1833         }
1834
1835         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1836         up(&s->open_sem);
1837         init_MUTEX(&s->sem);
1838         return 0;
1839 }
1840
1841 static int
1842 au1550_release(struct inode *inode, struct file *file)
1843 {
1844         struct au1550_state *s = (struct au1550_state *)file->private_data;
1845
1846         lock_kernel();
1847
1848         if (file->f_mode & FMODE_WRITE) {
1849                 unlock_kernel();
1850                 drain_dac(s, file->f_flags & O_NONBLOCK);
1851                 lock_kernel();
1852         }
1853
1854         down(&s->open_sem);
1855         if (file->f_mode & FMODE_WRITE) {
1856                 stop_dac(s);
1857                 kfree(s->dma_dac.rawbuf);
1858                 s->dma_dac.rawbuf = NULL;
1859         }
1860         if (file->f_mode & FMODE_READ) {
1861                 stop_adc(s);
1862                 kfree(s->dma_adc.rawbuf);
1863                 s->dma_adc.rawbuf = NULL;
1864         }
1865         s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1866         up(&s->open_sem);
1867         wake_up(&s->open_wait);
1868         unlock_kernel();
1869         return 0;
1870 }
1871
1872 static /*const */ struct file_operations au1550_audio_fops = {
1873         owner:          THIS_MODULE,
1874         llseek:         au1550_llseek,
1875         read:           au1550_read,
1876         write:          au1550_write,
1877         poll:           au1550_poll,
1878         ioctl:          au1550_ioctl,
1879         mmap:           au1550_mmap,
1880         open:           au1550_open,
1881         release:        au1550_release,
1882 };
1883
1884 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1885 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1886
1887 static int __devinit
1888 au1550_probe(void)
1889 {
1890         struct au1550_state *s = &au1550_state;
1891         int             val;
1892
1893         memset(s, 0, sizeof(struct au1550_state));
1894
1895         init_waitqueue_head(&s->dma_adc.wait);
1896         init_waitqueue_head(&s->dma_dac.wait);
1897         init_waitqueue_head(&s->open_wait);
1898         init_MUTEX(&s->open_sem);
1899         spin_lock_init(&s->lock);
1900
1901         s->codec = ac97_alloc_codec();
1902         if(s->codec == NULL) {
1903                 err("Out of memory");
1904                 return -1;
1905         }
1906         s->codec->private_data = s;
1907         s->codec->id = 0;
1908         s->codec->codec_read = rdcodec;
1909         s->codec->codec_write = wrcodec;
1910         s->codec->codec_wait = waitcodec;
1911
1912         if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1913                             0x30, "Au1550 AC97")) {
1914                 err("AC'97 ports in use");
1915         }
1916
1917         /* Allocate the DMA Channels
1918         */
1919         if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1920             DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1921                 err("Can't get DAC DMA");
1922                 goto err_dma1;
1923         }
1924         au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1925         if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1926                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1927                 err("Can't get DAC DMA descriptors");
1928                 goto err_dma1;
1929         }
1930
1931         if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1932             DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1933                 err("Can't get ADC DMA");
1934                 goto err_dma2;
1935         }
1936         au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1937         if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1938                                         NUM_DBDMA_DESCRIPTORS) == 0) {
1939                 err("Can't get ADC DMA descriptors");
1940                 goto err_dma2;
1941         }
1942
1943         pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1944
1945         /* register devices */
1946
1947         if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1948                 goto err_dev1;
1949         if ((s->codec->dev_mixer =
1950              register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1951                 goto err_dev2;
1952
1953         /* The GPIO for the appropriate PSC was configured by the
1954          * board specific start up.
1955          *
1956          * configure PSC for AC'97
1957          */
1958         au_writel(0, AC97_PSC_CTRL);    /* Disable PSC */
1959         au_sync();
1960         au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1961         au_sync();
1962
1963         /* cold reset the AC'97
1964         */
1965         au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1966         au_sync();
1967         au1550_delay(10);
1968         au_writel(0, PSC_AC97RST);
1969         au_sync();
1970
1971         /* need to delay around 500msec(bleech) to give
1972            some CODECs enough time to wakeup */
1973         au1550_delay(500);
1974
1975         /* warm reset the AC'97 to start the bitclk
1976         */
1977         au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1978         au_sync();
1979         udelay(100);
1980         au_writel(0, PSC_AC97RST);
1981         au_sync();
1982
1983         /* Enable PSC
1984         */
1985         au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
1986         au_sync();
1987
1988         /* Wait for PSC ready.
1989         */
1990         do {
1991                 val = readl((void *)PSC_AC97STAT);
1992                 au_sync();
1993         } while ((val & PSC_AC97STAT_SR) == 0);
1994
1995         /* Configure AC97 controller.
1996          * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
1997          */
1998         val = PSC_AC97CFG_SET_LEN(16);
1999         val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2000
2001         /* Enable device so we can at least
2002          * talk over the AC-link.
2003          */
2004         au_writel(val, PSC_AC97CFG);
2005         au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2006         au_sync();
2007         val |= PSC_AC97CFG_DE_ENABLE;
2008         au_writel(val, PSC_AC97CFG);
2009         au_sync();
2010
2011         /* Wait for Device ready.
2012         */
2013         do {
2014                 val = readl((void *)PSC_AC97STAT);
2015                 au_sync();
2016         } while ((val & PSC_AC97STAT_DR) == 0);
2017
2018         /* codec init */
2019         if (!ac97_probe_codec(s->codec))
2020                 goto err_dev3;
2021
2022         s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2023         s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2024         pr_info("AC'97 Base/Extended ID = %04x/%04x",
2025              s->codec_base_caps, s->codec_ext_caps);
2026
2027         if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2028                 /* codec does not support VRA
2029                 */
2030                 s->no_vra = 1;
2031         } else if (!vra) {
2032                 /* Boot option says disable VRA
2033                 */
2034                 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2035                 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2036                         ac97_extstat & ~AC97_EXTSTAT_VRA);
2037                 s->no_vra = 1;
2038         }
2039         if (s->no_vra)
2040                 pr_info("no VRA, interpolating and decimating");
2041
2042         /* set mic to be the recording source */
2043         val = SOUND_MASK_MIC;
2044         mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2045                      (unsigned long) &val);
2046
2047         return 0;
2048
2049  err_dev3:
2050         unregister_sound_mixer(s->codec->dev_mixer);
2051  err_dev2:
2052         unregister_sound_dsp(s->dev_audio);
2053  err_dev1:
2054         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2055  err_dma2:
2056         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2057  err_dma1:
2058         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2059
2060         ac97_release_codec(s->codec);
2061         return -1;
2062 }
2063
2064 static void __devinit
2065 au1550_remove(void)
2066 {
2067         struct au1550_state *s = &au1550_state;
2068
2069         if (!s)
2070                 return;
2071         synchronize_irq();
2072         au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2073         au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2074         release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2075         unregister_sound_dsp(s->dev_audio);
2076         unregister_sound_mixer(s->codec->dev_mixer);
2077         ac97_release_codec(s->codec);
2078 }
2079
2080 static int __init
2081 init_au1550(void)
2082 {
2083         return au1550_probe();
2084 }
2085
2086 static void __exit
2087 cleanup_au1550(void)
2088 {
2089         au1550_remove();
2090 }
2091
2092 module_init(init_au1550);
2093 module_exit(cleanup_au1550);
2094
2095 #ifndef MODULE
2096
2097 static int __init
2098 au1550_setup(char *options)
2099 {
2100         char           *this_opt;
2101
2102         if (!options || !*options)
2103                 return 0;
2104
2105         while ((this_opt = strsep(&options, ","))) {
2106                 if (!*this_opt)
2107                         continue;
2108                 if (!strncmp(this_opt, "vra", 3)) {
2109                         vra = 1;
2110                 }
2111         }
2112
2113         return 1;
2114 }
2115
2116 __setup("au1550_audio=", au1550_setup);
2117
2118 #endif /* MODULE */